// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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/ {
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rockchip_amp: rockchip-amp {
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compatible = "rockchip,rk3568-amp";
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>,
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<&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>,
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<&cru ACLK_MCU>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart4m1_xfer>;
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status = "okay";
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amp_cpus: amp-cpus {
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amp-cpu3 {
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id = <0x0 0x300>;
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entry = <0x0 0x2800000>;
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boot-on = <0>;
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mode = <0>;
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};
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* remote amp core address */
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amp_shmem_reserved: amp-shmem@7800000 {
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reg = <0x0 0x7800000 0x0 0x400000>;
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no-map;
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};
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rpmsg_reserved: rpmsg@7c00000 {
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reg = <0x0 0x7c00000 0x0 0x400000>;
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no-map;
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};
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rpmsg_dma_reserved: rpmsg-dma@8000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x8000000 0x0 0x100000>;
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no-map;
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};
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/* mcu address */
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mcu_reserved: mcu@8200000 {
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reg = <0x0 0x8200000 0x0 0x100000>;
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no-map;
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};
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};
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rpmsg: rpmsg@7c00000 {
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compatible = "rockchip,rpmsg";
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mbox-names = "rpmsg-rx", "rpmsg-tx";
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mboxes = <&mailbox 0 &mailbox 3>;
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rockchip,vdev-nums = <1>;
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rockchip,link-id = <0x03>;
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reg = <0x0 0x7c00000 0x0 0x20000>;
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memory-region = <&rpmsg_dma_reserved>;
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status = "okay";
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};
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};
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&mailbox {
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rockchip,txpoll-period-ms = <1>;
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status = "okay";
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};
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