// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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/{
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_vehicle: drm-vehicle@0{
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compatible = "shared-dma-pool";
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inactive;
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reusable;
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reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M
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linux,cma-default;
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};
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};
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gpio_det: gpio-det {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&vehicle_gpios>;
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/*if use the reverse, please config this*/
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car-reverse {
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car-reverse-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
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linux,debounce-ms = <5>;
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label = "car-reverse";
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gpio,wakeup;
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};
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};
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vehicle: vehicle {
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compatible = "rockchip,vehicle";
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status = "okay";
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// pinctrl-names = "default";
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// pinctrl-0 = <&camm0_clk0_out>;
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clocks = <&cru ACLK_VICAP>,
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<&cru HCLK_VICAP>,
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<&cru DCLK_VICAP>,
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<&cru CSIRX0_CLK_DATA>,
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<&cru CSIRX1_CLK_DATA>,
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<&cru CSIRX2_CLK_DATA>,
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<&cru CSIRX3_CLK_DATA>;
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clock-names = "aclk_cif",
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"hclk_cif",
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"dclk_cif",
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"csirx0_data",
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"csirx1_data",
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"csirx2_data",
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"csirx3_data";
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resets = <&cru SRST_A_VICAP>,
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<&cru SRST_H_VICAP>,
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<&cru SRST_D_VICAP>,
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<&cru SRST_I0_VICAP>,
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<&cru SRST_I1_VICAP>,
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<&cru SRST_I2_VICAP>,
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<&cru SRST_I3_VICAP>;
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reset-names = "rst_cif_a",
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"rst_cif_h",
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"rst_cif_d",
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"rst_cif_i0",
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"rst_cif_i1",
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"rst_cif_i2",
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"rst_cif_i3";
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power-domains = <&power RK3562_PD_VI>;
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cif,drop-frames = <4>; //frames to drop
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cif,chip-id = <2>; /*0:rk3568 1:rk3588 2:rk3562*/
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rockchip,grf = <&sys_grf>;
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rockchip,cru = <&cru>;
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rockchip,cif = <&rkcif>;
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rockchip,gpio-det = <&gpio_det>;
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rockchip,cif-sensor = <&cif_sensor>;
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rockchip,cif-phy = <&cif_phy>;
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ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25
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/*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/
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vehicle,rotate-mirror = <0x00>;
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vehicle,crtc_name = "video_port0";
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vehicle,plane_name = "Esmart0-win0";
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};
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cif_phy: cif_phy {
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status = "okay";
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csi2_dphy0 {
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status = "okay";
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clocks = <&cru CLK_CAM0_OUT2IO>,
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<&cru PCLK_CSIPHY0>,
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<&cru PCLK_CSIHOST0>;
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clock-names = "xvclk",
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"pclk",
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"pclk_csi2host";
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resets = <&cru SRST_P_CSIPHY0>,
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<&cru SRST_P_CSIHOST0>;
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reset-names = "srst_p_csiphy",
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"srst_csihost_p";
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csihost-idx = <0>;
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rockchip,csi2-dphy = <&csi2_dphy0_hw>;
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rockchip,csi2 = <&mipi0_csi2>;
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};
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csi2_dphy3 {
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status = "disabled";
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clocks = <&cru CLK_CAM2_OUT2IO>,
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<&cru PCLK_CSIPHY1>,
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<&cru PCLK_CSIHOST2>;
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clock-names = "xvclk",
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"pclk",
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"pclk_csi2host";
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resets = <&cru SRST_P_CSIPHY1>,
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<&cru SRST_P_CSIHOST2>;
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reset-names = "srst_p_csiphy",
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"srst_csihost_p";
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csihost-idx = <2>;
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rockchip,csi2-dphy = <&csi2_dphy1_hw>;
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rockchip,csi2 = <&mipi2_csi2>;
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};
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};
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cif_sensor: cif_sensor {
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compatible = "rockchip,sensor";
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status = "okay";
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nvp6324 {
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status = "okay";
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// dphy0
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powerdown-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
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pwdn_active = <1>;
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reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
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rst_active = <1>;
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// dphy3
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// powerdown-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
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// pwdn_active = <1>;
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// reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
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// rst_active = <1>;
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orientation = <90>;
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i2c_add = <0x60>;
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i2c_chl = <4>;
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cif_chl = <0>;
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ad_chl = <0>;
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mclk_rate = <24>;
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rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>;
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};
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};
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};
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&display_subsystem {
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memory-region = <&drm_logo>, <&drm_vehicle>;
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memory-region-names = "drm-logo", "drm-vehicle";
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};
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&i2c4 {
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status = "okay";
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};
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&pinctrl {
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vehicle {
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vehicle_gpios: vehicle-pins {
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/* gpios */
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rockchip,pins =
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/* car-reverse */
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<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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