// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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/*
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* This define is for support double show any dclk frequency.
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* dclk_vop will have a exclusive pll as parent.
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* set dclk_vop will change the pll rate as well.
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*/
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#ifdef RK3399_TWO_PLL_FOR_VOP
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&sdhci {
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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assigned-clock-rates = <200000000>;
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};
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&uart0 {
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assigned-clocks = <&cru SCLK_UART0_SRC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&uart1 {
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assigned-clocks = <&cru SCLK_UART_SRC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&uart2 {
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assigned-clocks = <&cru SCLK_UART_SRC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&uart3 {
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assigned-clocks = <&cru SCLK_UART_SRC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&uart4 {
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assigned-clocks = <&pmucru SCLK_UART4_SRC>;
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assigned-clock-parents = <&pmucru PLL_PPLL>;
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};
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&spdif {
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assigned-clocks = <&cru SCLK_SPDIF_DIV>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&i2s0{
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assigned-clocks = <&cru SCLK_I2S0_DIV>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&i2s1 {
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assigned-clocks = <&cru SCLK_I2S1_DIV>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&i2s2 {
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assigned-clocks = <&cru SCLK_I2S2_DIV>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&cru {
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assigned-clocks =
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<&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>,
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<&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>,
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<&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
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<&cru HCLK_SD>, <&cru SCLK_VDU_CA>,
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<&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
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<&cru FCLK_CM0S>, <&cru ACLK_CCI>,
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<&cru PCLK_ALIVE>, <&cru ACLK_GMAC>,
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<&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>,
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<&cru ARMCLKL>, <&cru ARMCLKB>,
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<&cru PLL_NPLL>, <&cru ACLK_GPU>,
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<&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
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<&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>,
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<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
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<&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>,
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<&cru PCLK_PERILP1>, <&cru SCLK_I2C1>,
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<&cru SCLK_I2C2>, <&cru SCLK_I2C3>,
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<&cru SCLK_I2C5>, <&cru SCLK_I2C6>,
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<&cru SCLK_I2C7>, <&cru SCLK_SPI0>,
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<&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
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<&cru SCLK_SPI4>, <&cru SCLK_SPI5>,
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<&cru ACLK_GIC>, <&cru ACLK_ISP0>,
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<&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>,
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<&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>,
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<&cru ACLK_HDCP>, <&cru ACLK_VIO>,
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<&cru HCLK_SD>, <&cru SCLK_CRYPTO0>,
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<&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>,
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<&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
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<&cru ACLK_IEP>, <&cru ACLK_RGA>,
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<&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>,
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<&cru ACLK_VCODEC>, <&cru PCLK_DDR>,
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<&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>,
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<&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
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<&cru FCLK_CM0S>, <&cru ACLK_CCI>,
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<&cru PCLK_ALIVE>, <&cru SCLK_CS>,
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<&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>,
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<&cru HCLK_VOP0>, <&cru ACLK_VOP1>,
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<&cru HCLK_VOP1>;
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assigned-clock-rates =
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<75000000>, <50000000>,
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<50000000>, <50000000>,
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<50000000>, <100000000>,
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<50000000>, <150000000>,
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<150000000>, <150000000>,
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<50000000>, <150000000>,
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<50000000>, <100000000>,
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<75000000>, <75000000>,
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<816000000>, <816000000>,
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<600000000>, <200000000>,
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<800000000>, <150000000>,
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<75000000>, <37500000>,
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<300000000>, <100000000>,
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<50000000>, <100000000>,
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<50000000>, <100000000>,
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<100000000>, <100000000>,
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<100000000>, <100000000>,
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<100000000>, <50000000>,
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<50000000>, <50000000>,
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<50000000>, <50000000>,
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<200000000>, <400000000>,
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<400000000>, <100000000>,
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<100000000>, <100000000>,
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<400000000>, <400000000>,
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<200000000>, <100000000>,
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<200000000>, <200000000>,
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<100000000>, <400000000>,
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<400000000>, <400000000>,
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<400000000>, <300000000>,
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<400000000>, <200000000>,
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<400000000>, <300000000>,
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<300000000>, <300000000>,
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<300000000>, <600000000>,/* aclk_cci */
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<100000000>, <150000000>,
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<150000000>, <400000000>,
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<100000000>, <400000000>,
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<100000000>;
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};
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#endif
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