// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "px30.dtsi"
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&cpu0_opp_table {
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/delete-node/ opp-408000000;
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/delete-node/ opp-600000000;
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/delete-node/ opp-816000000;
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/delete-node/ opp-1008000000;
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/delete-node/ opp-1200000000;
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/delete-node/ opp-1248000000;
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/delete-node/ opp-1296000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-1512000000;
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1125000 1125000 1125000>;
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clock-latency-ns = <40000>;
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};
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};
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&cru {
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assigned-clocks = <&cru PLL_NPLL>;
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assigned-clock-rates = <1040000000>;
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};
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&display_subsystem {
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status = "disabled";
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ports = <&vopb_out>, <&vopl_out>;
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logo-memory-region = <&drm_logo>;
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route {
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route_lvds: route-lvds {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_lvds>;
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};
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route_dsi: route-dsi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_dsi>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_rgb>;
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};
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};
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};
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&dmc_opp_table {
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/delete-node/ opp-194000000;
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/delete-node/ opp-328000000;
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/delete-node/ opp-450000000;
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/delete-node/ opp-528000000;
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/delete-node/ opp-666000000;
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opp-666000000 {
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opp-hz = /bits/ 64 <666000000>;
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opp-microvolt = <1050000>;
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};
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};
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&gpu_opp_table {
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/delete-node/ opp-200000000;
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/delete-node/ opp-300000000;
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/delete-node/ opp-400000000;
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/delete-node/ opp-480000000;
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opp-520000000 {
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opp-hz = /bits/ 64 <520000000>;
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opp-microvolt = <1125000>;
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};
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};
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&rgb {
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phys = <&video_phy>;
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phy-names = "phy";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&lcdc_m1_rgb_pins>;
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pinctrl-1 = <&lcdc_m1_sleep_pins>;
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};
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&pinctrl {
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lcdc {
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lcdc_m1_rgb_pins: lcdc-m1-rgb-pins {
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rockchip,pins =
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<3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */
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<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */
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<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */
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<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */
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<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */
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<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */
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<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */
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<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */
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<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */
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<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */
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<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */
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<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */
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<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */
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<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */
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<3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */
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<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */
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<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */
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<3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */
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};
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lcdc_m1_sleep_pins: lcdc-m1-sleep-pins {
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rockchip,pins =
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<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
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<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */
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<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */
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<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */
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<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */
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<3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */
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<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
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<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
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<3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
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<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
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<3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
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<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
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<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
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<3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
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<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
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<3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
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<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
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<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */
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};
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};
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};
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