/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/ {
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff130000 kpti=0 coherent_pool=1m";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,signal-irq = <159>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <0>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
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status = "okay";
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};
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firmware {
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firmware_android: android {};
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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secure_memory: secure-memory@20000000 {
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compatible = "rockchip,secure-memory";
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reg = <0x0 0x20000000 0x0 0x0>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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};
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&display_subsystem {
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logo-memory-region = <&drm_logo>;
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status = "okay";
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secure-memory-region = <&secure_memory>;
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route {
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route_hdmi: route-hdmi {
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status = "okay";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "fullscreen";
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charge_logo,mode = "fullscreen";
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connect = <&vop_out_hdmi>;
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};
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route_tve: route-tve {
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status = "okay";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "fullscreen";
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charge_logo,mode = "fullscreen";
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connect = <&vop_out_tve>;
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};
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};
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};
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&rng {
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status = "okay";
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};
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