// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "px30.dtsi"
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#include "rk3326-linux.dtsi"
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#include "px30-evb-ddr3-v10.dtsi"
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/ {
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model = "Rockchip linux PX30 evb ddr3 board";
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compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30";
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/delete-node/ test-power;
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};
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&dsi {
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status = "okay";
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panel@0 {
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compatible = "sitronix,st7703", "simple-panel-dsi";
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reg = <0>;
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power-supply = <&vcc3v3_lcd>;
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backlight = <&backlight>;
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prepare-delay-ms = <2>;
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reset-delay-ms = <1>;
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init-delay-ms = <20>;
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enable-delay-ms = <120>;
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disable-delay-ms = <50>;
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unprepare-delay-ms = <20>;
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width-mm = <68>;
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height-mm = <121>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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dsi,lanes = <4>;
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panel-init-sequence = [
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05 fa 01 11
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39 00 04 b9 f1 12 83
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39 00 1c ba 33 81 05 f9 0e 0e 00 00 00
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00 00 00 00 00 44 25 00 91 0a
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00 00 02 4f 01 00 00 37
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15 00 02 b8 25
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39 00 04 bf 02 11 00
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39 00 0b b3 0c 10 0a 50 03 ff 00 00 00
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00
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39 00 0a c0 73 73 50 50 00 00 08 70 00
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15 00 02 bc 46
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15 00 02 cc 0b
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15 00 02 b4 80
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39 00 04 b2 c8 12 30
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39 00 0f e3 07 07 0b 0b 03 0b 00 00 00
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00 ff 00 c0 10
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39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67
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77 33 33
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39 00 07 c6 00 00 ff ff 01 ff
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39 00 03 b5 09 09
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39 00 03 b6 87 95
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39 00 40 e9 c2 10 05 05 10 05 a0 12 31
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23 3f 81 0a a0 37 18 00 80 01
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00 00 00 00 80 01 00 00 00 48
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f8 86 42 08 88 88 80 88 88 88
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58 f8 87 53 18 88 88 81 88 88
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88 00 00 00 01 00 00 00 00 00
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00 00 00 00
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39 00 3e ea 00 1a 00 00 00 00 02 00 00
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00 00 00 1f 88 81 35 78 88 88
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85 88 88 88 0f 88 80 24 68 88
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88 84 88 88 88 23 10 00 00 1c
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00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 30 05 a0 00 00
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00 00
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39 00 23 e0 00 06 08 2a 31 3f 38 36 07
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0c 0d 11 13 12 13 11 18 00 06
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08 2a 31 3f 38 36 07 0c 0d 11
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13 12 13 11 18
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05 32 01 29
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];
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panel-exit-sequence = [
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05 00 01 28
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05 00 01 10
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];
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <64000000>;
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hactive = <720>;
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vactive = <1280>;
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hfront-porch = <40>;
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hsync-len = <10>;
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hback-porch = <40>;
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vfront-porch = <22>;
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vsync-len = <4>;
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vback-porch = <11>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_panel>;
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi_out_panel: endpoint {
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remote-endpoint = <&panel_in_dsi>;
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};
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};
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};
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};
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