// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*/
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/dts-v1/;
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#include "sparx5_pcb_common.dtsi"
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/{
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aliases {
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i2c0 = &i2c0;
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i2c152 = &i2c152;
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i2c153 = &i2c153;
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i2c154 = &i2c154;
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i2c155 = &i2c155;
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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priority = <200>;
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};
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};
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&gpio {
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i2cmux_pins_i: i2cmux-pins-i {
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pins = "GPIO_35", "GPIO_36",
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"GPIO_50", "GPIO_51";
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function = "twi_scl_m";
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output-low;
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};
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i2cmux_s29: i2cmux-0 {
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pins = "GPIO_35";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_s30: i2cmux-1 {
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pins = "GPIO_36";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_s31: i2cmux-2 {
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pins = "GPIO_50";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_s32: i2cmux-3 {
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pins = "GPIO_51";
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function = "twi_scl_m";
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output-high;
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};
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};
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&spi0 {
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status = "okay";
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spi@0 {
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compatible = "spi-mux";
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mux-controls = <&mux>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>; /* CS0 */
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spi-flash@9 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <8000000>;
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reg = <0x9>; /* SPI */
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};
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};
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};
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&spi0 {
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status = "okay";
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spi@0 {
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compatible = "spi-mux";
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mux-controls = <&mux>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>; /* CS0 */
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spi-flash@9 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <8000000>;
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reg = <0x9>; /* SPI */
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};
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};
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};
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&axi {
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i2c0_imux: i2c0-imux@0 {
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c0>;
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};
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};
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&i2c0_imux {
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pinctrl-names =
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"i2c152", "i2c153", "i2c154", "i2c155",
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"idle";
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pinctrl-0 = <&i2cmux_s29>;
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pinctrl-1 = <&i2cmux_s30>;
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pinctrl-2 = <&i2cmux_s31>;
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pinctrl-3 = <&i2cmux_s32>;
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pinctrl-4 = <&i2cmux_pins_i>;
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i2c152: i2c_sfp1 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c153: i2c_sfp2 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c154: i2c_sfp3 {
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reg = <0x2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c155: i2c_sfp4 {
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reg = <0x3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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