// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* Device tree for the CN9130-DB board.
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*/
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#include "cn9130.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada CN9130-DB";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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i2c0 = &cp0_i2c0;
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp0_eth1;
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ethernet2 = &cp0_eth2;
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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ap0_reg_sd_vccq: ap0_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "ap0_sd_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1 3300000 0x0>;
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};
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cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp0-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
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};
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cp0_usb3_0_phy0: cp0_usb3_phy@0 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp0_reg_usb3_vbus0>;
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};
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cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp0-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
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};
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cp0_usb3_0_phy1: cp0_usb3_phy@1 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp0_reg_usb3_vbus1>;
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};
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cp0_reg_sd_vccq: cp0_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "cp0_sd_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1
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3300000 0x0>;
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};
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cp0_reg_sd_vcc: cp0_sd_vcc@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp0_sd_vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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cp0_sfp_eth0: sfp-eth@0 {
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compatible = "sff,sfp";
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i2c-bus = <&cp0_sfpp0_i2c>;
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los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
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/*
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* SFP cages are unconnected on early PCBs because of an the I2C
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* lanes not being connected. Prevent the port for being
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* unusable by disabling the SFP node.
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*/
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status = "disabled";
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};
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};
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&uart0 {
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status = "okay";
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};
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/* on-board eMMC - U9 */
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&ap_sdhci0 {
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pinctrl-names = "default";
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bus-width = <8>;
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vqmmc-supply = <&ap0_reg_sd_vccq>;
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status = "okay";
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};
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&cp0_crypto {
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status = "disabled";
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};
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&cp0_ethernet {
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status = "okay";
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};
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/* SLM-1521-V2, CON9 */
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&cp0_eth0 {
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status = "disabled";
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phy-mode = "10gbase-kr";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy4 0>;
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managed = "in-band-status";
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sfp = <&cp0_sfp_eth0>;
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};
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/* CON56 */
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&cp0_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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/* CON57 */
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&cp0_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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&cp0_gpio1 {
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status = "okay";
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};
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&cp0_gpio2 {
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status = "okay";
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};
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&cp0_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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clock-frequency = <100000>;
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/* U36 */
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expander0: pca953x@21 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x21>;
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status = "okay";
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};
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/* U42 */
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eeprom0: eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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pagesize = <0x20>;
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};
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/* U38 */
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eeprom1: eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <0x20>;
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};
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};
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&cp0_i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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/* SLM-1521-V2 - U3 */
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i2c-mux@72 { /* verify address - depends on dpr */
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72>;
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cp0_sfpp0_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* U12 */
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cp0_module_expander1: pca9555@21 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x21>;
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};
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};
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};
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};
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&cp0_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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/* U54 */
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&cp0_nand_controller {
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins &nand_rb>;
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "Linux";
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reg = <0x200000 0xe00000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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};
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};
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/* SLM-1521-V2, CON6 */
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&cp0_pcie0 {
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status = "okay";
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num-lanes = <4>;
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num-viewport = <8>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy0 0
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&cp0_comphy1 0
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&cp0_comphy2 0
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&cp0_comphy3 0>;
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};
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&cp0_sata0 {
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status = "okay";
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/* SLM-1521-V2, CON2 */
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sata-port@1 {
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status = "okay";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy5 1>;
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};
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};
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/* CON 28 */
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&cp0_sdhci0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins
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&cp0_sdhci_cd_pins>;
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bus-width = <4>;
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cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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vqmmc-supply = <&cp0_reg_sd_vccq>;
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vmmc-supply = <&cp0_reg_sd_vcc>;
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};
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/* U55 */
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&cp0_spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi0_pins>;
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reg = <0x700680 0x50>;
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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/* On-board MUX does not allow higher frequencies */
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot-0";
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reg = <0x0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem-0";
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reg = <0x200000 0xe00000>;
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};
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};
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};
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};
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
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marvell,pins = "mpp0", "mpp1", "mpp2",
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"mpp3", "mpp4", "mpp5",
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"mpp6", "mpp7", "mpp8",
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"mpp9", "mpp10", "mpp11";
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marvell,function = "ge0";
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};
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cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
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marvell,pins = "mpp44", "mpp45", "mpp46",
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"mpp47", "mpp48", "mpp49",
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"mpp50", "mpp51", "mpp52",
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"mpp53", "mpp54", "mpp55";
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marvell,function = "ge1";
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};
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cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
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marvell,pins = "mpp43";
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marvell,function = "gpio";
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};
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cp0_sdhci_pins: cp0-sdhi-pins-0 {
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marvell,pins = "mpp56", "mpp57", "mpp58",
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"mpp59", "mpp60", "mpp61";
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marvell,function = "sdio";
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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nand_pins: nand-pins {
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marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
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"mpp19", "mpp20", "mpp21", "mpp22",
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"mpp23", "mpp24", "mpp25", "mpp26",
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"mpp27";
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marvell,function = "dev";
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};
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nand_rb: nand-rb {
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marvell,pins = "mpp13";
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marvell,function = "nf";
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};
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};
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};
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&cp0_usb3_0 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy0>;
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phy-names = "usb";
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};
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&cp0_usb3_1 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy1>;
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phy-names = "usb";
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};
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