// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2017 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada AP810.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "Marvell Armada AP810";
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compatible = "marvell,armada-ap810";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0_ap0;
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serial1 = &uart1_ap0;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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ap810-ap0 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space@e8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xe8000000 0x4000000>;
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interrupt-parent = <&gic>;
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gic: interrupt-controller@3000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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reg = <0x3000000 0x10000>, /* GICD */
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<0x3060000 0x100000>, /* GICR */
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<0x00c0000 0x2000>, /* GICC */
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<0x00d0000 0x1000>, /* GICH */
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<0x00e0000 0x2000>; /* GICV */
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gic_its_ap0: interrupt-controller@3040000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x3040000 0x20000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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xor@400000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x400000 0x1000>,
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<0x410000 0x1000>;
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msi-parent = <&gic_its_ap0 0xa0>;
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dma-coherent;
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};
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xor@420000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x420000 0x1000>,
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<0x430000 0x1000>;
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msi-parent = <&gic_its_ap0 0xa1>;
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dma-coherent;
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};
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xor@440000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x440000 0x1000>,
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<0x450000 0x1000>;
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msi-parent = <&gic_its_ap0 0xa2>;
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dma-coherent;
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};
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xor@460000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x460000 0x1000>,
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<0x470000 0x1000>;
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msi-parent = <&gic_its_ap0 0xa3>;
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dma-coherent;
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};
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uart0_ap0: serial@512000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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status = "disabled";
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};
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uart1_ap0: serial@512100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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status = "disabled";
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};
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};
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};
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};
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