// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 SolidRun ltd.
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* Based on Marvell MACCHIATOBin board
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*
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* Device Tree file for SolidRun's ClearFog GT 8K
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*/
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#include "armada-8040.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "SolidRun ClearFog GT 8K";
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compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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aliases {
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ethernet0 = &cp1_eth1;
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ethernet1 = &cp0_eth0;
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ethernet2 = &cp1_eth2;
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};
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v_3_3: regulator-3-3v {
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compatible = "regulator-fixed";
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regulator-name = "v_3_3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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status = "okay";
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};
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v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
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compatible = "regulator-fixed";
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gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_xhci_vbus_pins>;
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regulator-name = "v_5v0_usb3_hst_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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status = "okay";
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};
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sfp_cp0_eth0: sfp-cp0-eth0 {
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compatible = "sff,sfp";
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i2c-bus = <&cp0_i2c1>;
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mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
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maximum-power-milliwatt = <2000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&cp0_led0_pins
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&cp0_led1_pins>;
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pinctrl-names = "default";
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/* No designated function for these LEDs at the moment */
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led0 {
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label = "clearfog-gt-8k:green:led0";
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gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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led1 {
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label = "clearfog-gt-8k:green:led1";
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gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
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pinctrl-names = "default";
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button_0 {
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/* The rear button */
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label = "Rear Button";
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gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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button_1 {
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/* The wps button */
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label = "WPS Button";
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gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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};
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&uart0 {
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status = "okay";
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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};
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&ap_sdhci0 {
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bus-width = <8>;
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no-1-8-v;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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vqmmc-supply = <&v_3_3>;
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};
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&cp0_i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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};
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&cp0_i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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status = "okay";
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};
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&cp0_pinctrl {
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/*
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* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32, 33, 34] pci0/1/2 reset
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* [35-38] CP0 I2C1 and I2C0
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* [39] GPIO reset button
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* [40,41] LED0 and LED1
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* [43] 1512 phy reset
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* [47] USB VBUS EN (active low)
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* [48] FAN PWM
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* [49] SFP+ present signal
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* [50] TPM interrupt
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* [51] WLAN0 disable
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* [52] WLAN1 disable
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* [53] LTE disable
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* [54] NFC reset
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* [55] Micro SD card detect
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* [56-61] Micro SD
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*/
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cp0_pci0_reset_pins: pci0-reset-pins {
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marvell,pins = "mpp32";
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marvell,function = "gpio";
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};
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cp0_pci1_reset_pins: pci1-reset-pins {
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marvell,pins = "mpp33";
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marvell,function = "gpio";
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};
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cp0_pci2_reset_pins: pci2-reset-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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cp0_i2c1_pins: i2c1-pins {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp0_i2c0_pins: i2c0-pins {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp0_gpio_reset_pins: gpio-reset-pins {
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marvell,pins = "mpp39";
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marvell,function = "gpio";
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};
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cp0_led0_pins: led0-pins {
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marvell,pins = "mpp40";
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marvell,function = "gpio";
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};
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cp0_led1_pins: led1-pins {
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marvell,pins = "mpp41";
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marvell,function = "gpio";
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};
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cp0_copper_eth_phy_reset: copper-eth-phy-reset {
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marvell,pins = "mpp43";
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marvell,function = "gpio";
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};
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cp0_xhci_vbus_pins: xhci0-vbus-pins {
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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cp0_fan_pwm_pins: fan-pwm-pins {
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marvell,pins = "mpp48";
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marvell,function = "gpio";
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};
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cp0_sfp_present_pins: sfp-present-pins {
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marvell,pins = "mpp49";
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marvell,function = "gpio";
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};
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cp0_tpm_irq_pins: tpm-irq-pins {
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marvell,pins = "mpp50";
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marvell,function = "gpio";
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};
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cp0_wlan_disable_pins: wlan-disable-pins {
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marvell,pins = "mpp51";
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marvell,function = "gpio";
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};
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cp0_sdhci_pins: sdhci-pins {
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marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
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"mpp60", "mpp61";
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marvell,function = "sdio";
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};
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};
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&cp0_pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
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reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
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phys = <&cp0_comphy0 0>;
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phy-names = "cp0-pcie0-x1-phy";
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status = "okay";
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};
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&cp0_gpio2 {
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sata_reset {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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lte_reset {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_LOW>;
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output-low;
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};
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wlan_disable {
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gpio-hog;
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gpios = <19 GPIO_ACTIVE_LOW>;
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output-low;
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};
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lte_disable {
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gpio-hog;
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gpios = <21 GPIO_ACTIVE_LOW>;
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output-low;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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/* SFP */
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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phys = <&cp0_comphy2 0>;
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sfp = <&sfp_cp0_eth0>;
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};
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&cp0_sdhci0 {
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broken-cd;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins>;
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status = "okay";
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vqmmc-supply = <&v_3_3>;
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};
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&cp0_usb3_1 {
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status = "okay";
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};
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&cp1_pinctrl {
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/*
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* MPP Bus:
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* [0-5] TDM
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* [6] VHV Enable
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* [7] CP1 SPI0 CSn1 (FXS)
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* [8] CP1 SPI0 CSn0 (TPM)
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* [9.11]CP1 SPI0 MOSI/MISO/CLK
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* [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
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* [14] CP1 SPI1 CS0n (64Mb SPI ROM)
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* [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
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* [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
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* [24] Topaz switch reset
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* [26] Buzzer
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* [27] CP1 SMI MDIO
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* [28] CP1 SMI MDC
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* [29] CP0 10G SFP TX Disable
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* [30] WPS button
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* [31] Front panel button
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*/
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cp1_spi1_pins: spi1-pins {
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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cp1_switch_reset_pins: switch-reset-pins {
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marvell,pins = "mpp24";
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marvell,function = "gpio";
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};
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cp1_ge_mdio_pins: ge-mdio-pins {
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marvell,pins = "mpp27", "mpp28";
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marvell,function = "ge";
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};
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cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
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marvell,pins = "mpp29";
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marvell,function = "gpio";
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};
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cp1_wps_button_pins: wps-button-pins {
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marvell,pins = "mpp30";
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marvell,function = "gpio";
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};
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};
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&cp1_sata0 {
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pinctrl-0 = <&cp0_pci1_reset_pins>;
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status = "okay";
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sata-port@1 {
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phys = <&cp1_comphy0 1>;
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phy-names = "cp1-sata0-1-phy";
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};
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};
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&cp1_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_ge_mdio_pins>;
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status = "okay";
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ge_phy: ethernet-phy@0 {
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/* LED0 - GB link
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* LED1 - on: link, blink: activity
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*/
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marvell,reg-init = <3 16 0 0x1017>;
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_copper_eth_phy_reset>;
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reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <10000>;
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};
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switch0: switch0@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_switch_reset_pins>;
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reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-handle = <&switch0phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan3";
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phy-handle = <&switch0phy3>;
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&cp1_eth2>;
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phy-mode = "2500base-x";
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managed = "in-band-status";
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@11 {
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reg = <0x11>;
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};
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switch0phy1: switch0phy1@12 {
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reg = <0x12>;
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};
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switch0phy2: switch0phy2@13 {
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reg = <0x13>;
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};
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switch0phy3: switch0phy3@14 {
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reg = <0x14>;
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};
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};
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};
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};
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&cp1_ethernet {
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status = "okay";
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};
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/* 1G copper */
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&cp1_eth1 {
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status = "okay";
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phy-mode = "sgmii";
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phy = <&ge_phy>;
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phys = <&cp1_comphy3 1>;
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};
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/* Switch uplink */
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&cp1_eth2 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp1_comphy5 2>;
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managed = "in-band-status";
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};
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&cp1_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_spi1_pins>;
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status = "okay";
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spi-flash@0 {
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compatible = "st,w25q32";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&cp1_comphy2 {
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cp1_usbh0_con: connector {
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compatible = "usb-a-connector";
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phy-supply = <&v_5v0_usb3_hst_vbus>;
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};
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};
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&cp1_usb3_0 {
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phys = <&cp1_comphy2 0>;
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phy-names = "cp1-usb3h0-comphy";
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status = "okay";
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};
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