// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada 7040 Development board platform
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-7040.dtsi"
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/ {
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model = "Marvell Armada 7040 DB board";
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compatible = "marvell,armada7040-db", "marvell,armada7040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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aliases {
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp0_eth1;
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ethernet2 = &cp0_eth2;
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};
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cp0_exp_usb3_0_current_regulator: gpio-regulator {
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compatible = "regulator-gpio";
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regulator-name = "cp0-usb3-0-current-regulator";
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regulator-type = "current";
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regulator-min-microamp = <500000>;
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regulator-max-microamp = <900000>;
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gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
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states = <500000 0x0
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900000 0x1>;
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enable-active-high;
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gpios-states = <0>;
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};
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cp0_exp_usb3_1_current_regulator: gpio-regulator {
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compatible = "regulator-gpio";
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regulator-name = "cp0-usb3-1-current-regulator";
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regulator-type = "current";
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regulator-min-microamp = <500000>;
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regulator-max-microamp = <900000>;
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gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
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states = <500000 0x0
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900000 0x1>;
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enable-active-high;
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gpios-states = <0>;
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};
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cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
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vin-supply = <&cp0_exp_usb3_0_current_regulator>;
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};
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cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3h1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
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vin-supply = <&cp0_exp_usb3_1_current_regulator>;
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xce0000>;
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};
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};
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};
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};
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&uart0 {
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status = "okay";
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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};
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&cp0_pcie2 {
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status = "okay";
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phys = <&cp0_comphy5 2>;
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phy-names = "cp0-pcie2-x1-phy";
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};
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&cp0_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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expander0: pca9555@21 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x21>;
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/*
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* IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
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* IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
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* IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
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* IO0_3: USB2_DEVICE_DETECT
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* IO0_4: GPIO_0 IO1_4: SD_Status
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* IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
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* IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
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* IO0_7: IO1_7: SDIO_Vcntrl
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*/
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};
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};
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&cp0_nand_controller {
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/*
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* SPI on CPM and NAND have common pins on this board. We can
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* use only one at a time. To enable the NAND (which will
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* disable the SPI), the "status = "okay";" line have to be
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* added here.
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*/
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pinctrl-0 = <&nand_pins>, <&nand_rb>;
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pinctrl-names = "default";
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nand@0 {
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reg = <0>;
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label = "pxa3xx_nand-0";
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nand-rb = <0>;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "Linux";
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reg = <0x200000 0xe00000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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};
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};
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&cp0_spi1 {
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status = "okay";
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spi-flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xe00000>;
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};
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};
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};
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};
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&cp0_sata0 {
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status = "okay";
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sata-port@1 {
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phys = <&cp0_comphy3 1>;
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phy-names = "cp0-sata0-1-phy";
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};
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};
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&cp0_comphy1 {
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cp0_usbh0_con: connector {
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compatible = "usb-a-connector";
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phy-supply = <&cp0_reg_usb3_0_vbus>;
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};
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};
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&cp0_usb3_0 {
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phys = <&cp0_comphy1 0>;
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phy-names = "cp0-usb3h0-comphy";
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status = "okay";
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};
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&cp0_comphy4 {
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cp0_usbh1_con: connector {
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compatible = "usb-a-connector";
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phy-supply = <&cp0_reg_usb3_1_vbus>;
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};
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};
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&cp0_usb3_1 {
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phys = <&cp0_comphy4 1>;
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phy-names = "cp0-usb3h1-comphy";
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status = "okay";
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};
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&ap_sdhci0 {
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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};
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&cp0_sdhci0 {
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
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};
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&cp0_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth0 {
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status = "okay";
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/* Network PHY */
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phy-mode = "10gbase-kr";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy2 0>;
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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&cp0_eth1 {
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status = "okay";
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/* Network PHY */
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phy = <&phy0>;
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phy-mode = "sgmii";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy0 1>;
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};
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&cp0_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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