// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <asm/arch/sdram.h>
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#include "io_map.h"
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#define IO_TYPE_1_1_16 0 /* up1 1:1 mode 16bit */
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#define IO_TYPE_1_1_32 1 /* up1 1:1 mode 32bit */
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#define IO_TYPE_1_2 2 /* up1 1:2 mode */
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#define IO_TYPE_2 3 /* up2 */
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static u32 io_type;
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/* len should be 16byte align */
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int data_cpu_2_io(void *p, u32 len)
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{
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uchar *val = p;
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uchar buf[CPU_2_IO_ALIGN_LEN];
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u32 i, j;
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if ((len % sizeof(buf)) || !len)
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return -1;
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if (io_type == IO_TYPE_1_2) {
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len /= sizeof(buf);
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for (j = 0; j < len; j++) {
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memset(buf, 0, sizeof(buf));
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for (i = 0; i < sizeof(buf); i++)
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buf[i] = val[(i % 4) * 4 + i / 4 + j * sizeof(buf)];
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memcpy(&val[j * sizeof(buf)], buf, sizeof(buf));
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}
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} else if (io_type == IO_TYPE_1_1_32) {
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len /= 8;
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for (j = 0; j < len; j++) {
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memset(buf, 0, sizeof(buf));
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for (i = 0; i < 8; i++)
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buf[i] = val[(i % 4) * 2 + i / 4 + j * 8];
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memcpy(&val[j * 8], buf, 8);
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}
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}
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/* IO_TYPE_2 and IO_TYPE_1_1_16 do nothing*/
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return 0;
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}
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void data_cpu_2_io_init(void)
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{
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#if defined(CONFIG_ROCKCHIP_RK3036)
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io_type = IO_TYPE_1_1_16;
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#elif defined(CONFIG_ROCKCHIP_RK3228) || \
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defined(CONFIG_ROCKCHIP_RV1108) || \
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defined(CONFIG_ROCKCHIP_RK3368) || \
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defined(CONFIG_ROCKCHIP_RK3366)
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io_type = IO_TYPE_1_2;
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#elif defined(CONFIG_ROCKCHIP_RK3128) || \
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defined(CONFIG_ROCKCHIP_RK3288) || \
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defined(CONFIG_ROCKCHIP_RK3288)
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u32 bw;
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bw = get_ddr_bw();
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if (bw == 2)
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io_type = IO_TYPE_1_1_32;
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else
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io_type = IO_TYPE_1_1_16;
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#elif defined(CONFIG_ROCKCHIP_RK3328) || \
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defined(CONFIG_ROCKCHIP_PX30) || \
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defined(CONFIG_ROCKCHIP_RK1808)
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io_type = IO_TYPE_2;
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#else
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io_type = IO_TYPE_2;
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#endif
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}
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