/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2009 Texas Instruments Inc
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*
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* vpss - video processing subsystem module header file.
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*
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* Include this header file if a driver needs to configure vpss system
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* module. It exports a set of library functions for video drivers to
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* configure vpss system module functions such as clock enable/disable,
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* vpss interrupt mux to arm, and other common vpss system module
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* functions.
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*/
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#ifndef _VPSS_H
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#define _VPSS_H
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/* selector for ccdc input selection on DM355 */
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enum vpss_ccdc_source_sel {
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VPSS_CCDCIN,
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VPSS_HSSIIN,
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VPSS_PGLPBK, /* for DM365 only */
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VPSS_CCDCPG /* for DM365 only */
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};
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struct vpss_sync_pol {
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unsigned int ccdpg_hdpol:1;
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unsigned int ccdpg_vdpol:1;
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};
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struct vpss_pg_frame_size {
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short hlpfr;
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short pplen;
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};
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/* Used for enable/disable VPSS Clock */
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enum vpss_clock_sel {
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/* DM355/DM365 */
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VPSS_CCDC_CLOCK,
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VPSS_IPIPE_CLOCK,
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VPSS_H3A_CLOCK,
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VPSS_CFALD_CLOCK,
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/*
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* When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
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* following applies:-
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* en = 0 selects ENC_CLK
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* en = 1 selects ENC_CLK/2
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*/
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VPSS_VENC_CLOCK_SEL,
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VPSS_VPBE_CLOCK,
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/* DM365 only clocks */
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VPSS_IPIPEIF_CLOCK,
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VPSS_RSZ_CLOCK,
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VPSS_BL_CLOCK,
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/*
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* When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
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* following applies:-
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* en = 0 disable internal PCLK
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* en = 1 enables internal PCLK
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*/
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VPSS_PCLK_INTERNAL,
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/*
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* When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
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* following applies:-
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* en = 0 enables MMR clock
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* en = 1 enables VPSS clock
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*/
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VPSS_PSYNC_CLOCK_SEL,
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VPSS_LDC_CLOCK_SEL,
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VPSS_OSD_CLOCK_SEL,
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VPSS_FDIF_CLOCK,
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VPSS_LDC_CLOCK
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};
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/* select input to ccdc on dm355 */
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int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
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/* enable/disable a vpss clock, 0 - success, -1 - failure */
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int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
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/* set sync polarity, only for DM365*/
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void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
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/* set the PG_FRAME_SIZE register, only for DM365 */
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void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
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/* wbl reset for dm644x */
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enum vpss_wbl_sel {
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VPSS_PCR_AEW_WBL_0 = 16,
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VPSS_PCR_AF_WBL_0,
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VPSS_PCR_RSZ4_WBL_0,
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VPSS_PCR_RSZ3_WBL_0,
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VPSS_PCR_RSZ2_WBL_0,
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VPSS_PCR_RSZ1_WBL_0,
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VPSS_PCR_PREV_WBL_0,
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VPSS_PCR_CCDC_WBL_O,
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};
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/* clear wbl overflow flag for DM6446 */
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int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
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/* set sync polarity*/
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void vpss_set_sync_pol(struct vpss_sync_pol sync);
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/* set the PG_FRAME_SIZE register */
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void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size);
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/*
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* vpss_check_and_clear_interrupt - check and clear interrupt
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* @irq - common enumerator for IRQ
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*
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* Following return values used:-
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* 0 - interrupt occurred and cleared
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* 1 - interrupt not occurred
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* 2 - interrupt status not available
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*/
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int vpss_dma_complete_interrupt(void);
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#endif
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