/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Philippe Peurichard <philippe.peurichard@st.com>,
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* Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
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*/
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#ifndef __LINUX_MFD_STPMIC1_H
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#define __LINUX_MFD_STPMIC1_H
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#define TURN_ON_SR 0x1
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#define TURN_OFF_SR 0x2
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#define ICC_LDO_TURN_OFF_SR 0x3
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#define ICC_BUCK_TURN_OFF_SR 0x4
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#define RREQ_STATE_SR 0x5
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#define VERSION_SR 0x6
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#define SWOFF_PWRCTRL_CR 0x10
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#define PADS_PULL_CR 0x11
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#define BUCKS_PD_CR 0x12
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#define LDO14_PD_CR 0x13
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#define LDO56_VREF_PD_CR 0x14
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#define VBUS_DET_VIN_CR 0x15
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#define PKEY_TURNOFF_CR 0x16
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#define BUCKS_MASK_RANK_CR 0x17
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#define BUCKS_MASK_RESET_CR 0x18
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#define LDOS_MASK_RANK_CR 0x19
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#define LDOS_MASK_RESET_CR 0x1A
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#define WCHDG_CR 0x1B
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#define WCHDG_TIMER_CR 0x1C
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#define BUCKS_ICCTO_CR 0x1D
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#define LDOS_ICCTO_CR 0x1E
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#define BUCK1_ACTIVE_CR 0x20
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#define BUCK2_ACTIVE_CR 0x21
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#define BUCK3_ACTIVE_CR 0x22
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#define BUCK4_ACTIVE_CR 0x23
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#define VREF_DDR_ACTIVE_CR 0x24
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#define LDO1_ACTIVE_CR 0x25
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#define LDO2_ACTIVE_CR 0x26
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#define LDO3_ACTIVE_CR 0x27
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#define LDO4_ACTIVE_CR 0x28
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#define LDO5_ACTIVE_CR 0x29
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#define LDO6_ACTIVE_CR 0x2A
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#define BUCK1_STDBY_CR 0x30
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#define BUCK2_STDBY_CR 0x31
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#define BUCK3_STDBY_CR 0x32
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#define BUCK4_STDBY_CR 0x33
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#define VREF_DDR_STDBY_CR 0x34
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#define LDO1_STDBY_CR 0x35
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#define LDO2_STDBY_CR 0x36
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#define LDO3_STDBY_CR 0x37
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#define LDO4_STDBY_CR 0x38
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#define LDO5_STDBY_CR 0x39
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#define LDO6_STDBY_CR 0x3A
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#define BST_SW_CR 0x40
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#define INT_PENDING_R1 0x50
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#define INT_PENDING_R2 0x51
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#define INT_PENDING_R3 0x52
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#define INT_PENDING_R4 0x53
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#define INT_DBG_LATCH_R1 0x60
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#define INT_DBG_LATCH_R2 0x61
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#define INT_DBG_LATCH_R3 0x62
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#define INT_DBG_LATCH_R4 0x63
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#define INT_CLEAR_R1 0x70
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#define INT_CLEAR_R2 0x71
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#define INT_CLEAR_R3 0x72
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#define INT_CLEAR_R4 0x73
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#define INT_MASK_R1 0x80
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#define INT_MASK_R2 0x81
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#define INT_MASK_R3 0x82
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#define INT_MASK_R4 0x83
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#define INT_SET_MASK_R1 0x90
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#define INT_SET_MASK_R2 0x91
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#define INT_SET_MASK_R3 0x92
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#define INT_SET_MASK_R4 0x93
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#define INT_CLEAR_MASK_R1 0xA0
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#define INT_CLEAR_MASK_R2 0xA1
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#define INT_CLEAR_MASK_R3 0xA2
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#define INT_CLEAR_MASK_R4 0xA3
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#define INT_SRC_R1 0xB0
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#define INT_SRC_R2 0xB1
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#define INT_SRC_R3 0xB2
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#define INT_SRC_R4 0xB3
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#define PMIC_MAX_REGISTER_ADDRESS INT_SRC_R4
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#define STPMIC1_PMIC_NUM_IRQ_REGS 4
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#define TURN_OFF_SR_ICC_EVENT 0x08
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#define LDO_VOLTAGE_MASK GENMASK(6, 2)
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#define BUCK_VOLTAGE_MASK GENMASK(7, 2)
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#define LDO_BUCK_VOLTAGE_SHIFT 2
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#define LDO_ENABLE_MASK BIT(0)
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#define BUCK_ENABLE_MASK BIT(0)
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#define BUCK_HPLP_ENABLE_MASK BIT(1)
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#define BUCK_HPLP_SHIFT 1
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#define STDBY_ENABLE_MASK BIT(0)
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#define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)
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#define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)
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#define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)
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#define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)
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#define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)
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#define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)
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#define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)
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#define BUCK1_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK1_PULL_DOWN_MASK BIT(0)
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#define BUCK2_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK2_PULL_DOWN_MASK BIT(2)
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#define BUCK3_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK3_PULL_DOWN_MASK BIT(4)
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#define BUCK4_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK4_PULL_DOWN_MASK BIT(6)
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#define LDO1_PULL_DOWN_REG LDO14_PD_CR
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#define LDO1_PULL_DOWN_MASK BIT(0)
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#define LDO2_PULL_DOWN_REG LDO14_PD_CR
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#define LDO2_PULL_DOWN_MASK BIT(2)
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#define LDO3_PULL_DOWN_REG LDO14_PD_CR
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#define LDO3_PULL_DOWN_MASK BIT(4)
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#define LDO4_PULL_DOWN_REG LDO14_PD_CR
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#define LDO4_PULL_DOWN_MASK BIT(6)
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#define LDO5_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define LDO5_PULL_DOWN_MASK BIT(0)
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#define LDO6_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define LDO6_PULL_DOWN_MASK BIT(2)
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#define VREF_DDR_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define VREF_DDR_PULL_DOWN_MASK BIT(4)
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#define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)
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#define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0)
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#define LDO_BYPASS_MASK BIT(7)
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/* Main PMIC Control Register
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* SWOFF_PWRCTRL_CR
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* Address : 0x10
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*/
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#define ICC_EVENT_ENABLED BIT(4)
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#define PWRCTRL_POLARITY_HIGH BIT(3)
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#define PWRCTRL_PIN_VALID BIT(2)
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#define RESTART_REQUEST_ENABLED BIT(1)
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#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
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/* Main PMIC PADS Control Register
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* PADS_PULL_CR
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* Address : 0x11
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*/
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#define WAKEUP_DETECTOR_DISABLED BIT(4)
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#define PWRCTRL_PD_ACTIVE BIT(3)
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#define PWRCTRL_PU_ACTIVE BIT(2)
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#define WAKEUP_PD_ACTIVE BIT(1)
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#define PONKEY_PU_INACTIVE BIT(0)
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/* Main PMIC VINLOW Control Register
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* VBUS_DET_VIN_CRC DMSC
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* Address : 0x15
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*/
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#define SWIN_DETECTOR_ENABLED BIT(7)
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#define SWOUT_DETECTOR_ENABLED BIT(6)
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#define VINLOW_ENABLED BIT(0)
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#define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
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/* USB Control Register
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* Address : 0x40
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*/
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#define BOOST_OVP_DISABLED BIT(7)
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#define VBUS_OTG_DETECTION_DISABLED BIT(6)
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#define SW_OUT_DISCHARGE BIT(5)
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#define VBUS_OTG_DISCHARGE BIT(4)
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#define OCP_LIMIT_HIGH BIT(3)
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#define SWIN_SWOUT_ENABLED BIT(2)
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#define USBSW_OTG_SWITCH_ENABLED BIT(1)
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#define BOOST_ENABLED BIT(0)
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/* PKEY_TURNOFF_CR
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* Address : 0x16
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*/
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#define PONKEY_PWR_OFF BIT(7)
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#define PONKEY_CC_FLAG_CLEAR BIT(6)
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#define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0)
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#define PONKEY_TURNOFF_MASK GENMASK(7, 0)
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/*
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* struct stpmic1 - stpmic1 master device for sub-drivers
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* @dev: master device of the chip (can be used to access platform data)
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* @irq: main IRQ number
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* @regmap_irq_chip_data: irq chip data
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*/
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struct stpmic1 {
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struct device *dev;
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struct regmap *regmap;
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int irq;
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struct regmap_irq_chip_data *irq_data;
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};
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#endif /* __LINUX_MFD_STPMIC1_H */
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