/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __SOC_ROCKCHIP_PCIE_DMA_TRX_H
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#define __SOC_ROCKCHIP_PCIE_DMA_TRX_H
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#include <linux/debugfs.h>
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#define PCIE_DMA_TABLE_NUM 32
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#define PCIE_DMA_TRX_TYPE_NUM 3
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#define PCIE_DMA_CHN0 0x0
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#define PCIE_DMA_CHN1 0x1
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#define PCIE_DMA_DEFAULT_CHN PCIE_DMA_CHN0
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#define PCIE_DMA_DATA_SND_TABLE_OFFSET 0x0
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#define PCIE_DMA_DATA_RCV_ACK_TABLE_OFFSET 0x8
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#define PCIE_DMA_DATA_FREE_ACK_TABLE_OFFSET 0x10
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#define PCIE_DMA_DATA_READ_REMOTE_TABLE_OFFSET 0x18
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enum dma_dir {
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DMA_FROM_BUS,
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DMA_TO_BUS,
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};
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/**
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* The Channel Control Register for read and write.
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*/
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union chan_ctrl_lo {
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struct {
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u32 cb :1; // 0
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u32 tcb :1; // 1
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u32 llp :1; // 2
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u32 lie :1; // 3
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u32 rie :1; // 4
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u32 cs :2; // 5:6
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u32 rsvd1 :1; // 7
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u32 ccs :1; // 8
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u32 llen :1; // 9
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u32 b_64s :1; // 10
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u32 b_64d :1; // 11
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u32 pf :5; // 12:16
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u32 rsvd2 :7; // 17:23
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u32 sn :1; // 24
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u32 ro :1; // 25
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u32 td :1; // 26
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u32 tc :3; // 27:29
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u32 at :2; // 30:31
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};
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u32 asdword;
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};
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/**
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* The Channel Control Register high part for read and write.
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*/
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union chan_ctrl_hi {
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struct {
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u32 vfenb :1; // 0
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u32 vfunc :8; // 1-8
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u32 rsvd0 :23; // 9-31
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};
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u32 asdword;
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};
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/**
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* The Channel Weight Register.
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*/
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union weight {
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struct {
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u32 weight0 :5; // 0:4
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u32 weight1 :5; // 5:9
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u32 weight2 :5; // 10:14
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u32 weight3 :5; // 15:19
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u32 rsvd :12; // 20:31
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};
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u32 asdword;
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};
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/**
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* The Doorbell Register for read and write.
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*/
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union db {
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struct {
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u32 chnl :3; // 0
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u32 reserved0 :28; // 3:30
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u32 stop :1; // 31
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};
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u32 asdword;
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};
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/**
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* The Context Registers for read and write.
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*/
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struct ctx_regs {
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union chan_ctrl_lo ctrllo;
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union chan_ctrl_hi ctrlhi;
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u32 xfersize;
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u32 sarptrlo;
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u32 sarptrhi;
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u32 darptrlo;
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u32 darptrhi;
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};
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/**
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* The Enable Register for read and write.
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*/
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union enb {
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struct {
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u32 enb :1; // 0
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u32 reserved0 :31; // 1:31
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};
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u32 asdword;
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};
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/**
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* The Interrupt Status Register for read and write.
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*/
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union int_status {
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struct {
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u32 donesta :8;
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u32 rsvd0 :8;
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u32 abortsta :8;
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u32 rsvd1 :8;
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};
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u32 asdword;
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};
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/**
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* The Interrupt Clear Register for read and write.
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*/
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union int_clear {
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struct {
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u32 doneclr :8;
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u32 rsvd0 :8;
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u32 abortclr :8;
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u32 rsvd1 :8;
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};
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u32 asdword;
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};
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struct dma_table {
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u32 *descs;
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int chn;
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phys_addr_t phys_descs;
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u32 dir;
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u32 type;
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struct list_head tbl_node;
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union enb enb;
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struct ctx_regs ctx_reg;
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union weight weilo;
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union weight weihi;
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union db start;
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phys_addr_t local;
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phys_addr_t bus;
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size_t buf_size;
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};
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struct dma_trx_obj {
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struct device *dev;
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int loop_count;
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int loop_count_threshold;
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void *local_mem_base;
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phys_addr_t local_mem_start;
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size_t local_mem_size;
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phys_addr_t remote_mem_start;
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void *region_base;
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phys_addr_t region_start;
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size_t region_size;
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int dma_free;
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unsigned long local_write_available;
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unsigned long local_read_available;
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unsigned long remote_write_available;
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spinlock_t tbl_list_lock; /* lock dma table */
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struct list_head tbl_list;
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struct work_struct dma_trx_work;
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wait_queue_head_t event_queue;
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struct workqueue_struct *dma_trx_wq;
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struct dma_table *table[PCIE_DMA_TABLE_NUM];
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struct dma_table *cur;
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struct hrtimer scan_timer;
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int busno;
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void *priv;
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struct completion done;
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int ref_count;
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struct mutex count_mutex;
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unsigned long irq_num;
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struct dentry *pcie_root;
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struct pcie_misc_dev *pcie_dev;
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void (*start_dma_func)(struct dma_trx_obj *obj, struct dma_table *table);
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void (*config_dma_func)(struct dma_table *table);
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int (*get_dma_status)(struct dma_trx_obj *obj, u8 chn, enum dma_dir dir);
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int (*cb)(struct dma_trx_obj *obj, u32 chn, enum dma_dir dir);
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ktime_t begin;
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ktime_t end;
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u64 cache_time_total;
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u64 cache_time_avarage;
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u32 buffer_size;
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u32 rd_buf_size;
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u32 wr_buf_size;
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u32 ack_base;
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u32 set_data_check_pos;
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u32 set_local_idx_pos;
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u32 set_buf_size_pos;
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u32 set_chk_sum_pos;
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u32 version;
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int addr_reverse;
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};
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#if IS_ENABLED(CONFIG_ROCKCHIP_PCIE_DMA_OBJ)
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struct dma_trx_obj *rk_pcie_dma_obj_probe(struct device *dev);
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void rk_pcie_dma_obj_remove(struct dma_trx_obj *obj);
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#else
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static inline struct dma_trx_obj *rk_pcie_dma_obj_probe(struct device *dev)
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{
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return NULL;
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}
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static inline void rk_pcie_dma_obj_remove(struct dma_trx_obj *obj)
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{
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}
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#endif
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#endif
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