/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PCIe driver for Renesas R-Car SoCs
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* Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
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*
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* Author: Phil Edworthy <phil.edworthy@renesas.com>
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*/
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#ifndef _PCIE_RCAR_H
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#define _PCIE_RCAR_H
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#define PCIECAR 0x000010
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#define PCIECCTLR 0x000018
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#define CONFIG_SEND_ENABLE BIT(31)
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#define TYPE0 (0 << 8)
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#define TYPE1 BIT(8)
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#define PCIECDR 0x000020
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#define PCIEMSR 0x000028
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#define PCIEINTXR 0x000400
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#define ASTINTX BIT(16)
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#define PCIEPHYSR 0x0007f0
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#define PHYRDY BIT(0)
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#define PCIEMSITXR 0x000840
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/* Transfer control */
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#define PCIETCTLR 0x02000
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#define DL_DOWN BIT(3)
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#define CFINIT BIT(0)
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#define PCIETSTR 0x02004
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#define DATA_LINK_ACTIVE BIT(0)
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#define PCIEERRFR 0x02020
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#define UNSUPPORTED_REQUEST BIT(4)
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#define PCIEMSIFR 0x02044
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#define PCIEMSIALR 0x02048
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#define MSIFE BIT(0)
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#define PCIEMSIAUR 0x0204c
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#define PCIEMSIIER 0x02050
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/* root port address */
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#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
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/* local address reg & mask */
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#define PCIELAR(x) (0x02200 + ((x) * 0x20))
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#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
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#define LAM_PREFETCH BIT(3)
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#define LAM_64BIT BIT(2)
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#define LAR_ENABLE BIT(1)
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/* PCIe address reg & mask */
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#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
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#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
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#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
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#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
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#define PAR_ENABLE BIT(31)
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#define IO_SPACE BIT(8)
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/* Configuration */
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#define PCICONF(x) (0x010000 + ((x) * 0x4))
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#define INTDIS BIT(10)
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#define PMCAP(x) (0x010040 + ((x) * 0x4))
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#define MSICAP(x) (0x010050 + ((x) * 0x4))
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#define MSICAP0_MSIE BIT(16)
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#define MSICAP0_MMESCAP_OFFSET 17
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#define MSICAP0_MMESE_OFFSET 20
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#define MSICAP0_MMESE_MASK GENMASK(22, 20)
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#define EXPCAP(x) (0x010070 + ((x) * 0x4))
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#define VCCAP(x) (0x010100 + ((x) * 0x4))
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/* link layer */
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#define IDSETR0 0x011000
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#define IDSETR1 0x011004
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#define SUBIDSETR 0x011024
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#define TLCTLR 0x011048
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#define MACSR 0x011054
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#define SPCHGFIN BIT(4)
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#define SPCHGFAIL BIT(6)
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#define SPCHGSUC BIT(7)
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#define LINK_SPEED (0xf << 16)
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#define LINK_SPEED_2_5GTS (1 << 16)
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#define LINK_SPEED_5_0GTS (2 << 16)
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#define MACCTLR 0x011058
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#define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
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#define SPEED_CHANGE BIT(24)
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#define SCRAMBLE_DISABLE BIT(27)
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#define LTSMDIS BIT(31)
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#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
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#define PMSR 0x01105c
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#define MACS2R 0x011078
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#define MACCGSPSETR 0x011084
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#define SPCNGRSN BIT(31)
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/* R-Car H1 PHY */
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#define H1_PCIEPHYADRR 0x04000c
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#define WRITE_CMD BIT(16)
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#define PHY_ACK BIT(24)
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#define RATE_POS 12
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#define LANE_POS 8
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#define ADR_POS 0
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#define H1_PCIEPHYDOUTR 0x040014
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/* R-Car Gen2 PHY */
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#define GEN2_PCIEPHYADDR 0x780
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#define GEN2_PCIEPHYDATA 0x784
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#define GEN2_PCIEPHYCTRL 0x78c
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#define INT_PCI_MSI_NR 32
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#define RCONF(x) (PCICONF(0) + (x))
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#define RPMCAP(x) (PMCAP(0) + (x))
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#define REXPCAP(x) (EXPCAP(0) + (x))
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#define RVCCAP(x) (VCCAP(0) + (x))
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#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
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#define RCAR_PCI_MAX_RESOURCES 4
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#define MAX_NR_INBOUND_MAPS 6
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struct rcar_pcie {
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struct device *dev;
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void __iomem *base;
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};
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enum {
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RCAR_PCI_ACCESS_READ,
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RCAR_PCI_ACCESS_WRITE,
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};
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void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
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u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
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void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
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int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
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int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
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void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
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struct resource_entry *window);
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void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
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u64 pci_addr, u64 flags, int idx, bool host);
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#endif
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