/*
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* arch/arm/mach-ks8695/include/mach/regs-mem.h
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*
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* Copyright (C) 2006 Andrew Victor
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*
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* KS8695 - Memory Controller registers and bit definitions
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_MEM_H
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#define KS8695_MEM_H
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#define KS8695_MEM_OFFSET (0xF0000 + 0x4000)
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#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET)
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#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET)
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/*
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* Memory Controller Registers
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*/
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#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */
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#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */
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#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */
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#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */
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#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */
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#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */
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#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */
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#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */
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#define KS8695_SDGCON (0x38) /* SDRAM General Control */
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#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */
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#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */
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/* External I/O Access Control Registers */
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#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */
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#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */
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#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */
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#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */
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#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */
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#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */
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/* ROM/SRAM/Flash Control Register */
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#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */
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#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */
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#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */
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#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */
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#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */
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#define PMC_NORMAL (0 << 0)
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#define PMC_4WORD (1 << 0)
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#define PMC_8WORD (2 << 0)
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#define PMC_16WORD (3 << 0)
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/* External I/O and ROM/SRAM/Flash General Register */
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#define ERGCON_TMULT (3 << 28) /* Time Multiplier */
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#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */
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#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */
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#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */
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#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */
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#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */
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/* SDRAM Control Register */
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#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */
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#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */
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#define SDCON_DBCAB (3 << 8) /* Column Address Bits */
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#define SDCON_DBBNUM (1 << 3) /* Number of Banks */
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#define SDCON_DBDBW (3 << 1) /* Data Bus Width */
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/* SDRAM General Control Register */
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#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */
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#define SDGCON_SDCAS (3 << 0) /* CAS latency */
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/* SDRAM Buffer Control Register */
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#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */
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#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */
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#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */
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#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */
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#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */
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#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */
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#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */
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#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */
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/* SDRAM Refresh Timer Register */
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#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */
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#endif
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