/*
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* Realtek RTD1293/RTD1295/RTD1296 SoC
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*
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* Copyright (c) 2016-2017 Andreas Färber
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/memreserve/ 0x0000000000000000 0x0000000000030000;
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/memreserve/ 0x000000000001f000 0x0000000000001000;
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/memreserve/ 0x0000000000030000 0x00000000000d0000;
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/memreserve/ 0x0000000001b00000 0x00000000004be000;
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/memreserve/ 0x0000000001ffe000 0x0000000000004000;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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arm_pmu: arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Exclude up to 2 GiB of RAM */
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ranges = <0x80000000 0x80000000 0x80000000>;
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uart0: serial@98007800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x98007800 0x400>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <27000000>;
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status = "disabled";
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};
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uart1: serial@9801b200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9801b200 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <432000000>;
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status = "disabled";
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};
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uart2: serial@9801b400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9801b400 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <432000000>;
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status = "disabled";
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};
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gic: interrupt-controller@ff011000 {
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compatible = "arm,gic-400";
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reg = <0xff011000 0x1000>,
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<0xff012000 0x2000>,
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<0xff014000 0x2000>,
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<0xff016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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