/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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//============================================================
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// include files
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//============================================================
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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VOID
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odm_DynamicTxPowerInit(
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IN PVOID pDM_VOID
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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PADAPTER Adapter = pDM_Odm->Adapter;
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PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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/*if (!IS_HARDWARE_TYPE_8814A(Adapter)) {*/
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/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */
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/* ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));*/
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/* return;*/
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/*} else*/
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{
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pMgntInfo->bDynamicTxPowerEnable = TRUE;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
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("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));
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}
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#if DEV_BUS_TYPE==RT_USB_INTERFACE
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if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
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{
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odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
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pMgntInfo->bDynamicTxPowerEnable = TRUE;
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}
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else
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#else
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//so 92c pci do not need dynamic tx power? vivi check it later
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pMgntInfo->bDynamicTxPowerEnable = FALSE;
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#endif
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pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
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pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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pDM_Odm->LastDTPLvl = TxHighPwrLevel_Normal;
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pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
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pDM_Odm->tx_agc_ofdm_18_6 = ODM_GetBBReg(pDM_Odm, 0xC24, bMaskDWord); /*TXAGC {18M 12M 9M 6M}*/
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#endif
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}
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VOID
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odm_DynamicTxPowerSavePowerIndex(
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IN PVOID pDM_VOID
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
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u1Byte index;
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u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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PADAPTER Adapter = pDM_Odm->Adapter;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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for(index = 0; index< 6; index++)
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pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
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#endif
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#endif
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}
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VOID
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odm_DynamicTxPowerRestorePowerIndex(
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IN PVOID pDM_VOID
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
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u1Byte index;
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PADAPTER Adapter = pDM_Odm->Adapter;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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for(index = 0; index< 6; index++)
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PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
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#endif
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#endif
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}
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VOID
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odm_DynamicTxPowerWritePowerIndex(
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IN PVOID pDM_VOID,
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IN u1Byte Value)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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u1Byte index;
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u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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for(index = 0; index< 6; index++)
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//PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
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ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
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}
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VOID
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odm_DynamicTxPowerNIC_CE(
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IN PVOID pDM_VOID
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
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#if (RTL8821A_SUPPORT == 1)
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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u1Byte val;
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u1Byte rssi_tmp = pDM_Odm->RSSI_Min;
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if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
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return;
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if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
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pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
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/**/
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} else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
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pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
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/**/
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} else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) {
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pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
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/**/
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}
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if (pDM_Odm->LastDTPLvl != pDM_Odm->DynamicTxHighPowerLvl) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", pDM_Odm->LastDTPLvl, pDM_Odm->DynamicTxHighPowerLvl));
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pDM_Odm->LastDTPLvl = pDM_Odm->DynamicTxHighPowerLvl;
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if (pDM_Odm->SupportICType & (ODM_RTL8821)) {
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if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
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ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/
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val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff;
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if (val >= 0x20)
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val -= 0x16;
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ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n"));
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} else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
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ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/
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val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff;
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if (val >= 0x20)
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val -= 0x10;
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ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n"));
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} else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) {
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ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 0); /* Resp TXAGC offset = 0dB*/
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ODM_SetBBReg(pDM_Odm, 0xC24, bMaskDWord, pDM_Odm->tx_agc_ofdm_18_6);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n"));
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}
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}
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}
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#endif
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#endif
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}
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VOID
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odm_DynamicTxPower(
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IN PVOID pDM_VOID
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)
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{
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//
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// For AP/ADSL use prtl8192cd_priv
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// For CE/NIC use PADAPTER
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//
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//PADAPTER pAdapter = pDM_Odm->Adapter;
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// prtl8192cd_priv priv = pDM_Odm->priv;
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
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return;
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//
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// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
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// at the same time. In the stage2/3, we need to prive universal interface and merge all
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// HW dynamic mechanism.
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//
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switch (pDM_Odm->SupportPlatform)
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{
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case ODM_WIN:
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odm_DynamicTxPowerNIC(pDM_Odm);
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break;
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case ODM_CE:
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odm_DynamicTxPowerNIC_CE(pDM_Odm);
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break;
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case ODM_AP:
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odm_DynamicTxPowerAP(pDM_Odm);
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break;
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default:
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break;
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}
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}
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VOID
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odm_DynamicTxPowerNIC(
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IN PVOID pDM_VOID
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
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return;
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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if (pDM_Odm->SupportICType == ODM_RTL8814A) {
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odm_DynamicTxPower_8814A(pDM_Odm);
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} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
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PADAPTER Adapter = pDM_Odm->Adapter;
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PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter);
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if (pMgntInfo->RegRspPwr == 1) {
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if (pDM_Odm->RSSI_Min > 60)
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ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); /*Resp TXAGC offset = -3dB*/
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else if (pDM_Odm->RSSI_Min < 55)
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ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); /*Resp TXAGC offset = 0dB*/
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}
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}
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#endif
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}
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VOID
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odm_DynamicTxPowerAP(
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IN PVOID pDM_VOID
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1))
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prtl8192cd_priv priv = pDM_Odm->priv;
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s4Byte i;
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s2Byte pwr_thd = 63;
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if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
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return;
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#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1))
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if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A))
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pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1;
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#endif
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/*
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* Check if station is near by to use lower tx power
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*/
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if ((priv->up_time % 3) == 0 ) {
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int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
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for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
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PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
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if(IS_STA_VALID(pstat) ) {
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if(disable_pwr_ctrl)
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pstat->hp_level = 0;
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else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
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pstat->hp_level = 1;
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else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8)))
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pstat->hp_level = 0;
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}
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}
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#if defined(CONFIG_WLAN_HAL_8192EE)
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if (GET_CHIP_VER(priv) == VERSION_8192E) {
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if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) {
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if(pDM_Odm->RSSI_Min > pwr_thd)
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RRSR_power_control_11n(priv, 1 );
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else if(pDM_Odm->RSSI_Min < (pwr_thd-8))
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RRSR_power_control_11n(priv, 0 );
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} else {
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RRSR_power_control_11n(priv, 0 );
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}
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}
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#endif
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#ifdef CONFIG_WLAN_HAL_8814AE
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if (GET_CHIP_VER(priv) == VERSION_8814A) {
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if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) {
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if (pDM_Odm->RSSI_Min > pwr_thd)
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RRSR_power_control_14(priv, 1);
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else if (pDM_Odm->RSSI_Min < (pwr_thd-8))
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RRSR_power_control_14(priv, 0);
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} else {
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RRSR_power_control_14(priv, 0);
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}
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}
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#endif
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}
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//#endif
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#endif
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}
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VOID
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odm_DynamicTxPower_8821(
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IN PVOID pDM_VOID,
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IN pu1Byte pDesc,
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IN u1Byte macId
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)
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{
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#if (RTL8821A_SUPPORT == 1)
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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PSTA_INFO_T pEntry;
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u1Byte reg0xc56_byte;
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u1Byte txpwr_offset = 0;
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pEntry = pDM_Odm->pODM_StaInfo[macId];
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reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte));
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if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) {
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/* Avoid TXAGC error after TX power offset is applied.
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For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
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Total power = 6-11= -5( overflow!! ), PA may be burned !
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so txpwr_offset should be adjusted by Reg0xc56*/
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if (reg0xc56_byte < 7)
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txpwr_offset = 1;
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else if (reg0xc56_byte < 11)
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txpwr_offset = 2;
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else
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txpwr_offset = 3;
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SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset));
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} else{
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SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset));
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}
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#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
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#endif /*#if (RTL8821A_SUPPORT==1)*/
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}
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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VOID
|
odm_DynamicTxPower_8814A(
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IN PVOID pDM_VOID
|
)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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PADAPTER Adapter = pDM_Odm->Adapter;
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PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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s4Byte UndecoratedSmoothedPWDB;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
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("TxLevel=%d pMgntInfo->IOTAction=%x pMgntInfo->bDynamicTxPowerEnable=%d\n",
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pHalData->DynamicTxHighPowerLvl, pMgntInfo->IOTAction, pMgntInfo->bDynamicTxPowerEnable));
|
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/*STA not connected and AP not connected*/
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if ((!pMgntInfo->bMediaConnect) && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n"));
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pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
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return;
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}
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|
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if ((pMgntInfo->bDynamicTxPowerEnable != TRUE) || pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) {
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pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
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} else {
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if (pMgntInfo->bMediaConnect) { /*Default port*/
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if (ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) {
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UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
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} else {
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UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
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}
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} else {/*associated entry pwdb*/
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UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
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}
|
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/*Should we separate as 2.4G/5G band?*/
|
|
if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
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pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
|
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
|
} else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
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(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
|
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
|
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
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} else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) {
|
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
|
}
|
}
|
|
|
if (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) {
|
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8814A() Channel = %d\n" , pHalData->CurrentChannel));
|
odm_SetTxPowerLevel8814(Adapter, pHalData->CurrentChannel, pHalData->DynamicTxHighPowerLvl);
|
}
|
|
|
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
("odm_DynamicTxPower_8814A() Channel = %d TXpower lvl=%d/%d\n" ,
|
pHalData->CurrentChannel, pHalData->LastDTPLvl, pHalData->DynamicTxHighPowerLvl));
|
|
pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
|
|
}
|
|
|
|
/**/
|
/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
|
/**/
|
/**/
|
VOID
|
odm_SetTxPowerLevel8814(
|
IN PADAPTER Adapter,
|
IN u1Byte Channel,
|
IN u1Byte PwrLvl
|
)
|
{
|
#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
|
u4Byte i, j, k = 0;
|
u4Byte value[264] = {0};
|
u4Byte path = 0, PowerIndex, txagc_table_wd = 0x00801000;
|
|
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
|
u1Byte jaguar2Rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
|
{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
|
{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
|
{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
|
{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
|
{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
|
{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
|
{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
|
{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
|
{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
|
{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
|
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
|
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
|
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
|
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
|
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
|
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} };
|
|
for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) {
|
|
u1Byte usb_host = UsbModeQueryHubUsbType(Adapter);
|
u1Byte usb_rfset = UsbModeQueryRfSet(Adapter);
|
u1Byte usb_rf_type = RT_GetRFType(Adapter);
|
|
for (i = 0; i <= 16; i++) {
|
for (j = 0; j <= 3; j++) {
|
if (jaguar2Rates[i][j] == 0)
|
continue;
|
|
txagc_table_wd = 0x00801000;
|
PowerIndex = (u4Byte) PHY_GetTxPowerIndex(Adapter, (u1Byte)path, jaguar2Rates[i][j], pHalData->CurrentChannelBW, Channel);
|
|
/*for Query bus type to recude tx power.*/
|
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(Adapter) && usb_rf_type == RF_3T3R) {
|
if (Channel <= 14) {
|
if (PowerIndex >= 16)
|
PowerIndex -= 16;
|
else
|
PowerIndex = 0;
|
} else
|
PowerIndex = 0;
|
}
|
|
if (PwrLvl == TxHighPwrLevel_Level1) {
|
if (PowerIndex >= 0x10)
|
PowerIndex -= 0x10;
|
else
|
PowerIndex = 0;
|
} else if (PwrLvl == TxHighPwrLevel_Level2) {
|
PowerIndex = 0;
|
}
|
|
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2Rates[i][j]) | (PowerIndex << 24);
|
|
PHY_SetTxPowerIndexShadow(Adapter, (u1Byte)PowerIndex, (u1Byte)path, jaguar2Rates[i][j]);
|
|
value[k++] = txagc_table_wd;
|
}
|
}
|
}
|
|
if (Adapter->MgntInfo.bScanInProgress == FALSE && Adapter->MgntInfo.RegFWOffload == 2)
|
HalDownloadTxPowerLevel8814(Adapter, value);
|
#endif
|
}
|
#endif
|
|
|
