/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <nvif/class.h>
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static void
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gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80)));
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u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80)));
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const struct nvkm_enum *warp;
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char glob[128];
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nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
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warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
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nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: "
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"global %08x [%s] warp %04x [%s]\n",
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gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : "");
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr);
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}
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static void
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gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
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{
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gv100_gr_trap_sm(gr, gpc, tpc, 0);
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gv100_gr_trap_sm(gr, gpc, tpc, 1);
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}
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static void
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gv100_gr_init_4188a4(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000);
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}
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static void
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gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int sm;
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for (sm = 0; sm < 0x100; sm += 0x80) {
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004);
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}
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}
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static void
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gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000);
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}
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static void
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gv100_gr_init_419bd8(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000);
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}
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static const struct gf100_gr_func
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gv100_gr = {
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gm200_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_419bd8 = gv100_gr_init_419bd8,
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.init_gpc_mmu = gm200_gr_init_gpc_mmu,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = gf117_gr_init_zcull,
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.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
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.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
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.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
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.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_504430 = gv100_gr_init_504430,
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.init_shader_exceptions = gv100_gr_init_shader_exceptions,
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.init_4188a4 = gv100_gr_init_4188a4,
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.trap_mp = gv100_gr_trap_mp,
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.rops = gm200_gr_rops,
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.gpc_nr = 6,
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.tpc_nr = 5,
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.ppc_nr = 3,
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.grctx = &gv100_grctx,
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.zbc = &gp102_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, VOLTA_A, &gf100_fermi },
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{ -1, -1, VOLTA_COMPUTE_A },
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{}
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}
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};
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int
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gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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{
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return gm200_gr_new_(&gv100_gr, device, index, pgr);
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}
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