/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_HW_SHARED_H__
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#define __DAL_HW_SHARED_H__
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#include "os_types.h"
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#include "fixed31_32.h"
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#include "dc_hw_types.h"
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/******************************************************************************
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* Data types shared between different Virtual HW blocks
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******************************************************************************/
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#define MAX_AUDIOS 7
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#define MAX_PIPES 6
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struct gamma_curve {
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uint32_t offset;
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uint32_t segments_num;
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};
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struct curve_points {
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struct fixed31_32 x;
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struct fixed31_32 y;
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struct fixed31_32 offset;
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struct fixed31_32 slope;
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uint32_t custom_float_x;
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uint32_t custom_float_y;
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uint32_t custom_float_offset;
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uint32_t custom_float_slope;
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};
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struct pwl_result_data {
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struct fixed31_32 red;
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struct fixed31_32 green;
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struct fixed31_32 blue;
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struct fixed31_32 delta_red;
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struct fixed31_32 delta_green;
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struct fixed31_32 delta_blue;
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uint32_t red_reg;
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uint32_t green_reg;
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uint32_t blue_reg;
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uint32_t delta_red_reg;
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uint32_t delta_green_reg;
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uint32_t delta_blue_reg;
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};
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struct pwl_params {
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struct gamma_curve arr_curve_points[34];
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struct curve_points arr_points[2];
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struct pwl_result_data rgb_resulted[256 + 3];
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uint32_t hw_points_num;
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};
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/* move to dpp
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* while we are moving functionality out of opp to dpp to align
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* HW programming to HW IP, we define these struct in hw_shared
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* so we can still compile while refactoring
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*/
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enum lb_pixel_depth {
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/* do not change the values because it is used as bit vector */
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LB_PIXEL_DEPTH_18BPP = 1,
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LB_PIXEL_DEPTH_24BPP = 2,
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LB_PIXEL_DEPTH_30BPP = 4,
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LB_PIXEL_DEPTH_36BPP = 8
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};
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enum graphics_csc_adjust_type {
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GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
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GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
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GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
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};
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enum ipp_degamma_mode {
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IPP_DEGAMMA_MODE_BYPASS,
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IPP_DEGAMMA_MODE_HW_sRGB,
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IPP_DEGAMMA_MODE_HW_xvYCC,
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IPP_DEGAMMA_MODE_USER_PWL
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};
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enum ipp_output_format {
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IPP_OUTPUT_FORMAT_12_BIT_FIX,
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IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
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IPP_OUTPUT_FORMAT_FLOAT
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};
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enum expansion_mode {
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EXPANSION_MODE_DYNAMIC,
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EXPANSION_MODE_ZERO
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};
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struct default_adjustment {
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enum lb_pixel_depth lb_color_depth;
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enum dc_color_space out_color_space;
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enum dc_color_space in_color_space;
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enum dc_color_depth color_depth;
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enum pixel_format surface_pixel_format;
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enum graphics_csc_adjust_type csc_adjust_type;
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bool force_hw_default;
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};
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struct out_csc_color_matrix {
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enum dc_color_space color_space;
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uint16_t regval[12];
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};
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enum opp_regamma {
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OPP_REGAMMA_BYPASS = 0,
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OPP_REGAMMA_SRGB,
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OPP_REGAMMA_XVYCC,
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OPP_REGAMMA_USER
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};
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struct dc_bias_and_scale {
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uint16_t scale_red;
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uint16_t bias_red;
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uint16_t scale_green;
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uint16_t bias_green;
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uint16_t scale_blue;
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uint16_t bias_blue;
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};
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enum test_pattern_dyn_range {
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TEST_PATTERN_DYN_RANGE_VESA = 0,
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TEST_PATTERN_DYN_RANGE_CEA
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};
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enum test_pattern_mode {
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TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
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TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
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TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
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TEST_PATTERN_MODE_VERTICALBARS,
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TEST_PATTERN_MODE_HORIZONTALBARS,
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TEST_PATTERN_MODE_SINGLERAMP_RGB,
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TEST_PATTERN_MODE_DUALRAMP_RGB
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};
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enum test_pattern_color_format {
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TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
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TEST_PATTERN_COLOR_FORMAT_BPC_8,
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TEST_PATTERN_COLOR_FORMAT_BPC_10,
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TEST_PATTERN_COLOR_FORMAT_BPC_12
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};
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enum controller_dp_test_pattern {
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CONTROLLER_DP_TEST_PATTERN_D102 = 0,
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CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
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CONTROLLER_DP_TEST_PATTERN_PRBS7,
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CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
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CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
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CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
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CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
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CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
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CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
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CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
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};
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enum dc_lut_mode {
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LUT_BYPASS,
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LUT_RAM_A,
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LUT_RAM_B
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};
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#endif /* __DAL_HW_SHARED_H__ */
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