/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_I2C_HW_ENGINE_DCE110_H__
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#define __DAL_I2C_HW_ENGINE_DCE110_H__
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#define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
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SRI(SETUP, DC_I2C_DDC, id),\
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SRI(SPEED, DC_I2C_DDC, id),\
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SR(DC_I2C_ARBITRATION),\
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SR(DC_I2C_CONTROL),\
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SR(DC_I2C_SW_STATUS),\
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SR(DC_I2C_TRANSACTION0),\
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SR(DC_I2C_TRANSACTION1),\
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SR(DC_I2C_TRANSACTION2),\
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SR(DC_I2C_TRANSACTION3),\
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SR(DC_I2C_DATA),\
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SR(MICROSECOND_TIME_BASE_DIV)
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#define I2C_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
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I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
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I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
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I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
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I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
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I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
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I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
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I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
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I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
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I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
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I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
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I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
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I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
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I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
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I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
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I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
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I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
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I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
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I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
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I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
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I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
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I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
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I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
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I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
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I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
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I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh)
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#define I2C_COMMON_MASK_SH_LIST_DCE100(mask_sh)\
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I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
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#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
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I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
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I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
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struct dce110_i2c_hw_engine_shift {
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uint8_t DC_I2C_DDC1_ENABLE;
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uint8_t DC_I2C_DDC1_TIME_LIMIT;
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uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
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uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
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uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
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uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
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uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
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uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
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uint8_t DC_I2C_NO_QUEUED_SW_GO;
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uint8_t DC_I2C_SW_PRIORITY;
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uint8_t DC_I2C_SOFT_RESET;
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uint8_t DC_I2C_SW_STATUS_RESET;
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uint8_t DC_I2C_GO;
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uint8_t DC_I2C_SEND_RESET;
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uint8_t DC_I2C_TRANSACTION_COUNT;
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uint8_t DC_I2C_DDC_SELECT;
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uint8_t DC_I2C_DDC1_PRESCALE;
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uint8_t DC_I2C_DDC1_THRESHOLD;
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uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
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uint8_t DC_I2C_SW_STOPPED_ON_NACK;
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uint8_t DC_I2C_SW_TIMEOUT;
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uint8_t DC_I2C_SW_ABORTED;
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uint8_t DC_I2C_SW_DONE;
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uint8_t DC_I2C_SW_STATUS;
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uint8_t DC_I2C_STOP_ON_NACK0;
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uint8_t DC_I2C_START0;
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uint8_t DC_I2C_RW0;
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uint8_t DC_I2C_STOP0;
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uint8_t DC_I2C_COUNT0;
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uint8_t DC_I2C_DATA_RW;
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uint8_t DC_I2C_DATA;
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uint8_t DC_I2C_INDEX;
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uint8_t DC_I2C_INDEX_WRITE;
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uint8_t XTAL_REF_DIV;
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};
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struct dce110_i2c_hw_engine_mask {
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uint32_t DC_I2C_DDC1_ENABLE;
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uint32_t DC_I2C_DDC1_TIME_LIMIT;
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uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
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uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
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uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
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uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
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uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
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uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
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uint32_t DC_I2C_NO_QUEUED_SW_GO;
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uint32_t DC_I2C_SW_PRIORITY;
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uint32_t DC_I2C_SOFT_RESET;
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uint32_t DC_I2C_SW_STATUS_RESET;
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uint32_t DC_I2C_GO;
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uint32_t DC_I2C_SEND_RESET;
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uint32_t DC_I2C_TRANSACTION_COUNT;
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uint32_t DC_I2C_DDC_SELECT;
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uint32_t DC_I2C_DDC1_PRESCALE;
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uint32_t DC_I2C_DDC1_THRESHOLD;
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uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
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uint32_t DC_I2C_SW_STOPPED_ON_NACK;
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uint32_t DC_I2C_SW_TIMEOUT;
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uint32_t DC_I2C_SW_ABORTED;
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uint32_t DC_I2C_SW_DONE;
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uint32_t DC_I2C_SW_STATUS;
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uint32_t DC_I2C_STOP_ON_NACK0;
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uint32_t DC_I2C_START0;
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uint32_t DC_I2C_RW0;
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uint32_t DC_I2C_STOP0;
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uint32_t DC_I2C_COUNT0;
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uint32_t DC_I2C_DATA_RW;
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uint32_t DC_I2C_DATA;
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uint32_t DC_I2C_INDEX;
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uint32_t DC_I2C_INDEX_WRITE;
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uint32_t XTAL_REF_DIV;
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};
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struct dce110_i2c_hw_engine_registers {
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uint32_t SETUP;
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uint32_t SPEED;
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uint32_t DC_I2C_ARBITRATION;
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uint32_t DC_I2C_CONTROL;
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uint32_t DC_I2C_SW_STATUS;
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uint32_t DC_I2C_TRANSACTION0;
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uint32_t DC_I2C_TRANSACTION1;
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uint32_t DC_I2C_TRANSACTION2;
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uint32_t DC_I2C_TRANSACTION3;
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uint32_t DC_I2C_DATA;
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uint32_t MICROSECOND_TIME_BASE_DIV;
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};
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struct i2c_hw_engine_dce110 {
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struct i2c_hw_engine base;
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const struct dce110_i2c_hw_engine_registers *regs;
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const struct dce110_i2c_hw_engine_shift *i2c_shift;
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const struct dce110_i2c_hw_engine_mask *i2c_mask;
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struct {
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uint32_t DC_I2C_DDCX_SETUP;
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uint32_t DC_I2C_DDCX_SPEED;
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} addr;
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uint32_t engine_id;
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/* expressed in kilohertz */
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uint32_t reference_frequency;
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/* number of bytes currently used in HW buffer */
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uint32_t buffer_used_bytes;
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/* number of bytes used for write transaction in HW buffer
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* - this will be used as the index to read from*/
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uint32_t buffer_used_write;
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/* number of pending transactions (before GO) */
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uint32_t transaction_count;
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uint32_t engine_keep_power_up_count;
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uint32_t i2_setup_time_limit;
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};
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struct i2c_hw_engine_dce110_create_arg {
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uint32_t engine_id;
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uint32_t reference_frequency;
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uint32_t default_speed;
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struct dc_context *ctx;
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const struct dce110_i2c_hw_engine_registers *regs;
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const struct dce110_i2c_hw_engine_shift *i2c_shift;
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const struct dce110_i2c_hw_engine_mask *i2c_mask;
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};
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struct i2c_engine *dal_i2c_hw_engine_dce110_create(
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const struct i2c_hw_engine_dce110_create_arg *arg);
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enum {
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I2C_SETUP_TIME_LIMIT_DCE = 255,
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I2C_SETUP_TIME_LIMIT_DCN = 3,
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I2C_HW_BUFFER_SIZE = 538,
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I2C_SEND_RESET_LENGTH_9 = 9,
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I2C_SEND_RESET_LENGTH_10 = 10,
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};
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#endif
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