/*
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* topic.h 1.8 1999/08/28 04:01:47
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*
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* The contents of this file are subject to the Mozilla Public License
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* Version 1.1 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License
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* at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and
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* limitations under the License.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* Alternatively, the contents of this file may be used under the
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* terms of the GNU General Public License version 2 (the "GPL"), in which
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* case the provisions of the GPL are applicable instead of the
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* above. If you wish to allow the use of your version of this file
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* only under the terms of the GPL and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the GPL. If you do not delete the
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* provisions above, a recipient may use your version of this file
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* under either the MPL or the GPL.
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* topic.h $Release$ 1999/08/28 04:01:47
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*/
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#ifndef _LINUX_TOPIC_H
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#define _LINUX_TOPIC_H
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/* Register definitions for Toshiba ToPIC95/97/100 controllers */
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#define TOPIC_SOCKET_CONTROL 0x0090 /* 32 bit */
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#define TOPIC_SCR_IRQSEL 0x00000001
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#define TOPIC_SLOT_CONTROL 0x00a0 /* 8 bit */
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#define TOPIC_SLOT_SLOTON 0x80
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#define TOPIC_SLOT_SLOTEN 0x40
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#define TOPIC_SLOT_ID_LOCK 0x20
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#define TOPIC_SLOT_ID_WP 0x10
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#define TOPIC_SLOT_PORT_MASK 0x0c
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#define TOPIC_SLOT_PORT_SHIFT 2
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#define TOPIC_SLOT_OFS_MASK 0x03
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#define TOPIC_CARD_CONTROL 0x00a1 /* 8 bit */
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#define TOPIC_CCR_INTB 0x20
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#define TOPIC_CCR_INTA 0x10
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#define TOPIC_CCR_CLOCK 0x0c
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#define TOPIC_CCR_PCICLK 0x0c
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#define TOPIC_CCR_PCICLK_2 0x08
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#define TOPIC_CCR_CCLK 0x04
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#define TOPIC97_INT_CONTROL 0x00a1 /* 8 bit */
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#define TOPIC97_ICR_INTB 0x20
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#define TOPIC97_ICR_INTA 0x10
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#define TOPIC97_ICR_STSIRQNP 0x04
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#define TOPIC97_ICR_IRQNP 0x02
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#define TOPIC97_ICR_IRQSEL 0x01
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#define TOPIC_CARD_DETECT 0x00a3 /* 8 bit */
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#define TOPIC_CDR_MODE_PC32 0x80
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#define TOPIC_CDR_VS1 0x04
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#define TOPIC_CDR_VS2 0x02
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#define TOPIC_CDR_SW_DETECT 0x01
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#define TOPIC_REGISTER_CONTROL 0x00a4 /* 32 bit */
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#define TOPIC_RCR_RESUME_RESET 0x80000000
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#define TOPIC_RCR_REMOVE_RESET 0x40000000
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#define TOPIC97_RCR_CLKRUN_ENA 0x20000000
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#define TOPIC97_RCR_TESTMODE 0x10000000
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#define TOPIC97_RCR_IOPLUP 0x08000000
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#define TOPIC_RCR_BUFOFF_PWROFF 0x02000000
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#define TOPIC_RCR_BUFOFF_SIGOFF 0x01000000
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#define TOPIC97_RCR_CB_DEV_MASK 0x0000f800
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#define TOPIC97_RCR_CB_DEV_SHIFT 11
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#define TOPIC97_RCR_RI_DISABLE 0x00000004
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#define TOPIC97_RCR_CAUDIO_OFF 0x00000002
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#define TOPIC_RCR_CAUDIO_INVERT 0x00000001
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#define TOPIC97_MISC1 0x00ad /* 8bit */
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#define TOPIC97_MISC1_CLOCKRUN_ENABLE 0x80
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#define TOPIC97_MISC1_CLOCKRUN_MODE 0x40
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#define TOPIC97_MISC1_DETECT_REQ_ENA 0x10
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#define TOPIC97_MISC1_SCK_CLEAR_DIS 0x04
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#define TOPIC97_MISC1_R2_LOW_ENABLE 0x10
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#define TOPIC97_MISC2 0x00ae /* 8 bit */
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#define TOPIC97_MISC2_SPWRCLK_MASK 0x70
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#define TOPIC97_MISC2_SPWRMOD 0x08
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#define TOPIC97_MISC2_SPWR_ENABLE 0x04
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#define TOPIC97_MISC2_ZV_MODE 0x02
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#define TOPIC97_MISC2_ZV_ENABLE 0x01
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#define TOPIC97_ZOOM_VIDEO_CONTROL 0x009c /* 8 bit */
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#define TOPIC97_ZV_CONTROL_ENABLE 0x01
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#define TOPIC97_AUDIO_VIDEO_SWITCH 0x003c /* 8 bit */
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#define TOPIC97_AVS_AUDIO_CONTROL 0x02
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#define TOPIC97_AVS_VIDEO_CONTROL 0x01
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#define TOPIC_EXCA_IF_CONTROL 0x3e /* 8 bit */
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#define TOPIC_EXCA_IFC_33V_ENA 0x01
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#define TOPIC_PCI_CFG_PPBCN 0x3e /* 16-bit */
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#define TOPIC_PCI_CFG_PPBCN_WBEN 0x0400
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static void topic97_zoom_video(struct pcmcia_socket *sock, int onoff)
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{
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struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
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u8 reg_zv, reg;
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reg_zv = config_readb(socket, TOPIC97_ZOOM_VIDEO_CONTROL);
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if (onoff) {
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reg_zv |= TOPIC97_ZV_CONTROL_ENABLE;
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config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, reg_zv);
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reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH);
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reg |= TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL;
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config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg);
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} else {
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reg_zv &= ~TOPIC97_ZV_CONTROL_ENABLE;
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config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, reg_zv);
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reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH);
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reg &= ~(TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL);
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config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg);
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}
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}
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static int topic97_override(struct yenta_socket *socket)
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{
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/* ToPIC97/100 support ZV */
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socket->socket.zoom_video = topic97_zoom_video;
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return 0;
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}
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static int topic95_override(struct yenta_socket *socket)
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{
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u8 fctrl;
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u16 ppbcn;
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/* enable 3.3V support for 16bit cards */
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fctrl = exca_readb(socket, TOPIC_EXCA_IF_CONTROL);
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exca_writeb(socket, TOPIC_EXCA_IF_CONTROL, fctrl | TOPIC_EXCA_IFC_33V_ENA);
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/* tell yenta to use exca registers to power 16bit cards */
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socket->flags |= YENTA_16BIT_POWER_EXCA | YENTA_16BIT_POWER_DF;
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/* Disable write buffers to prevent lockups under load with numerous
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Cardbus cards, observed on Tecra 500CDT and reported elsewhere on the
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net. This is not a power-on default according to the datasheet
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but some BIOSes seem to set it. */
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if (pci_read_config_word(socket->dev, TOPIC_PCI_CFG_PPBCN, &ppbcn) == 0
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&& socket->dev->revision <= 7
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&& (ppbcn & TOPIC_PCI_CFG_PPBCN_WBEN)) {
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ppbcn &= ~TOPIC_PCI_CFG_PPBCN_WBEN;
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pci_write_config_word(socket->dev, TOPIC_PCI_CFG_PPBCN, ppbcn);
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dev_info(&socket->dev->dev, "Disabled ToPIC95 Cardbus write buffers.\n");
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}
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return 0;
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}
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#endif /* _LINUX_TOPIC_H */
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