/*
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* Copyright (C) 2015 Spreadtrum Communications Inc.
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*
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* Authors :
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* Keguang Zhang <keguang.zhang@spreadtrum.com>
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* Jingxiang Li <Jingxiang.li@spreadtrum.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __WL_INTF_H__
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#define __WL_INTF_H__
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#ifdef CPUFREQ_UPDATE_SUPPORT
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#include <linux/cpufreq.h>
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#endif /* CPUFREQ_UPDATE_SUPPORT */
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#include "wl_core.h"
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#include <wcn_bus.h>
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#define HW_TYPE_SDIO 0
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#define HW_TYPE_PCIE 1
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#define HW_TYPE_SIPC 2
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#define HW_TYPE_USB 3
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#define SDIO_RX_CMD_PORT 22
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#define SDIO_RX_PKT_LOG_PORT 23
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/*use port 24 because fifo_len = 8*/
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#define SDIO_RX_DATA_PORT 24
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#define SDIO_TX_CMD_PORT 8
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/*use port 10 because fifo_len = 8*/
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#define SDIO_TX_DATA_PORT 10
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#define PCIE_RX_CMD_PORT 22
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#define PCIE_RX_DATA_PORT 23
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#define PCIE_TX_CMD_PORT 2
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#define PCIE_TX_DATA_PORT 3
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#define USB_RX_CMD_PORT 20
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#define USB_RX_PKT_LOG_PORT 21
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#define USB_RX_DATA_PORT 22
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#define USB_TX_CMD_PORT 4
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#define USB_TX_DATA_PORT 6
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#define MSDU_DSCR_RSVD 5
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#define DEL_LUT_INDEX 0
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#define ADD_LUT_INDEX 1
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#define UPD_LUT_INDEX 2
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#define BOOST_TXNUM_LEVEL 16
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#define BOOST_RXNUM_LEVEL 16
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/*will not drop TCP ACK if TCPRX tp under this Mb level*/
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#define DROPACK_TP_TH_IN_M 40
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/*count RX TP timer in ms*/
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#define RX_TP_COUNT_IN_MS 500
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#ifdef SPRDWL_TX_SELF
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#include <linux/wakelock.h>
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struct sprdwl_tx_buf {
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unsigned char *base;
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unsigned short buf_len;
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unsigned short curpos;
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int change_size;
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};
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#endif
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#define MAX_CHN_NUM 16
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struct sprdwl_intf_ops {
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unsigned int max_num;
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void *intf;
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struct mchn_ops_t *hif_ops;
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};
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struct sdiohal_puh {
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unsigned int pad:6;
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unsigned int check_sum:1;
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unsigned int len:16;
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unsigned int eof:1;
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unsigned int subtype:4;
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unsigned int type:4;
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}; /* 32bits public header */
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struct tx_msdu_dscr {
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struct {
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/*0:cmd, 1:event, 2:normal data,*/
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/*3:special data, 4:PCIE remote addr*/
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unsigned char type:3;
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/*direction of address buffer of cmd/event,*/
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/*0:Tx, 1:Rx*/
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unsigned char direction_ind:1;
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unsigned char need_rsp:1;
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/*ctxt_id*/
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unsigned char interface:3;
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} common;
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unsigned char offset;
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struct {
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/*1:need HW to do checksum*/
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unsigned char checksum_offload:1;
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/*0:udp, 1:tcp*/
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unsigned char checksum_type:1;
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/*1:use SW rate,no aggregation 0:normal*/
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unsigned char sw_rate:1;
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/*WDS frame*/
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unsigned char wds:1;
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/*1:frame sent from SWQ to MH,
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*0:frame sent from TXQ to MH,
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default:0
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*/
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unsigned char swq_flag:1;
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unsigned char rsvd:1;
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/*used by PCIe address buffer, need set default:0*/
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unsigned char next_buffer_type:1;
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/*used by PCIe address buffer, need set default:0*/
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unsigned char pcie_mh_readcomp:1;
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} tx_ctrl;
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unsigned short pkt_len;
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struct {
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unsigned char msdu_tid:4;
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unsigned char mac_data_offset:4;
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} buffer_info;
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unsigned char sta_lut_index;
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unsigned char color_bit:2;
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unsigned short rsvd:14;
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unsigned short tcp_udp_header_offset;
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} __packed;
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struct pcie_addr_buffer {
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struct {
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unsigned char type:3;
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/*direction of address buffer of cmd/event,*/
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/*0:Tx, 1:Rx*/
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unsigned char direction_ind:1;
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unsigned char need_rsp:1;
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unsigned char interface:3;
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} common;
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unsigned short number;
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unsigned char offset;
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struct {
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unsigned char rsvd:6;
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unsigned char buffer_type:1;
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unsigned char buffer_inuse:1;
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} buffer_ctrl;
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unsigned char pcie_addr[0][5];
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} __packed;
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struct txc_addr_buff {
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struct {
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unsigned char type:3;
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unsigned char direction_ind:1;
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unsigned char need_rsp:1;
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unsigned char interface:3;
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} common;
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/*addr offset from common*/
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unsigned char offset;
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struct {
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unsigned char cksum:1;
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unsigned char cksum_type:1;
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unsigned char sw_ctrl:1;
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unsigned char wds:1;
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unsigned char swq_flag:1;
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unsigned char rsvd:1;
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/*0: data buffer, 1: address buffer*/
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unsigned char next_buffer_type:1;
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/*used only by address buffer*/
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/*0: MH process done, 1: before send to MH*/
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unsigned char mh_done:1;
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} tx_ctrl;
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unsigned short number;
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unsigned short rsvd;
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} __packed;
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#define GET_MSG_BUF(ptr) \
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((struct sprdwl_msg_buf *) \
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(*(unsigned long *)((ptr)->buf - sizeof(unsigned long *))))
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#if defined(MORE_DEBUG)
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#define STATS_COUNT 200
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#define UPDATE_TX_PACKETS(dev, tx_count, tx_bytes) do { \
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(dev)->stats.tx_packets += (tx_count); \
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(dev)->stats.tx_bytes += (tx_bytes); \
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(dev)->stats.gap_num += (tx_count); \
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} while (0)
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#endif
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#define DOT11_ADDBA_POLICY_DELAYED 0 /* delayed BA policy */
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#define DOT11_ADDBA_POLICY_IMMEDIATE 1 /* immediate BA policy */
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enum addba_req_result {
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ADDBA_REQ_RESULT_SUCCESS,
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ADDBA_REQ_RESULT_FAIL,
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ADDBA_REQ_RESULT_TIMEOUT,
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ADDBA_REQ_RESULT_DECLINE,
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};
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struct ieeetypes_addba_param {
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u16 amsdu_permit : 1;
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u16 ba_policy : 1;
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u16 tid : 4;
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u16 buffer_size : 10;
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} __packed;
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struct ieeetypes_delba_param {
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u16 reserved : 11;
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u16 initiator : 1;
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u16 tid : 4;
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} __packed;
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struct host_addba_param {
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u8 lut_index;
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u8 perr_mac_addr[6];
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u8 dialog_token;
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struct ieeetypes_addba_param addba_param;
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u16 timeout;
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} __packed;
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struct host_delba_param {
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u8 lut_index;
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u8 perr_mac_addr[6];
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struct ieeetypes_delba_param delba_param;
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u16 reason_code;
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} __packed;
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struct sprdwl_pop_work {
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int chn;
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void *head;
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void *tail;
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int num;
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};
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static inline bool sprdwl_is_group(unsigned char *addr)
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{
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if ((addr[0] & BIT(0)) != 0)
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return true;
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return false;
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}
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int sprdwl_intf_init(struct sprdwl_priv *priv, struct sprdwl_intf *intf);
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void sprdwl_intf_deinit(struct sprdwl_intf *dev);
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int if_tx_cmd(struct sprdwl_intf *intf, unsigned char *data, int len);
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int if_tx_addr_trans(struct sprdwl_intf *intf, unsigned char *data, int len);
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int sprdwl_intf_tx_list(struct sprdwl_intf *dev,
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struct list_head *tx_list,
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struct list_head *tx_list_head,
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int tx_count,
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int ac_index,
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u8 coex_bt_on);
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int sprdwl_intf_fill_msdu_dscr(struct sprdwl_vif *vif,
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struct sk_buff *skb,
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u8 type,
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u8 offset);
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int sprdwl_tx_free_pcie_data(struct sprdwl_intf *dev, unsigned char *data,
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unsigned short len);
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void *sprdwl_get_rx_data(struct sprdwl_intf *intf, void *pos, void **data,
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void **tran_data, int *len, int offset);
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void sprdwl_free_rx_data(struct sprdwl_intf *intf,
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int chn, void *head, void *tail, int num);
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#if defined FPGA_LOOPBACK_TEST
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int sprdwl_intf_tx_data_fpga_test(struct sprdwl_intf *intf,
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unsigned char *data, int len);
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int sprdwl_intf_fill_msdu_dscr_test(struct sprdwl_priv *priv,
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struct sk_buff *skb,
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u8 type,
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u8 offset);
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#endif /* FPGA_LOOPBACK_TEST */
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void sprdwl_hex_dump(unsigned char *name,
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unsigned char *data, unsigned short len);
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struct sprdwl_peer_entry
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*sprdwl_find_peer_entry_using_lut_index(struct sprdwl_intf *intf,
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unsigned char sta_lut_index);
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void sprdwl_event_sta_lut(struct sprdwl_vif *vif, u8 *data, u16 len);
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struct sprdwl_peer_entry
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*sprdwl_find_peer_entry_using_addr(struct sprdwl_vif *vif, u8 *addr);
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void sprdwl_tx_addba(struct sprdwl_intf *intf,
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struct sprdwl_peer_entry *peer_entry, unsigned char tid);
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void sprdwl_tx_delba(struct sprdwl_intf *intf,
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struct sprdwl_peer_entry *peer_entry, unsigned int ac_index);
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void sprdwl_tx_send_addba(struct sprdwl_vif *vif, void *data, int len);
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void sprdwl_tx_send_delba(struct sprdwl_vif *vif, void *data, int len);
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unsigned char sprdwl_find_lut_index(struct sprdwl_intf *intf,
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struct sprdwl_vif *vif);
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int sprdwl_dis_flush_txlist(struct sprdwl_intf *intf, u8 lut_index);
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void sprdwl_handle_pop_list(void *data);
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int sprdwl_add_topop_list(int chn, struct mbuf_t *head,
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struct mbuf_t *tail, int num);
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enum sprdwl_hw_type get_hwintf_type(void);
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void set_coex_bt_on_off(u8 action);
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#ifdef CPUFREQ_UPDATE_SUPPORT
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int sprdwl_notifier_boost(struct notifier_block *nb, unsigned long event, void *data);
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void sprdwl_boost(void);
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void sprdwl_unboost(void);
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#endif /* CPUFREQ_UPDATE_SUPPORT */
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void adjust_txnum_level(char *buf, unsigned char offset);
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void adjust_rxnum_level(char *buf, unsigned char offset);
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void sprdwl_bus_deinit(void);
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void sprdwl_count_rx_tp_tcp_ack(struct sprdwl_intf *intf, u32 len);
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#endif /* __SPRDWL_INTF_SDIO_SC2355_H__ */
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