/*
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* Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
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* Copyright (c) 2015 iComm Corporation
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SSV6200_COMMON_H_
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#define _SSV6200_COMMON_H_
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#define FW_VERSION_REG ADR_TX_SEG
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#define M_ENG_CPU 0x00
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#define M_ENG_HWHCI 0x01
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#define M_ENG_EMPTY 0x02
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#define M_ENG_ENCRYPT 0x03
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#define M_ENG_MACRX 0x04
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#define M_ENG_MIC 0x05
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#define M_ENG_TX_EDCA0 0x06
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#define M_ENG_TX_EDCA1 0x07
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#define M_ENG_TX_EDCA2 0x08
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#define M_ENG_TX_EDCA3 0x09
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#define M_ENG_TX_MNG 0x0A
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#define M_ENG_ENCRYPT_SEC 0x0B
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#define M_ENG_MIC_SEC 0x0C
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#define M_ENG_RESERVED_1 0x0D
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#define M_ENG_RESERVED_2 0x0E
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#define M_ENG_TRASH_CAN 0x0F
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#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
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#define M_CPU_HWENG 0x00
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#define M_CPU_TXL34CS 0x01
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#define M_CPU_RXL34CS 0x02
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#define M_CPU_DEFRAG 0x03
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#define M_CPU_EDCATX 0x04
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#define M_CPU_RXDATA 0x05
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#define M_CPU_RXMGMT 0x06
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#define M_CPU_RXCTRL 0x07
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#define M_CPU_FRAG 0x08
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#define M_CPU_TXTPUT 0x09
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#ifndef ID_TRAP_SW_TXTPUT
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#define ID_TRAP_SW_TXTPUT 50
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#endif
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#define M0_TXREQ 0
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#define M1_TXREQ 1
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#define M2_TXREQ 2
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#define M0_RXEVENT 3
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#define M2_RXEVENT 4
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#define HOST_CMD 5
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#define HOST_EVENT 6
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#define TEST_CMD 7
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#define SSV6XXX_RX_DESC_LEN \
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(sizeof(struct ssv6200_rx_desc) + \
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sizeof(struct ssv6200_rxphy_info))
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#define SSV6XXX_TX_DESC_LEN \
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(sizeof(struct ssv6200_tx_desc) + 0)
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#define TXPB_OFFSET 80
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#define RXPB_OFFSET 80
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#define SSV6200_TX_PKT_RSVD_SETTING 0x3
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#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
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#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
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#define SSV62XX_TX_MAX_RATES 3
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enum ssv6xxx_sr_bhvr {
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SUSPEND_RESUME_0,
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SUSPEND_RESUME_1,
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SUSPEND_RESUME_MAX
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};
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enum ssv6xxx_reboot_bhvr {
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SSV_SYS_REBOOT = 1,
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SSV_SYS_HALF,
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SSV_SYS_POWER_OFF
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};
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struct fw_rc_retry_params {
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u32 count:4;
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u32 drate:6;
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u32 crate:6;
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u32 rts_cts_nav:16;
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u32 frame_consume_time:10;
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u32 dl_length:12;
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u32 RSVD:10;
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} __attribute__((packed));
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struct ssv6200_tx_desc
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{
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u32 len:16;
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u32 c_type:3;
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u32 f80211:1;
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u32 qos:1;
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u32 ht:1;
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u32 use_4addr:1;
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u32 RSVD_0:3;
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u32 bc_que:1;
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u32 security:1;
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u32 more_data:1;
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u32 stype_b5b4:2;
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u32 extra_info:1;
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u32 fCmd;
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u32 hdr_offset:8;
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u32 frag:1;
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u32 unicast:1;
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u32 hdr_len:6;
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u32 tx_report:1;
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u32 tx_burst:1;
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u32 ack_policy:2;
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u32 aggregation:1;
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u32 RSVD_1:3;
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u32 do_rts_cts:2;
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u32 reason:6;
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u32 payload_offset:8;
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u32 RSVD_4:7;
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u32 RSVD_2:1;
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u32 fCmdIdx:3;
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u32 wsid:4;
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u32 txq_idx:3;
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u32 TxF_ID:6;
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u32 rts_cts_nav:16;
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u32 frame_consume_time:10;
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u32 crate_idx:6;
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u32 drate_idx:6;
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u32 dl_length:12;
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u32 RSVD_3:14;
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u32 RESERVED[8];
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struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
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};
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struct ssv6200_rx_desc
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{
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u32 len:16;
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u32 c_type:3;
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u32 f80211:1;
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u32 qos:1;
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u32 ht:1;
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u32 use_4addr:1;
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u32 l3cs_err:1;
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u32 l4cs_err:1;
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u32 align2:1;
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u32 RSVD_0:2;
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u32 psm:1;
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u32 stype_b5b4:2;
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u32 extra_info:1;
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u32 edca0_used:4;
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u32 edca1_used:5;
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u32 edca2_used:5;
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u32 edca3_used:5;
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u32 mng_used:4;
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u32 tx_page_used:9;
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u32 hdr_offset:8;
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u32 frag:1;
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u32 unicast:1;
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u32 hdr_len:6;
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u32 RxResult:8;
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u32 wildcard_bssid:1;
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u32 RSVD_1:1;
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u32 reason:6;
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u32 payload_offset:8;
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u32 tx_id_used:8;
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u32 fCmdIdx:3;
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u32 wsid:4;
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u32 RSVD_3:3;
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u32 rate_idx:6;
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};
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struct ssv6200_rxphy_info {
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u32 len:16;
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u32 rsvd0:16;
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u32 mode:3;
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u32 ch_bw:3;
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u32 preamble:1;
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u32 ht_short_gi:1;
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u32 rate:7;
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u32 rsvd1:1;
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u32 smoothing:1;
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u32 no_sounding:1;
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u32 aggregate:1;
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u32 stbc:2;
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u32 fec:1;
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u32 n_ess:2;
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u32 rsvd2:8;
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u32 l_length:12;
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u32 l_rate:3;
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u32 rsvd3:17;
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u32 rsvd4;
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u32 rpci:8;
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u32 snr:8;
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u32 service:16;
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};
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struct ssv6200_rxphy_info_padding {
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u32 rpci:8;
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u32 snr:8;
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u32 RSVD:16;
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};
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struct ssv6200_txphy_info {
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u32 rsvd[7];
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};
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#ifdef CONFIG_P2P_NOA
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struct ssv6xxx_p2p_noa_param {
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u32 duration;
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u32 interval;
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u32 start_time;
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u32 enable:8;
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u32 count:8;
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u8 addr[6];
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u8 vif_id;
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}__attribute__((packed));
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#endif
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typedef struct cfg_host_cmd {
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u32 len:16;
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u32 c_type:3;
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u32 RSVD0:5;
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u32 h_cmd:8;
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u32 cmd_seq_no;
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union {
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u32 dummy;
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u8 dat8[0];
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u16 dat16[0];
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u32 dat32[0];
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};
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} HDR_HostCmd;
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#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
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struct sdio_rxtput_cfg {
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u32 size_per_frame;
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u32 total_frames;
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};
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typedef enum{
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SSV6XXX_HOST_CMD_START = 0 ,
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SSV6XXX_HOST_CMD_LOG ,
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SSV6XXX_HOST_CMD_PS ,
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SSV6XXX_HOST_CMD_INIT_CALI ,
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SSV6XXX_HOST_CMD_RX_TPUT ,
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SSV6XXX_HOST_CMD_TX_TPUT ,
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SSV6XXX_HOST_CMD_WATCHDOG_START,
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SSV6XXX_HOST_CMD_WATCHDOG_STOP,
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#ifdef FW_WSID_WATCH_LIST
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SSV6XXX_HOST_CMD_WSID_OP ,
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#endif
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#ifdef CONFIG_P2P_NOA
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SSV6XXX_HOST_CMD_SET_NOA ,
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#endif
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SSV6XXX_HOST_SOC_CMD_MAXID ,
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}ssv6xxx_host_cmd_id;
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#define SSV_NUM_HW_STA 2
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typedef struct cfg_host_event {
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u32 len:16;
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u32 c_type:3;
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u32 RSVD0:5;
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u32 h_event:8;
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u32 evt_seq_no;
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u8 dat[0];
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} HDR_HostEvent;
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typedef enum{
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#ifdef USE_CMD_RESP
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SOC_EVT_CMD_RESP ,
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SOC_EVT_SCAN_RESULT ,
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SOC_EVT_DEAUTH ,
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#else
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SOC_EVT_GET_REG_RESP ,
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#endif
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SOC_EVT_NO_BA ,
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SOC_EVT_RC_MPDU_REPORT ,
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SOC_EVT_RC_AMPDU_REPORT ,
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SOC_EVT_LOG ,
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#ifdef CONFIG_P2P_NOA
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SOC_EVT_NOA ,
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#endif
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SOC_EVT_USER_END ,
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SOC_EVT_SDIO_TEST_COMMAND ,
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SOC_EVT_RESET_HOST ,
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SOC_EVT_SDIO_TXTPUT_RESULT ,
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SOC_EVT_WATCHDOG_TRIGGER ,
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SOC_EVT_TXLOOPBK_RESULT ,
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SOC_EVT_MAXID ,
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} ssv6xxx_soc_event;
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#ifdef CONFIG_P2P_NOA
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typedef enum{
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SSV6XXX_NOA_START = 0 ,
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SSV6XXX_NOA_STOP ,
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}ssv6xxx_host_noa_event;
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struct ssv62xx_noa_evt {
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u8 evt_id;
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u8 vif;
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} __attribute__((packed));
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#endif
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typedef enum{
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SSV6XXX_RC_COUNTER_CLEAR = 1 ,
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SSV6XXX_RC_REPORT ,
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}ssv6xxx_host_rate_control_event;
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#define MAX_AGGR_NUM (24)
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struct ssv62xx_tx_rate {
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s8 data_rate;
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u8 count;
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} __attribute__((packed));
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struct ampdu_ba_notify_data {
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u8 wsid;
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struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
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u16 seq_no[MAX_AGGR_NUM];
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} __attribute__((packed));
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struct firmware_rate_control_report_data{
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u8 wsid;
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struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
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u16 ampdu_len;
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u16 ampdu_ack_len;
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int ack_signal;
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} __attribute__((packed));
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#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
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#define SSV_RC_RATE_MAX 39
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#ifdef FW_WSID_WATCH_LIST
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enum SSV6XXX_WSID_OPS
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{
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SSV6XXX_WSID_OPS_ADD,
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SSV6XXX_WSID_OPS_DEL,
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SSV6XXX_WSID_OPS_RESETALL,
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SSV6XXX_WSID_OPS_ENABLE_CAPS,
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SSV6XXX_WSID_OPS_DISABLE_CAPS,
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SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
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SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
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SSV6XXX_WSID_OPS_MAX
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};
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enum SSV6XXX_WSID_SEC
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{
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SSV6XXX_WSID_SEC_NONE = 0,
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SSV6XXX_WSID_SEC_PAIRWISE = 1<<0,
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SSV6XXX_WSID_SEC_GROUP = 1<<1,
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};
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enum SSV6XXX_WSID_SEC_TYPE
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{
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SSV6XXX_WSID_SEC_SW,
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SSV6XXX_WSID_SEC_HW,
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SSV6XXX_WSID_SEC_TYPE_MAX
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};
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enum SSV6XXX_RETURN_STATE
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{
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SSV6XXX_STATE_OK,
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SSV6XXX_STATE_NG,
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SSV6XXX_STATE_MAX
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};
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struct ssv6xxx_wsid_params
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{
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u8 cmd;
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u8 wsid_idx;
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u8 target_wsid[6];
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u8 hw_security;
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};
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#endif
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struct ssv6xxx_iqk_cfg {
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u32 cfg_xtal:8;
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u32 cfg_pa:8;
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u32 cfg_pabias_ctrl:8;
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u32 cfg_pacascode_ctrl:8;
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u32 cfg_tssi_trgt:8;
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u32 cfg_tssi_div:8;
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u32 cfg_def_tx_scale_11b:8;
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u32 cfg_def_tx_scale_11b_p0d5:8;
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u32 cfg_def_tx_scale_11g:8;
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u32 cfg_def_tx_scale_11g_p0d5:8;
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u32 cmd_sel;
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union {
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u32 fx_sel;
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u32 argv;
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};
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u32 phy_tbl_size;
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u32 rf_tbl_size;
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};
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#define PHY_SETTING_SIZE sizeof(phy_setting)
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#ifdef CONFIG_SSV_CABRIO_E
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struct ssv6xxx_ch_cfg {
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u32 reg_addr;
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u32 ch1_12_value;
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u32 ch13_14_value;
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};
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#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
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#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
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#endif
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#define MAX_PHY_SETTING_TABLE_SIZE 1920
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#define MAX_RF_SETTING_TABLE_SIZE 512
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typedef enum {
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SSV6XXX_VOLT_DCDC_CONVERT = 0,
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SSV6XXX_VOLT_LDO_CONVERT,
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} ssv6xxx_cfg_volt;
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typedef enum {
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SSV6XXX_VOLT_33V = 0,
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SSV6XXX_VOLT_42V,
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} ssv6xxx_cfg_volt_value;
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typedef enum {
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SSV6XXX_IQK_CFG_XTAL_26M = 0,
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SSV6XXX_IQK_CFG_XTAL_40M,
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SSV6XXX_IQK_CFG_XTAL_24M,
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SSV6XXX_IQK_CFG_XTAL_MAX,
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} ssv6xxx_iqk_cfg_xtal;
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typedef enum {
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SSV6XXX_IQK_CFG_PA_DEF = 0,
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SSV6XXX_IQK_CFG_PA_LI_MPB,
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SSV6XXX_IQK_CFG_PA_LI_EVB,
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SSV6XXX_IQK_CFG_PA_HP,
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} ssv6xxx_iqk_cfg_pa;
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typedef enum {
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SSV6XXX_IQK_CMD_INIT_CALI = 0,
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SSV6XXX_IQK_CMD_RTBL_LOAD,
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SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
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SSV6XXX_IQK_CMD_RTBL_RESET,
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SSV6XXX_IQK_CMD_RTBL_SET,
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SSV6XXX_IQK_CMD_RTBL_EXPORT,
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SSV6XXX_IQK_CMD_TK_EVM,
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SSV6XXX_IQK_CMD_TK_TONE,
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SSV6XXX_IQK_CMD_TK_CHCH,
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} ssv6xxx_iqk_cmd_sel;
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#define SSV6XXX_IQK_TEMPERATURE 0x00000004
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#define SSV6XXX_IQK_RXDC 0x00000008
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#define SSV6XXX_IQK_RXRC 0x00000010
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#define SSV6XXX_IQK_TXDC 0x00000020
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#define SSV6XXX_IQK_TXIQ 0x00000040
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#define SSV6XXX_IQK_RXIQ 0x00000080
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#define SSV6XXX_IQK_TSSI 0x00000100
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#define SSV6XXX_IQK_PAPD 0x00000200
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typedef struct ssv_cabrio_reg_st {
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u32 address;
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u32 data;
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} ssv_cabrio_reg;
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typedef enum __PBuf_Type_E {
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NOTYPE_BUF = 0,
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TX_BUF = 1,
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RX_BUF = 2
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} PBuf_Type_E;
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struct SKB_info_st
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{
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struct ieee80211_sta *sta;
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u16 mpdu_retry_counter;
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unsigned long aggr_timestamp;
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u16 ampdu_tx_status;
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u16 ampdu_tx_final_retry_count;
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u16 lowest_rate;
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struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
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#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
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ktime_t timestamp;
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#endif
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#ifdef MULTI_THREAD_ENCRYPT
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volatile u8 crypt_st;
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#endif
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};
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typedef struct SKB_info_st SKB_info;
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typedef struct SKB_info_st *p_SKB_info;
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#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
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#ifdef MULTI_THREAD_ENCRYPT
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enum ssv_pkt_crypt_status
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{
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PKT_CRYPT_ST_DEC_PRE,
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PKT_CRYPT_ST_ENC_PRE,
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PKT_CRYPT_ST_DEC_DONE,
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PKT_CRYPT_ST_ENC_DONE,
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PKT_CRYPT_ST_FAIL,
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PKT_CRYPT_ST_NOT_SUPPORT
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};
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#endif
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#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
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#define SKB_DURATION_TIMEOUT_MS 100
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enum ssv_debug_skb_timestamp
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{
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SKB_DURATION_STAGE_TX_ENQ,
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SKB_DURATION_STAGE_TO_SDIO,
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SKB_DURATION_STAGE_IN_HWQ,
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SKB_DURATION_STAGE_END
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};
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#endif
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#define SSV6051Q_P1 0x00000000
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#define SSV6051Q_P2 0x70000000
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#define SSV6051Z 0x71000000
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#define SSV6051Q 0x73000000
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#define SSV6051P 0x75000000
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#ifdef CONFIG_SSV_CABRIO_E
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struct ssv6xxx_tx_loopback {
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u32 reg;
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u32 val;
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u32 restore_val;
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u8 restore;
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u8 delay_ms;
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};
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#endif
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#endif
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