/*
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* Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
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* Copyright (c) 2015 iComm Corporation
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define MCU_ENABLE_MSK 0x00000001
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#define MCU_ENABLE_I_MSK 0xfffffffe
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#define MCU_ENABLE_SFT 0
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#define MCU_ENABLE_HI 0
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#define MCU_ENABLE_SZ 1
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#define MAC_SW_RST_MSK 0x00000002
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#define MAC_SW_RST_I_MSK 0xfffffffd
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#define MAC_SW_RST_SFT 1
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#define MAC_SW_RST_HI 1
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#define MAC_SW_RST_SZ 1
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#define MCU_SW_RST_MSK 0x00000004
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#define MCU_SW_RST_I_MSK 0xfffffffb
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#define MCU_SW_RST_SFT 2
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#define MCU_SW_RST_HI 2
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#define MCU_SW_RST_SZ 1
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#define SDIO_SW_RST_MSK 0x00000008
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#define SDIO_SW_RST_I_MSK 0xfffffff7
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#define SDIO_SW_RST_SFT 3
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#define SDIO_SW_RST_HI 3
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#define SDIO_SW_RST_SZ 1
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#define SPI_SLV_SW_RST_MSK 0x00000010
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#define SPI_SLV_SW_RST_I_MSK 0xffffffef
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#define SPI_SLV_SW_RST_SFT 4
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#define SPI_SLV_SW_RST_HI 4
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#define SPI_SLV_SW_RST_SZ 1
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#define UART_SW_RST_MSK 0x00000020
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#define UART_SW_RST_I_MSK 0xffffffdf
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#define UART_SW_RST_SFT 5
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#define UART_SW_RST_HI 5
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#define UART_SW_RST_SZ 1
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#define DMA_SW_RST_MSK 0x00000040
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#define DMA_SW_RST_I_MSK 0xffffffbf
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#define DMA_SW_RST_SFT 6
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#define DMA_SW_RST_HI 6
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#define DMA_SW_RST_SZ 1
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#define WDT_SW_RST_MSK 0x00000080
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#define WDT_SW_RST_I_MSK 0xffffff7f
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#define WDT_SW_RST_SFT 7
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#define WDT_SW_RST_HI 7
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#define WDT_SW_RST_SZ 1
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#define I2C_SLV_SW_RST_MSK 0x00000100
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#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
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#define I2C_SLV_SW_RST_SFT 8
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#define I2C_SLV_SW_RST_HI 8
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#define I2C_SLV_SW_RST_SZ 1
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#define INT_CTL_SW_RST_MSK 0x00000200
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#define INT_CTL_SW_RST_I_MSK 0xfffffdff
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#define INT_CTL_SW_RST_SFT 9
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#define INT_CTL_SW_RST_HI 9
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#define INT_CTL_SW_RST_SZ 1
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#define BTCX_SW_RST_MSK 0x00000400
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#define BTCX_SW_RST_I_MSK 0xfffffbff
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#define BTCX_SW_RST_SFT 10
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#define BTCX_SW_RST_HI 10
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#define BTCX_SW_RST_SZ 1
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#define GPIO_SW_RST_MSK 0x00000800
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#define GPIO_SW_RST_I_MSK 0xfffff7ff
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#define GPIO_SW_RST_SFT 11
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#define GPIO_SW_RST_HI 11
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#define GPIO_SW_RST_SZ 1
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#define US0TMR_SW_RST_MSK 0x00001000
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#define US0TMR_SW_RST_I_MSK 0xffffefff
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#define US0TMR_SW_RST_SFT 12
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#define US0TMR_SW_RST_HI 12
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#define US0TMR_SW_RST_SZ 1
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#define US1TMR_SW_RST_MSK 0x00002000
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#define US1TMR_SW_RST_I_MSK 0xffffdfff
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#define US1TMR_SW_RST_SFT 13
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#define US1TMR_SW_RST_HI 13
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#define US1TMR_SW_RST_SZ 1
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#define US2TMR_SW_RST_MSK 0x00004000
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#define US2TMR_SW_RST_I_MSK 0xffffbfff
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#define US2TMR_SW_RST_SFT 14
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#define US2TMR_SW_RST_HI 14
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#define US2TMR_SW_RST_SZ 1
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#define US3TMR_SW_RST_MSK 0x00008000
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#define US3TMR_SW_RST_I_MSK 0xffff7fff
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#define US3TMR_SW_RST_SFT 15
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#define US3TMR_SW_RST_HI 15
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#define US3TMR_SW_RST_SZ 1
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#define MS0TMR_SW_RST_MSK 0x00010000
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#define MS0TMR_SW_RST_I_MSK 0xfffeffff
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#define MS0TMR_SW_RST_SFT 16
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#define MS0TMR_SW_RST_HI 16
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#define MS0TMR_SW_RST_SZ 1
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#define MS1TMR_SW_RST_MSK 0x00020000
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#define MS1TMR_SW_RST_I_MSK 0xfffdffff
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#define MS1TMR_SW_RST_SFT 17
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#define MS1TMR_SW_RST_HI 17
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#define MS1TMR_SW_RST_SZ 1
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#define MS2TMR_SW_RST_MSK 0x00040000
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#define MS2TMR_SW_RST_I_MSK 0xfffbffff
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#define MS2TMR_SW_RST_SFT 18
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#define MS2TMR_SW_RST_HI 18
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#define MS2TMR_SW_RST_SZ 1
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#define MS3TMR_SW_RST_MSK 0x00080000
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#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
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#define MS3TMR_SW_RST_SFT 19
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#define MS3TMR_SW_RST_HI 19
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#define MS3TMR_SW_RST_SZ 1
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#define RF_BB_SW_RST_MSK 0x00100000
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#define RF_BB_SW_RST_I_MSK 0xffefffff
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#define RF_BB_SW_RST_SFT 20
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#define RF_BB_SW_RST_HI 20
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#define RF_BB_SW_RST_SZ 1
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#define SYS_ALL_RST_MSK 0x00200000
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#define SYS_ALL_RST_I_MSK 0xffdfffff
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#define SYS_ALL_RST_SFT 21
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#define SYS_ALL_RST_HI 21
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#define SYS_ALL_RST_SZ 1
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#define DAT_UART_SW_RST_MSK 0x00400000
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#define DAT_UART_SW_RST_I_MSK 0xffbfffff
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#define DAT_UART_SW_RST_SFT 22
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#define DAT_UART_SW_RST_HI 22
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#define DAT_UART_SW_RST_SZ 1
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#define I2C_MST_SW_RST_MSK 0x00800000
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#define I2C_MST_SW_RST_I_MSK 0xff7fffff
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#define I2C_MST_SW_RST_SFT 23
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#define I2C_MST_SW_RST_HI 23
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#define I2C_MST_SW_RST_SZ 1
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#define RG_REBOOT_MSK 0x00000001
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#define RG_REBOOT_I_MSK 0xfffffffe
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#define RG_REBOOT_SFT 0
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#define RG_REBOOT_HI 0
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#define RG_REBOOT_SZ 1
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#define TRAP_IMG_FLS_MSK 0x00010000
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#define TRAP_IMG_FLS_I_MSK 0xfffeffff
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#define TRAP_IMG_FLS_SFT 16
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#define TRAP_IMG_FLS_HI 16
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#define TRAP_IMG_FLS_SZ 1
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#define TRAP_REBOOT_MSK 0x00020000
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#define TRAP_REBOOT_I_MSK 0xfffdffff
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#define TRAP_REBOOT_SFT 17
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#define TRAP_REBOOT_HI 17
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#define TRAP_REBOOT_SZ 1
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#define TRAP_BOOT_FLS_MSK 0x00040000
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#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
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#define TRAP_BOOT_FLS_SFT 18
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#define TRAP_BOOT_FLS_HI 18
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#define TRAP_BOOT_FLS_SZ 1
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#define CHIP_ID_31_0_MSK 0xffffffff
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#define CHIP_ID_31_0_I_MSK 0x00000000
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#define CHIP_ID_31_0_SFT 0
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#define CHIP_ID_31_0_HI 31
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#define CHIP_ID_31_0_SZ 32
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#define CHIP_ID_63_32_MSK 0xffffffff
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#define CHIP_ID_63_32_I_MSK 0x00000000
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#define CHIP_ID_63_32_SFT 0
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#define CHIP_ID_63_32_HI 31
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#define CHIP_ID_63_32_SZ 32
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#define CHIP_ID_95_64_MSK 0xffffffff
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#define CHIP_ID_95_64_I_MSK 0x00000000
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#define CHIP_ID_95_64_SFT 0
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#define CHIP_ID_95_64_HI 31
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#define CHIP_ID_95_64_SZ 32
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#define CHIP_ID_127_96_MSK 0xffffffff
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#define CHIP_ID_127_96_I_MSK 0x00000000
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#define CHIP_ID_127_96_SFT 0
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#define CHIP_ID_127_96_HI 31
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#define CHIP_ID_127_96_SZ 32
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#define CK_SEL_1_0_MSK 0x00000003
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#define CK_SEL_1_0_I_MSK 0xfffffffc
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#define CK_SEL_1_0_SFT 0
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#define CK_SEL_1_0_HI 1
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#define CK_SEL_1_0_SZ 2
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#define CK_SEL_2_MSK 0x00000004
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#define CK_SEL_2_I_MSK 0xfffffffb
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#define CK_SEL_2_SFT 2
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#define CK_SEL_2_HI 2
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#define CK_SEL_2_SZ 1
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#define SYS_CLK_EN_MSK 0x00000001
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#define SYS_CLK_EN_I_MSK 0xfffffffe
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#define SYS_CLK_EN_SFT 0
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#define SYS_CLK_EN_HI 0
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#define SYS_CLK_EN_SZ 1
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#define MAC_CLK_EN_MSK 0x00000002
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#define MAC_CLK_EN_I_MSK 0xfffffffd
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#define MAC_CLK_EN_SFT 1
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#define MAC_CLK_EN_HI 1
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#define MAC_CLK_EN_SZ 1
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#define MCU_CLK_EN_MSK 0x00000004
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#define MCU_CLK_EN_I_MSK 0xfffffffb
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#define MCU_CLK_EN_SFT 2
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#define MCU_CLK_EN_HI 2
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#define MCU_CLK_EN_SZ 1
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#define SDIO_CLK_EN_MSK 0x00000008
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#define SDIO_CLK_EN_I_MSK 0xfffffff7
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#define SDIO_CLK_EN_SFT 3
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#define SDIO_CLK_EN_HI 3
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#define SDIO_CLK_EN_SZ 1
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#define SPI_SLV_CLK_EN_MSK 0x00000010
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#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
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#define SPI_SLV_CLK_EN_SFT 4
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#define SPI_SLV_CLK_EN_HI 4
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#define SPI_SLV_CLK_EN_SZ 1
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#define UART_CLK_EN_MSK 0x00000020
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#define UART_CLK_EN_I_MSK 0xffffffdf
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#define UART_CLK_EN_SFT 5
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#define UART_CLK_EN_HI 5
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#define UART_CLK_EN_SZ 1
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#define DMA_CLK_EN_MSK 0x00000040
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#define DMA_CLK_EN_I_MSK 0xffffffbf
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#define DMA_CLK_EN_SFT 6
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#define DMA_CLK_EN_HI 6
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#define DMA_CLK_EN_SZ 1
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#define WDT_CLK_EN_MSK 0x00000080
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#define WDT_CLK_EN_I_MSK 0xffffff7f
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#define WDT_CLK_EN_SFT 7
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#define WDT_CLK_EN_HI 7
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#define WDT_CLK_EN_SZ 1
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#define I2C_SLV_CLK_EN_MSK 0x00000100
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#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
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#define I2C_SLV_CLK_EN_SFT 8
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#define I2C_SLV_CLK_EN_HI 8
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#define I2C_SLV_CLK_EN_SZ 1
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#define INT_CTL_CLK_EN_MSK 0x00000200
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#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
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#define INT_CTL_CLK_EN_SFT 9
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#define INT_CTL_CLK_EN_HI 9
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#define INT_CTL_CLK_EN_SZ 1
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#define BTCX_CLK_EN_MSK 0x00000400
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#define BTCX_CLK_EN_I_MSK 0xfffffbff
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#define BTCX_CLK_EN_SFT 10
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#define BTCX_CLK_EN_HI 10
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#define BTCX_CLK_EN_SZ 1
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#define GPIO_CLK_EN_MSK 0x00000800
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#define GPIO_CLK_EN_I_MSK 0xfffff7ff
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#define GPIO_CLK_EN_SFT 11
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#define GPIO_CLK_EN_HI 11
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#define GPIO_CLK_EN_SZ 1
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#define US0TMR_CLK_EN_MSK 0x00001000
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#define US0TMR_CLK_EN_I_MSK 0xffffefff
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#define US0TMR_CLK_EN_SFT 12
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#define US0TMR_CLK_EN_HI 12
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#define US0TMR_CLK_EN_SZ 1
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#define US1TMR_CLK_EN_MSK 0x00002000
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#define US1TMR_CLK_EN_I_MSK 0xffffdfff
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#define US1TMR_CLK_EN_SFT 13
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#define US1TMR_CLK_EN_HI 13
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#define US1TMR_CLK_EN_SZ 1
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#define US2TMR_CLK_EN_MSK 0x00004000
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#define US2TMR_CLK_EN_I_MSK 0xffffbfff
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#define US2TMR_CLK_EN_SFT 14
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#define US2TMR_CLK_EN_HI 14
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#define US2TMR_CLK_EN_SZ 1
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#define US3TMR_CLK_EN_MSK 0x00008000
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#define US3TMR_CLK_EN_I_MSK 0xffff7fff
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#define US3TMR_CLK_EN_SFT 15
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#define US3TMR_CLK_EN_HI 15
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#define US3TMR_CLK_EN_SZ 1
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#define MS0TMR_CLK_EN_MSK 0x00010000
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#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
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#define MS0TMR_CLK_EN_SFT 16
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#define MS0TMR_CLK_EN_HI 16
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#define MS0TMR_CLK_EN_SZ 1
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#define MS1TMR_CLK_EN_MSK 0x00020000
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#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
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#define MS1TMR_CLK_EN_SFT 17
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#define MS1TMR_CLK_EN_HI 17
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#define MS1TMR_CLK_EN_SZ 1
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#define MS2TMR_CLK_EN_MSK 0x00040000
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#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
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#define MS2TMR_CLK_EN_SFT 18
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#define MS2TMR_CLK_EN_HI 18
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#define MS2TMR_CLK_EN_SZ 1
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#define MS3TMR_CLK_EN_MSK 0x00080000
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#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
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#define MS3TMR_CLK_EN_SFT 19
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#define MS3TMR_CLK_EN_HI 19
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#define MS3TMR_CLK_EN_SZ 1
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#define BIST_CLK_EN_MSK 0x00100000
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#define BIST_CLK_EN_I_MSK 0xffefffff
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#define BIST_CLK_EN_SFT 20
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#define BIST_CLK_EN_HI 20
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#define BIST_CLK_EN_SZ 1
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#define I2C_MST_CLK_EN_MSK 0x00800000
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#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
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#define I2C_MST_CLK_EN_SFT 23
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#define I2C_MST_CLK_EN_HI 23
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#define I2C_MST_CLK_EN_SZ 1
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#define BTCX_CSR_CLK_EN_MSK 0x00000400
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#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
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#define BTCX_CSR_CLK_EN_SFT 10
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#define BTCX_CSR_CLK_EN_HI 10
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#define BTCX_CSR_CLK_EN_SZ 1
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#define MCU_DBG_SEL_MSK 0x0000003f
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#define MCU_DBG_SEL_I_MSK 0xffffffc0
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#define MCU_DBG_SEL_SFT 0
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#define MCU_DBG_SEL_HI 5
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#define MCU_DBG_SEL_SZ 6
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#define MCU_STOP_NOGRANT_MSK 0x00000100
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#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
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#define MCU_STOP_NOGRANT_SFT 8
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#define MCU_STOP_NOGRANT_HI 8
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#define MCU_STOP_NOGRANT_SZ 1
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#define MCU_STOP_ANYTIME_MSK 0x00000200
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#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
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#define MCU_STOP_ANYTIME_SFT 9
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#define MCU_STOP_ANYTIME_HI 9
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#define MCU_STOP_ANYTIME_SZ 1
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#define MCU_DBG_DATA_MSK 0xffffffff
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#define MCU_DBG_DATA_I_MSK 0x00000000
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#define MCU_DBG_DATA_SFT 0
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#define MCU_DBG_DATA_HI 31
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#define MCU_DBG_DATA_SZ 32
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#define AHB_SW_RST_MSK 0x00000001
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#define AHB_SW_RST_I_MSK 0xfffffffe
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#define AHB_SW_RST_SFT 0
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#define AHB_SW_RST_HI 0
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#define AHB_SW_RST_SZ 1
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#define AHB_ERR_RST_MSK 0x00000002
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#define AHB_ERR_RST_I_MSK 0xfffffffd
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#define AHB_ERR_RST_SFT 1
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#define AHB_ERR_RST_HI 1
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#define AHB_ERR_RST_SZ 1
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#define REG_AHB_DEBUG_MX_MSK 0x00000030
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#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
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#define REG_AHB_DEBUG_MX_SFT 4
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#define REG_AHB_DEBUG_MX_HI 5
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#define REG_AHB_DEBUG_MX_SZ 2
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#define REG_PKT_W_NBRT_MSK 0x00000100
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#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
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#define REG_PKT_W_NBRT_SFT 8
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#define REG_PKT_W_NBRT_HI 8
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#define REG_PKT_W_NBRT_SZ 1
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#define REG_PKT_R_NBRT_MSK 0x00000200
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#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
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#define REG_PKT_R_NBRT_SFT 9
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#define REG_PKT_R_NBRT_HI 9
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#define REG_PKT_R_NBRT_SZ 1
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#define IQ_SRAM_SEL_0_MSK 0x00001000
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#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
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#define IQ_SRAM_SEL_0_SFT 12
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#define IQ_SRAM_SEL_0_HI 12
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#define IQ_SRAM_SEL_0_SZ 1
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#define IQ_SRAM_SEL_1_MSK 0x00002000
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#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
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#define IQ_SRAM_SEL_1_SFT 13
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#define IQ_SRAM_SEL_1_HI 13
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#define IQ_SRAM_SEL_1_SZ 1
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#define IQ_SRAM_SEL_2_MSK 0x00004000
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#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
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#define IQ_SRAM_SEL_2_SFT 14
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#define IQ_SRAM_SEL_2_HI 14
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#define IQ_SRAM_SEL_2_SZ 1
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#define AHB_STATUS_MSK 0xffff0000
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#define AHB_STATUS_I_MSK 0x0000ffff
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#define AHB_STATUS_SFT 16
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#define AHB_STATUS_HI 31
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#define AHB_STATUS_SZ 16
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#define PARALLEL_DR_MSK 0x00000001
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#define PARALLEL_DR_I_MSK 0xfffffffe
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#define PARALLEL_DR_SFT 0
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#define PARALLEL_DR_HI 0
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#define PARALLEL_DR_SZ 1
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#define MBRUN_MSK 0x00000010
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#define MBRUN_I_MSK 0xffffffef
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#define MBRUN_SFT 4
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#define MBRUN_HI 4
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#define MBRUN_SZ 1
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#define SHIFT_DR_MSK 0x00000100
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#define SHIFT_DR_I_MSK 0xfffffeff
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#define SHIFT_DR_SFT 8
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#define SHIFT_DR_HI 8
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#define SHIFT_DR_SZ 1
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#define MODE_REG_SI_MSK 0x00000200
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#define MODE_REG_SI_I_MSK 0xfffffdff
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#define MODE_REG_SI_SFT 9
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#define MODE_REG_SI_HI 9
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#define MODE_REG_SI_SZ 1
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#define SIMULATION_MODE_MSK 0x00000400
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#define SIMULATION_MODE_I_MSK 0xfffffbff
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#define SIMULATION_MODE_SFT 10
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#define SIMULATION_MODE_HI 10
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#define SIMULATION_MODE_SZ 1
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#define DBIST_MODE_MSK 0x00000800
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#define DBIST_MODE_I_MSK 0xfffff7ff
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#define DBIST_MODE_SFT 11
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#define DBIST_MODE_HI 11
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#define DBIST_MODE_SZ 1
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#define MODE_REG_IN_MSK 0x001fffff
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#define MODE_REG_IN_I_MSK 0xffe00000
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#define MODE_REG_IN_SFT 0
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#define MODE_REG_IN_HI 20
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#define MODE_REG_IN_SZ 21
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#define MODE_REG_OUT_MCU_MSK 0x001fffff
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#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
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#define MODE_REG_OUT_MCU_SFT 0
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#define MODE_REG_OUT_MCU_HI 20
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#define MODE_REG_OUT_MCU_SZ 21
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#define MODE_REG_SO_MCU_MSK 0x80000000
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#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
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#define MODE_REG_SO_MCU_SFT 31
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#define MODE_REG_SO_MCU_HI 31
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#define MODE_REG_SO_MCU_SZ 1
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#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
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#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
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#define MONITOR_BUS_MCU_31_0_SFT 0
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#define MONITOR_BUS_MCU_31_0_HI 31
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#define MONITOR_BUS_MCU_31_0_SZ 32
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#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
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#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
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#define MONITOR_BUS_MCU_33_32_SFT 0
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#define MONITOR_BUS_MCU_33_32_HI 1
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#define MONITOR_BUS_MCU_33_32_SZ 2
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#define TB_ADR_SEL_MSK 0x0000ffff
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#define TB_ADR_SEL_I_MSK 0xffff0000
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#define TB_ADR_SEL_SFT 0
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#define TB_ADR_SEL_HI 15
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#define TB_ADR_SEL_SZ 16
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#define TB_CS_MSK 0x80000000
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#define TB_CS_I_MSK 0x7fffffff
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#define TB_CS_SFT 31
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#define TB_CS_HI 31
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#define TB_CS_SZ 1
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#define TB_RDATA_MSK 0xffffffff
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#define TB_RDATA_I_MSK 0x00000000
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#define TB_RDATA_SFT 0
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#define TB_RDATA_HI 31
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#define TB_RDATA_SZ 32
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#define UART_W2B_EN_MSK 0x00000001
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#define UART_W2B_EN_I_MSK 0xfffffffe
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#define UART_W2B_EN_SFT 0
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#define UART_W2B_EN_HI 0
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#define UART_W2B_EN_SZ 1
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#define DATA_UART_W2B_EN_MSK 0x00000010
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#define DATA_UART_W2B_EN_I_MSK 0xffffffef
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#define DATA_UART_W2B_EN_SFT 4
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#define DATA_UART_W2B_EN_HI 4
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#define DATA_UART_W2B_EN_SZ 1
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#define AHB_ILL_ADDR_MSK 0xffffffff
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#define AHB_ILL_ADDR_I_MSK 0x00000000
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#define AHB_ILL_ADDR_SFT 0
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#define AHB_ILL_ADDR_HI 31
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#define AHB_ILL_ADDR_SZ 32
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#define AHB_FEN_ADDR_MSK 0xffffffff
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#define AHB_FEN_ADDR_I_MSK 0x00000000
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#define AHB_FEN_ADDR_SFT 0
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#define AHB_FEN_ADDR_HI 31
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#define AHB_FEN_ADDR_SZ 32
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#define ILL_ADDR_CLR_MSK 0x00000001
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#define ILL_ADDR_CLR_I_MSK 0xfffffffe
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#define ILL_ADDR_CLR_SFT 0
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#define ILL_ADDR_CLR_HI 0
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#define ILL_ADDR_CLR_SZ 1
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#define FENCE_HIT_CLR_MSK 0x00000002
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#define FENCE_HIT_CLR_I_MSK 0xfffffffd
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#define FENCE_HIT_CLR_SFT 1
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#define FENCE_HIT_CLR_HI 1
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#define FENCE_HIT_CLR_SZ 1
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#define ILL_ADDR_INT_MSK 0x00000010
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#define ILL_ADDR_INT_I_MSK 0xffffffef
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#define ILL_ADDR_INT_SFT 4
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#define ILL_ADDR_INT_HI 4
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#define ILL_ADDR_INT_SZ 1
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#define FENCE_HIT_INT_MSK 0x00000020
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#define FENCE_HIT_INT_I_MSK 0xffffffdf
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#define FENCE_HIT_INT_SFT 5
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#define FENCE_HIT_INT_HI 5
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#define FENCE_HIT_INT_SZ 1
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#define PWM_INI_VALUE_P_A_MSK 0x000000ff
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#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
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#define PWM_INI_VALUE_P_A_SFT 0
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#define PWM_INI_VALUE_P_A_HI 7
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#define PWM_INI_VALUE_P_A_SZ 8
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#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
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#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
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#define PWM_INI_VALUE_N_A_SFT 8
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#define PWM_INI_VALUE_N_A_HI 15
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#define PWM_INI_VALUE_N_A_SZ 8
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#define PWM_POST_SCALER_A_MSK 0x000f0000
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#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
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#define PWM_POST_SCALER_A_SFT 16
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#define PWM_POST_SCALER_A_HI 19
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#define PWM_POST_SCALER_A_SZ 4
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#define PWM_ALWAYSON_A_MSK 0x20000000
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#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
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#define PWM_ALWAYSON_A_SFT 29
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#define PWM_ALWAYSON_A_HI 29
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#define PWM_ALWAYSON_A_SZ 1
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#define PWM_INVERT_A_MSK 0x40000000
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#define PWM_INVERT_A_I_MSK 0xbfffffff
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#define PWM_INVERT_A_SFT 30
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#define PWM_INVERT_A_HI 30
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#define PWM_INVERT_A_SZ 1
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#define PWM_ENABLE_A_MSK 0x80000000
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#define PWM_ENABLE_A_I_MSK 0x7fffffff
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#define PWM_ENABLE_A_SFT 31
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#define PWM_ENABLE_A_HI 31
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#define PWM_ENABLE_A_SZ 1
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#define PWM_INI_VALUE_P_B_MSK 0x000000ff
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#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
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#define PWM_INI_VALUE_P_B_SFT 0
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#define PWM_INI_VALUE_P_B_HI 7
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#define PWM_INI_VALUE_P_B_SZ 8
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#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
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#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
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#define PWM_INI_VALUE_N_B_SFT 8
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#define PWM_INI_VALUE_N_B_HI 15
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#define PWM_INI_VALUE_N_B_SZ 8
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#define PWM_POST_SCALER_B_MSK 0x000f0000
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#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
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#define PWM_POST_SCALER_B_SFT 16
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#define PWM_POST_SCALER_B_HI 19
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#define PWM_POST_SCALER_B_SZ 4
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#define PWM_ALWAYSON_B_MSK 0x20000000
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#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
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#define PWM_ALWAYSON_B_SFT 29
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#define PWM_ALWAYSON_B_HI 29
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#define PWM_ALWAYSON_B_SZ 1
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#define PWM_INVERT_B_MSK 0x40000000
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#define PWM_INVERT_B_I_MSK 0xbfffffff
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#define PWM_INVERT_B_SFT 30
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#define PWM_INVERT_B_HI 30
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#define PWM_INVERT_B_SZ 1
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#define PWM_ENABLE_B_MSK 0x80000000
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#define PWM_ENABLE_B_I_MSK 0x7fffffff
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#define PWM_ENABLE_B_SFT 31
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#define PWM_ENABLE_B_HI 31
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#define PWM_ENABLE_B_SZ 1
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#define HBUSREQ_LOCK_MSK 0x00001fff
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#define HBUSREQ_LOCK_I_MSK 0xffffe000
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#define HBUSREQ_LOCK_SFT 0
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#define HBUSREQ_LOCK_HI 12
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#define HBUSREQ_LOCK_SZ 13
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#define HBURST_LOCK_MSK 0x00001fff
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#define HBURST_LOCK_I_MSK 0xffffe000
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#define HBURST_LOCK_SFT 0
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#define HBURST_LOCK_HI 12
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#define HBURST_LOCK_SZ 13
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#define PRESCALER_USTIMER_MSK 0x000001ff
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#define PRESCALER_USTIMER_I_MSK 0xfffffe00
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#define PRESCALER_USTIMER_SFT 0
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#define PRESCALER_USTIMER_HI 8
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#define PRESCALER_USTIMER_SZ 9
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#define MODE_REG_IN_MMU_MSK 0x0000ffff
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#define MODE_REG_IN_MMU_I_MSK 0xffff0000
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#define MODE_REG_IN_MMU_SFT 0
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#define MODE_REG_IN_MMU_HI 15
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#define MODE_REG_IN_MMU_SZ 16
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#define MODE_REG_OUT_MMU_MSK 0x0000ffff
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#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
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#define MODE_REG_OUT_MMU_SFT 0
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#define MODE_REG_OUT_MMU_HI 15
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#define MODE_REG_OUT_MMU_SZ 16
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#define MODE_REG_SO_MMU_MSK 0x80000000
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#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
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#define MODE_REG_SO_MMU_SFT 31
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#define MODE_REG_SO_MMU_HI 31
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#define MODE_REG_SO_MMU_SZ 1
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#define MONITOR_BUS_MMU_MSK 0x0007ffff
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#define MONITOR_BUS_MMU_I_MSK 0xfff80000
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#define MONITOR_BUS_MMU_SFT 0
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#define MONITOR_BUS_MMU_HI 18
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#define MONITOR_BUS_MMU_SZ 19
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#define TEST_MODE0_MSK 0x00000001
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#define TEST_MODE0_I_MSK 0xfffffffe
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#define TEST_MODE0_SFT 0
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#define TEST_MODE0_HI 0
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#define TEST_MODE0_SZ 1
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#define TEST_MODE1_MSK 0x00000002
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#define TEST_MODE1_I_MSK 0xfffffffd
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#define TEST_MODE1_SFT 1
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#define TEST_MODE1_HI 1
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#define TEST_MODE1_SZ 1
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#define TEST_MODE2_MSK 0x00000004
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#define TEST_MODE2_I_MSK 0xfffffffb
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#define TEST_MODE2_SFT 2
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#define TEST_MODE2_HI 2
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#define TEST_MODE2_SZ 1
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#define TEST_MODE3_MSK 0x00000008
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#define TEST_MODE3_I_MSK 0xfffffff7
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#define TEST_MODE3_SFT 3
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#define TEST_MODE3_HI 3
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#define TEST_MODE3_SZ 1
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#define TEST_MODE4_MSK 0x00000010
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#define TEST_MODE4_I_MSK 0xffffffef
|
#define TEST_MODE4_SFT 4
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#define TEST_MODE4_HI 4
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#define TEST_MODE4_SZ 1
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#define TEST_MODE_ALL_MSK 0x00000020
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#define TEST_MODE_ALL_I_MSK 0xffffffdf
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#define TEST_MODE_ALL_SFT 5
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#define TEST_MODE_ALL_HI 5
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#define TEST_MODE_ALL_SZ 1
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#define WDT_INIT_MSK 0x00000001
|
#define WDT_INIT_I_MSK 0xfffffffe
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#define WDT_INIT_SFT 0
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#define WDT_INIT_HI 0
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#define WDT_INIT_SZ 1
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#define SD_HOST_INIT_MSK 0x00000002
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#define SD_HOST_INIT_I_MSK 0xfffffffd
|
#define SD_HOST_INIT_SFT 1
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#define SD_HOST_INIT_HI 1
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#define SD_HOST_INIT_SZ 1
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#define ALLOW_SD_RESET_MSK 0x00000001
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#define ALLOW_SD_RESET_I_MSK 0xfffffffe
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#define ALLOW_SD_RESET_SFT 0
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#define ALLOW_SD_RESET_HI 0
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#define ALLOW_SD_RESET_SZ 1
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#define UART_NRTS_MSK 0x00000001
|
#define UART_NRTS_I_MSK 0xfffffffe
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#define UART_NRTS_SFT 0
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#define UART_NRTS_HI 0
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#define UART_NRTS_SZ 1
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#define UART_NCTS_MSK 0x00000002
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#define UART_NCTS_I_MSK 0xfffffffd
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#define UART_NCTS_SFT 1
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#define UART_NCTS_HI 1
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#define UART_NCTS_SZ 1
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#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
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#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
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#define TU0_TM_INIT_VALUE_SFT 0
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#define TU0_TM_INIT_VALUE_HI 15
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#define TU0_TM_INIT_VALUE_SZ 16
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#define TU0_TM_MODE_MSK 0x00010000
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#define TU0_TM_MODE_I_MSK 0xfffeffff
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#define TU0_TM_MODE_SFT 16
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#define TU0_TM_MODE_HI 16
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#define TU0_TM_MODE_SZ 1
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#define TU0_TM_INT_STS_DONE_MSK 0x00020000
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#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
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#define TU0_TM_INT_STS_DONE_SFT 17
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#define TU0_TM_INT_STS_DONE_HI 17
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#define TU0_TM_INT_STS_DONE_SZ 1
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#define TU0_TM_INT_MASK_MSK 0x00040000
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#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
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#define TU0_TM_INT_MASK_SFT 18
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#define TU0_TM_INT_MASK_HI 18
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#define TU0_TM_INT_MASK_SZ 1
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#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
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#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
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#define TU0_TM_CUR_VALUE_SFT 0
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#define TU0_TM_CUR_VALUE_HI 15
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#define TU0_TM_CUR_VALUE_SZ 16
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#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
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#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
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#define TU1_TM_INIT_VALUE_SFT 0
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#define TU1_TM_INIT_VALUE_HI 15
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#define TU1_TM_INIT_VALUE_SZ 16
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#define TU1_TM_MODE_MSK 0x00010000
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#define TU1_TM_MODE_I_MSK 0xfffeffff
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#define TU1_TM_MODE_SFT 16
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#define TU1_TM_MODE_HI 16
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#define TU1_TM_MODE_SZ 1
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#define TU1_TM_INT_STS_DONE_MSK 0x00020000
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#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
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#define TU1_TM_INT_STS_DONE_SFT 17
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#define TU1_TM_INT_STS_DONE_HI 17
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#define TU1_TM_INT_STS_DONE_SZ 1
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#define TU1_TM_INT_MASK_MSK 0x00040000
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#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TU1_TM_INT_MASK_SFT 18
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#define TU1_TM_INT_MASK_HI 18
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#define TU1_TM_INT_MASK_SZ 1
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#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
|
#define TU1_TM_CUR_VALUE_SFT 0
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#define TU1_TM_CUR_VALUE_HI 15
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#define TU1_TM_CUR_VALUE_SZ 16
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#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
|
#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
|
#define TU2_TM_INIT_VALUE_SFT 0
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#define TU2_TM_INIT_VALUE_HI 15
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#define TU2_TM_INIT_VALUE_SZ 16
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#define TU2_TM_MODE_MSK 0x00010000
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#define TU2_TM_MODE_I_MSK 0xfffeffff
|
#define TU2_TM_MODE_SFT 16
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#define TU2_TM_MODE_HI 16
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#define TU2_TM_MODE_SZ 1
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#define TU2_TM_INT_STS_DONE_MSK 0x00020000
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#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
|
#define TU2_TM_INT_STS_DONE_SFT 17
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#define TU2_TM_INT_STS_DONE_HI 17
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#define TU2_TM_INT_STS_DONE_SZ 1
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#define TU2_TM_INT_MASK_MSK 0x00040000
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#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TU2_TM_INT_MASK_SFT 18
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#define TU2_TM_INT_MASK_HI 18
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#define TU2_TM_INT_MASK_SZ 1
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#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
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#define TU2_TM_CUR_VALUE_SFT 0
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#define TU2_TM_CUR_VALUE_HI 15
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#define TU2_TM_CUR_VALUE_SZ 16
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#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
|
#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
|
#define TU3_TM_INIT_VALUE_SFT 0
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#define TU3_TM_INIT_VALUE_HI 15
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#define TU3_TM_INIT_VALUE_SZ 16
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#define TU3_TM_MODE_MSK 0x00010000
|
#define TU3_TM_MODE_I_MSK 0xfffeffff
|
#define TU3_TM_MODE_SFT 16
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#define TU3_TM_MODE_HI 16
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#define TU3_TM_MODE_SZ 1
|
#define TU3_TM_INT_STS_DONE_MSK 0x00020000
|
#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
|
#define TU3_TM_INT_STS_DONE_SFT 17
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#define TU3_TM_INT_STS_DONE_HI 17
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#define TU3_TM_INT_STS_DONE_SZ 1
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#define TU3_TM_INT_MASK_MSK 0x00040000
|
#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TU3_TM_INT_MASK_SFT 18
|
#define TU3_TM_INT_MASK_HI 18
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#define TU3_TM_INT_MASK_SZ 1
|
#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
|
#define TU3_TM_CUR_VALUE_SFT 0
|
#define TU3_TM_CUR_VALUE_HI 15
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#define TU3_TM_CUR_VALUE_SZ 16
|
#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
|
#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
|
#define TM0_TM_INIT_VALUE_SFT 0
|
#define TM0_TM_INIT_VALUE_HI 15
|
#define TM0_TM_INIT_VALUE_SZ 16
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#define TM0_TM_MODE_MSK 0x00010000
|
#define TM0_TM_MODE_I_MSK 0xfffeffff
|
#define TM0_TM_MODE_SFT 16
|
#define TM0_TM_MODE_HI 16
|
#define TM0_TM_MODE_SZ 1
|
#define TM0_TM_INT_STS_DONE_MSK 0x00020000
|
#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
|
#define TM0_TM_INT_STS_DONE_SFT 17
|
#define TM0_TM_INT_STS_DONE_HI 17
|
#define TM0_TM_INT_STS_DONE_SZ 1
|
#define TM0_TM_INT_MASK_MSK 0x00040000
|
#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TM0_TM_INT_MASK_SFT 18
|
#define TM0_TM_INT_MASK_HI 18
|
#define TM0_TM_INT_MASK_SZ 1
|
#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
|
#define TM0_TM_CUR_VALUE_SFT 0
|
#define TM0_TM_CUR_VALUE_HI 15
|
#define TM0_TM_CUR_VALUE_SZ 16
|
#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
|
#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
|
#define TM1_TM_INIT_VALUE_SFT 0
|
#define TM1_TM_INIT_VALUE_HI 15
|
#define TM1_TM_INIT_VALUE_SZ 16
|
#define TM1_TM_MODE_MSK 0x00010000
|
#define TM1_TM_MODE_I_MSK 0xfffeffff
|
#define TM1_TM_MODE_SFT 16
|
#define TM1_TM_MODE_HI 16
|
#define TM1_TM_MODE_SZ 1
|
#define TM1_TM_INT_STS_DONE_MSK 0x00020000
|
#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
|
#define TM1_TM_INT_STS_DONE_SFT 17
|
#define TM1_TM_INT_STS_DONE_HI 17
|
#define TM1_TM_INT_STS_DONE_SZ 1
|
#define TM1_TM_INT_MASK_MSK 0x00040000
|
#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TM1_TM_INT_MASK_SFT 18
|
#define TM1_TM_INT_MASK_HI 18
|
#define TM1_TM_INT_MASK_SZ 1
|
#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
|
#define TM1_TM_CUR_VALUE_SFT 0
|
#define TM1_TM_CUR_VALUE_HI 15
|
#define TM1_TM_CUR_VALUE_SZ 16
|
#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
|
#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
|
#define TM2_TM_INIT_VALUE_SFT 0
|
#define TM2_TM_INIT_VALUE_HI 15
|
#define TM2_TM_INIT_VALUE_SZ 16
|
#define TM2_TM_MODE_MSK 0x00010000
|
#define TM2_TM_MODE_I_MSK 0xfffeffff
|
#define TM2_TM_MODE_SFT 16
|
#define TM2_TM_MODE_HI 16
|
#define TM2_TM_MODE_SZ 1
|
#define TM2_TM_INT_STS_DONE_MSK 0x00020000
|
#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
|
#define TM2_TM_INT_STS_DONE_SFT 17
|
#define TM2_TM_INT_STS_DONE_HI 17
|
#define TM2_TM_INT_STS_DONE_SZ 1
|
#define TM2_TM_INT_MASK_MSK 0x00040000
|
#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TM2_TM_INT_MASK_SFT 18
|
#define TM2_TM_INT_MASK_HI 18
|
#define TM2_TM_INT_MASK_SZ 1
|
#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
|
#define TM2_TM_CUR_VALUE_SFT 0
|
#define TM2_TM_CUR_VALUE_HI 15
|
#define TM2_TM_CUR_VALUE_SZ 16
|
#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
|
#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
|
#define TM3_TM_INIT_VALUE_SFT 0
|
#define TM3_TM_INIT_VALUE_HI 15
|
#define TM3_TM_INIT_VALUE_SZ 16
|
#define TM3_TM_MODE_MSK 0x00010000
|
#define TM3_TM_MODE_I_MSK 0xfffeffff
|
#define TM3_TM_MODE_SFT 16
|
#define TM3_TM_MODE_HI 16
|
#define TM3_TM_MODE_SZ 1
|
#define TM3_TM_INT_STS_DONE_MSK 0x00020000
|
#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
|
#define TM3_TM_INT_STS_DONE_SFT 17
|
#define TM3_TM_INT_STS_DONE_HI 17
|
#define TM3_TM_INT_STS_DONE_SZ 1
|
#define TM3_TM_INT_MASK_MSK 0x00040000
|
#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
|
#define TM3_TM_INT_MASK_SFT 18
|
#define TM3_TM_INT_MASK_HI 18
|
#define TM3_TM_INT_MASK_SZ 1
|
#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
|
#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
|
#define TM3_TM_CUR_VALUE_SFT 0
|
#define TM3_TM_CUR_VALUE_HI 15
|
#define TM3_TM_CUR_VALUE_SZ 16
|
#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
|
#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
|
#define MCU_WDT_TIME_CNT_SFT 0
|
#define MCU_WDT_TIME_CNT_HI 15
|
#define MCU_WDT_TIME_CNT_SZ 16
|
#define MCU_WDT_STATUS_MSK 0x00020000
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#define MCU_WDT_STATUS_I_MSK 0xfffdffff
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#define MCU_WDT_STATUS_SFT 17
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#define MCU_WDT_STATUS_HI 17
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#define MCU_WDT_STATUS_SZ 1
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#define MCU_WDOG_ENA_MSK 0x80000000
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#define MCU_WDOG_ENA_I_MSK 0x7fffffff
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#define MCU_WDOG_ENA_SFT 31
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#define MCU_WDOG_ENA_HI 31
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#define MCU_WDOG_ENA_SZ 1
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#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
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#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
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#define SYS_WDT_TIME_CNT_SFT 0
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#define SYS_WDT_TIME_CNT_HI 15
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#define SYS_WDT_TIME_CNT_SZ 16
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#define SYS_WDT_STATUS_MSK 0x00020000
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#define SYS_WDT_STATUS_I_MSK 0xfffdffff
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#define SYS_WDT_STATUS_SFT 17
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#define SYS_WDT_STATUS_HI 17
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#define SYS_WDT_STATUS_SZ 1
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#define SYS_WDOG_ENA_MSK 0x80000000
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#define SYS_WDOG_ENA_I_MSK 0x7fffffff
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#define SYS_WDOG_ENA_SFT 31
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#define SYS_WDOG_ENA_HI 31
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#define SYS_WDOG_ENA_SZ 1
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#define XLNA_EN_O_OE_MSK 0x00000001
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#define XLNA_EN_O_OE_I_MSK 0xfffffffe
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#define XLNA_EN_O_OE_SFT 0
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#define XLNA_EN_O_OE_HI 0
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#define XLNA_EN_O_OE_SZ 1
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#define XLNA_EN_O_PE_MSK 0x00000002
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#define XLNA_EN_O_PE_I_MSK 0xfffffffd
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#define XLNA_EN_O_PE_SFT 1
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#define XLNA_EN_O_PE_HI 1
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#define XLNA_EN_O_PE_SZ 1
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#define PAD6_IE_MSK 0x00000008
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#define PAD6_IE_I_MSK 0xfffffff7
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#define PAD6_IE_SFT 3
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#define PAD6_IE_HI 3
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#define PAD6_IE_SZ 1
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#define PAD6_SEL_I_MSK 0x00000030
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#define PAD6_SEL_I_I_MSK 0xffffffcf
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#define PAD6_SEL_I_SFT 4
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#define PAD6_SEL_I_HI 5
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#define PAD6_SEL_I_SZ 2
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#define PAD6_OD_MSK 0x00000100
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#define PAD6_OD_I_MSK 0xfffffeff
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#define PAD6_OD_SFT 8
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#define PAD6_OD_HI 8
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#define PAD6_OD_SZ 1
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#define PAD6_SEL_O_MSK 0x00001000
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#define PAD6_SEL_O_I_MSK 0xffffefff
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#define PAD6_SEL_O_SFT 12
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#define PAD6_SEL_O_HI 12
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#define PAD6_SEL_O_SZ 1
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#define XLNA_EN_O_C_MSK 0x10000000
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#define XLNA_EN_O_C_I_MSK 0xefffffff
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#define XLNA_EN_O_C_SFT 28
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#define XLNA_EN_O_C_HI 28
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#define XLNA_EN_O_C_SZ 1
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#define WIFI_TX_SW_O_OE_MSK 0x00000001
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#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
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#define WIFI_TX_SW_O_OE_SFT 0
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#define WIFI_TX_SW_O_OE_HI 0
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#define WIFI_TX_SW_O_OE_SZ 1
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#define WIFI_TX_SW_O_PE_MSK 0x00000002
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#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
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#define WIFI_TX_SW_O_PE_SFT 1
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#define WIFI_TX_SW_O_PE_HI 1
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#define WIFI_TX_SW_O_PE_SZ 1
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#define PAD7_IE_MSK 0x00000008
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#define PAD7_IE_I_MSK 0xfffffff7
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#define PAD7_IE_SFT 3
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#define PAD7_IE_HI 3
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#define PAD7_IE_SZ 1
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#define PAD7_SEL_I_MSK 0x00000030
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#define PAD7_SEL_I_I_MSK 0xffffffcf
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#define PAD7_SEL_I_SFT 4
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#define PAD7_SEL_I_HI 5
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#define PAD7_SEL_I_SZ 2
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#define PAD7_OD_MSK 0x00000100
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#define PAD7_OD_I_MSK 0xfffffeff
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#define PAD7_OD_SFT 8
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#define PAD7_OD_HI 8
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#define PAD7_OD_SZ 1
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#define PAD7_SEL_O_MSK 0x00001000
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#define PAD7_SEL_O_I_MSK 0xffffefff
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#define PAD7_SEL_O_SFT 12
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#define PAD7_SEL_O_HI 12
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#define PAD7_SEL_O_SZ 1
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#define WIFI_TX_SW_O_C_MSK 0x10000000
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#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
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#define WIFI_TX_SW_O_C_SFT 28
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#define WIFI_TX_SW_O_C_HI 28
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#define WIFI_TX_SW_O_C_SZ 1
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#define WIFI_RX_SW_O_OE_MSK 0x00000001
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#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
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#define WIFI_RX_SW_O_OE_SFT 0
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#define WIFI_RX_SW_O_OE_HI 0
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#define WIFI_RX_SW_O_OE_SZ 1
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#define WIFI_RX_SW_O_PE_MSK 0x00000002
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#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
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#define WIFI_RX_SW_O_PE_SFT 1
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#define WIFI_RX_SW_O_PE_HI 1
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#define WIFI_RX_SW_O_PE_SZ 1
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#define PAD8_IE_MSK 0x00000008
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#define PAD8_IE_I_MSK 0xfffffff7
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#define PAD8_IE_SFT 3
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#define PAD8_IE_HI 3
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#define PAD8_IE_SZ 1
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#define PAD8_SEL_I_MSK 0x00000030
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#define PAD8_SEL_I_I_MSK 0xffffffcf
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#define PAD8_SEL_I_SFT 4
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#define PAD8_SEL_I_HI 5
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#define PAD8_SEL_I_SZ 2
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#define PAD8_OD_MSK 0x00000100
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#define PAD8_OD_I_MSK 0xfffffeff
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#define PAD8_OD_SFT 8
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#define PAD8_OD_HI 8
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#define PAD8_OD_SZ 1
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#define WIFI_RX_SW_O_C_MSK 0x10000000
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#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
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#define WIFI_RX_SW_O_C_SFT 28
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#define WIFI_RX_SW_O_C_HI 28
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#define WIFI_RX_SW_O_C_SZ 1
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#define BT_SW_O_OE_MSK 0x00000001
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#define BT_SW_O_OE_I_MSK 0xfffffffe
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#define BT_SW_O_OE_SFT 0
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#define BT_SW_O_OE_HI 0
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#define BT_SW_O_OE_SZ 1
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#define BT_SW_O_PE_MSK 0x00000002
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#define BT_SW_O_PE_I_MSK 0xfffffffd
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#define BT_SW_O_PE_SFT 1
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#define BT_SW_O_PE_HI 1
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#define BT_SW_O_PE_SZ 1
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#define PAD9_IE_MSK 0x00000008
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#define PAD9_IE_I_MSK 0xfffffff7
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#define PAD9_IE_SFT 3
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#define PAD9_IE_HI 3
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#define PAD9_IE_SZ 1
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#define PAD9_SEL_I_MSK 0x00000030
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#define PAD9_SEL_I_I_MSK 0xffffffcf
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#define PAD9_SEL_I_SFT 4
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#define PAD9_SEL_I_HI 5
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#define PAD9_SEL_I_SZ 2
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#define PAD9_OD_MSK 0x00000100
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#define PAD9_OD_I_MSK 0xfffffeff
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#define PAD9_OD_SFT 8
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#define PAD9_OD_HI 8
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#define PAD9_OD_SZ 1
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#define PAD9_SEL_O_MSK 0x00001000
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#define PAD9_SEL_O_I_MSK 0xffffefff
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#define PAD9_SEL_O_SFT 12
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#define PAD9_SEL_O_HI 12
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#define PAD9_SEL_O_SZ 1
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#define BT_SW_O_C_MSK 0x10000000
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#define BT_SW_O_C_I_MSK 0xefffffff
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#define BT_SW_O_C_SFT 28
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#define BT_SW_O_C_HI 28
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#define BT_SW_O_C_SZ 1
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#define XPA_EN_O_OE_MSK 0x00000001
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#define XPA_EN_O_OE_I_MSK 0xfffffffe
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#define XPA_EN_O_OE_SFT 0
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#define XPA_EN_O_OE_HI 0
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#define XPA_EN_O_OE_SZ 1
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#define XPA_EN_O_PE_MSK 0x00000002
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#define XPA_EN_O_PE_I_MSK 0xfffffffd
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#define XPA_EN_O_PE_SFT 1
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#define XPA_EN_O_PE_HI 1
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#define XPA_EN_O_PE_SZ 1
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#define PAD11_IE_MSK 0x00000008
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#define PAD11_IE_I_MSK 0xfffffff7
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#define PAD11_IE_SFT 3
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#define PAD11_IE_HI 3
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#define PAD11_IE_SZ 1
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#define PAD11_SEL_I_MSK 0x00000030
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#define PAD11_SEL_I_I_MSK 0xffffffcf
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#define PAD11_SEL_I_SFT 4
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#define PAD11_SEL_I_HI 5
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#define PAD11_SEL_I_SZ 2
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#define PAD11_OD_MSK 0x00000100
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#define PAD11_OD_I_MSK 0xfffffeff
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#define PAD11_OD_SFT 8
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#define PAD11_OD_HI 8
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#define PAD11_OD_SZ 1
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#define PAD11_SEL_O_MSK 0x00001000
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#define PAD11_SEL_O_I_MSK 0xffffefff
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#define PAD11_SEL_O_SFT 12
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#define PAD11_SEL_O_HI 12
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#define PAD11_SEL_O_SZ 1
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#define XPA_EN_O_C_MSK 0x10000000
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#define XPA_EN_O_C_I_MSK 0xefffffff
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#define XPA_EN_O_C_SFT 28
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#define XPA_EN_O_C_HI 28
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#define XPA_EN_O_C_SZ 1
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#define PAD15_OE_MSK 0x00000001
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#define PAD15_OE_I_MSK 0xfffffffe
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#define PAD15_OE_SFT 0
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#define PAD15_OE_HI 0
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#define PAD15_OE_SZ 1
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#define PAD15_PE_MSK 0x00000002
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#define PAD15_PE_I_MSK 0xfffffffd
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#define PAD15_PE_SFT 1
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#define PAD15_PE_HI 1
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#define PAD15_PE_SZ 1
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#define PAD15_DS_MSK 0x00000004
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#define PAD15_DS_I_MSK 0xfffffffb
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#define PAD15_DS_SFT 2
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#define PAD15_DS_HI 2
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#define PAD15_DS_SZ 1
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#define PAD15_IE_MSK 0x00000008
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#define PAD15_IE_I_MSK 0xfffffff7
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#define PAD15_IE_SFT 3
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#define PAD15_IE_HI 3
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#define PAD15_IE_SZ 1
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#define PAD15_SEL_I_MSK 0x00000030
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#define PAD15_SEL_I_I_MSK 0xffffffcf
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#define PAD15_SEL_I_SFT 4
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#define PAD15_SEL_I_HI 5
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#define PAD15_SEL_I_SZ 2
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#define PAD15_OD_MSK 0x00000100
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#define PAD15_OD_I_MSK 0xfffffeff
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#define PAD15_OD_SFT 8
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#define PAD15_OD_HI 8
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#define PAD15_OD_SZ 1
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#define PAD15_SEL_O_MSK 0x00001000
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#define PAD15_SEL_O_I_MSK 0xffffefff
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#define PAD15_SEL_O_SFT 12
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#define PAD15_SEL_O_HI 12
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#define PAD15_SEL_O_SZ 1
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#define TEST_1_ID_MSK 0x10000000
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#define TEST_1_ID_I_MSK 0xefffffff
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#define TEST_1_ID_SFT 28
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#define TEST_1_ID_HI 28
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#define TEST_1_ID_SZ 1
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#define PAD16_OE_MSK 0x00000001
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#define PAD16_OE_I_MSK 0xfffffffe
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#define PAD16_OE_SFT 0
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#define PAD16_OE_HI 0
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#define PAD16_OE_SZ 1
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#define PAD16_PE_MSK 0x00000002
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#define PAD16_PE_I_MSK 0xfffffffd
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#define PAD16_PE_SFT 1
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#define PAD16_PE_HI 1
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#define PAD16_PE_SZ 1
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#define PAD16_DS_MSK 0x00000004
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#define PAD16_DS_I_MSK 0xfffffffb
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#define PAD16_DS_SFT 2
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#define PAD16_DS_HI 2
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#define PAD16_DS_SZ 1
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#define PAD16_IE_MSK 0x00000008
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#define PAD16_IE_I_MSK 0xfffffff7
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#define PAD16_IE_SFT 3
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#define PAD16_IE_HI 3
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#define PAD16_IE_SZ 1
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#define PAD16_SEL_I_MSK 0x00000030
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#define PAD16_SEL_I_I_MSK 0xffffffcf
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#define PAD16_SEL_I_SFT 4
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#define PAD16_SEL_I_HI 5
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#define PAD16_SEL_I_SZ 2
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#define PAD16_OD_MSK 0x00000100
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#define PAD16_OD_I_MSK 0xfffffeff
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#define PAD16_OD_SFT 8
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#define PAD16_OD_HI 8
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#define PAD16_OD_SZ 1
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#define PAD16_SEL_O_MSK 0x00001000
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#define PAD16_SEL_O_I_MSK 0xffffefff
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#define PAD16_SEL_O_SFT 12
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#define PAD16_SEL_O_HI 12
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#define PAD16_SEL_O_SZ 1
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#define TEST_2_ID_MSK 0x10000000
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#define TEST_2_ID_I_MSK 0xefffffff
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#define TEST_2_ID_SFT 28
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#define TEST_2_ID_HI 28
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#define TEST_2_ID_SZ 1
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#define PAD17_OE_MSK 0x00000001
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#define PAD17_OE_I_MSK 0xfffffffe
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#define PAD17_OE_SFT 0
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#define PAD17_OE_HI 0
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#define PAD17_OE_SZ 1
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#define PAD17_PE_MSK 0x00000002
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#define PAD17_PE_I_MSK 0xfffffffd
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#define PAD17_PE_SFT 1
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#define PAD17_PE_HI 1
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#define PAD17_PE_SZ 1
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#define PAD17_DS_MSK 0x00000004
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#define PAD17_DS_I_MSK 0xfffffffb
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#define PAD17_DS_SFT 2
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#define PAD17_DS_HI 2
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#define PAD17_DS_SZ 1
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#define PAD17_IE_MSK 0x00000008
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#define PAD17_IE_I_MSK 0xfffffff7
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#define PAD17_IE_SFT 3
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#define PAD17_IE_HI 3
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#define PAD17_IE_SZ 1
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#define PAD17_SEL_I_MSK 0x00000030
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#define PAD17_SEL_I_I_MSK 0xffffffcf
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#define PAD17_SEL_I_SFT 4
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#define PAD17_SEL_I_HI 5
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#define PAD17_SEL_I_SZ 2
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#define PAD17_OD_MSK 0x00000100
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#define PAD17_OD_I_MSK 0xfffffeff
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#define PAD17_OD_SFT 8
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#define PAD17_OD_HI 8
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#define PAD17_OD_SZ 1
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#define PAD17_SEL_O_MSK 0x00001000
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#define PAD17_SEL_O_I_MSK 0xffffefff
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#define PAD17_SEL_O_SFT 12
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#define PAD17_SEL_O_HI 12
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#define PAD17_SEL_O_SZ 1
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#define TEST_3_ID_MSK 0x10000000
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#define TEST_3_ID_I_MSK 0xefffffff
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#define TEST_3_ID_SFT 28
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#define TEST_3_ID_HI 28
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#define TEST_3_ID_SZ 1
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#define PAD18_OE_MSK 0x00000001
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#define PAD18_OE_I_MSK 0xfffffffe
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#define PAD18_OE_SFT 0
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#define PAD18_OE_HI 0
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#define PAD18_OE_SZ 1
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#define PAD18_PE_MSK 0x00000002
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#define PAD18_PE_I_MSK 0xfffffffd
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#define PAD18_PE_SFT 1
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#define PAD18_PE_HI 1
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#define PAD18_PE_SZ 1
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#define PAD18_DS_MSK 0x00000004
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#define PAD18_DS_I_MSK 0xfffffffb
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#define PAD18_DS_SFT 2
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#define PAD18_DS_HI 2
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#define PAD18_DS_SZ 1
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#define PAD18_IE_MSK 0x00000008
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#define PAD18_IE_I_MSK 0xfffffff7
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#define PAD18_IE_SFT 3
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#define PAD18_IE_HI 3
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#define PAD18_IE_SZ 1
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#define PAD18_SEL_I_MSK 0x00000030
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#define PAD18_SEL_I_I_MSK 0xffffffcf
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#define PAD18_SEL_I_SFT 4
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#define PAD18_SEL_I_HI 5
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#define PAD18_SEL_I_SZ 2
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#define PAD18_OD_MSK 0x00000100
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#define PAD18_OD_I_MSK 0xfffffeff
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#define PAD18_OD_SFT 8
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#define PAD18_OD_HI 8
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#define PAD18_OD_SZ 1
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#define PAD18_SEL_O_MSK 0x00003000
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#define PAD18_SEL_O_I_MSK 0xffffcfff
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#define PAD18_SEL_O_SFT 12
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#define PAD18_SEL_O_HI 13
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#define PAD18_SEL_O_SZ 2
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#define TEST_4_ID_MSK 0x10000000
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#define TEST_4_ID_I_MSK 0xefffffff
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#define TEST_4_ID_SFT 28
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#define TEST_4_ID_HI 28
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#define TEST_4_ID_SZ 1
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#define PAD19_OE_MSK 0x00000001
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#define PAD19_OE_I_MSK 0xfffffffe
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#define PAD19_OE_SFT 0
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#define PAD19_OE_HI 0
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#define PAD19_OE_SZ 1
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#define PAD19_PE_MSK 0x00000002
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#define PAD19_PE_I_MSK 0xfffffffd
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#define PAD19_PE_SFT 1
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#define PAD19_PE_HI 1
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#define PAD19_PE_SZ 1
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#define PAD19_DS_MSK 0x00000004
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#define PAD19_DS_I_MSK 0xfffffffb
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#define PAD19_DS_SFT 2
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#define PAD19_DS_HI 2
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#define PAD19_DS_SZ 1
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#define PAD19_IE_MSK 0x00000008
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#define PAD19_IE_I_MSK 0xfffffff7
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#define PAD19_IE_SFT 3
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#define PAD19_IE_HI 3
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#define PAD19_IE_SZ 1
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#define PAD19_SEL_I_MSK 0x00000030
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#define PAD19_SEL_I_I_MSK 0xffffffcf
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#define PAD19_SEL_I_SFT 4
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#define PAD19_SEL_I_HI 5
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#define PAD19_SEL_I_SZ 2
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#define PAD19_OD_MSK 0x00000100
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#define PAD19_OD_I_MSK 0xfffffeff
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#define PAD19_OD_SFT 8
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#define PAD19_OD_HI 8
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#define PAD19_OD_SZ 1
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#define PAD19_SEL_O_MSK 0x00007000
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#define PAD19_SEL_O_I_MSK 0xffff8fff
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#define PAD19_SEL_O_SFT 12
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#define PAD19_SEL_O_HI 14
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#define PAD19_SEL_O_SZ 3
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#define SHORT_TO_20_ID_MSK 0x10000000
|
#define SHORT_TO_20_ID_I_MSK 0xefffffff
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#define SHORT_TO_20_ID_SFT 28
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#define SHORT_TO_20_ID_HI 28
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#define SHORT_TO_20_ID_SZ 1
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#define PAD20_OE_MSK 0x00000001
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#define PAD20_OE_I_MSK 0xfffffffe
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#define PAD20_OE_SFT 0
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#define PAD20_OE_HI 0
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#define PAD20_OE_SZ 1
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#define PAD20_PE_MSK 0x00000002
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#define PAD20_PE_I_MSK 0xfffffffd
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#define PAD20_PE_SFT 1
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#define PAD20_PE_HI 1
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#define PAD20_PE_SZ 1
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#define PAD20_DS_MSK 0x00000004
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#define PAD20_DS_I_MSK 0xfffffffb
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#define PAD20_DS_SFT 2
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#define PAD20_DS_HI 2
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#define PAD20_DS_SZ 1
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#define PAD20_IE_MSK 0x00000008
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#define PAD20_IE_I_MSK 0xfffffff7
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#define PAD20_IE_SFT 3
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#define PAD20_IE_HI 3
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#define PAD20_IE_SZ 1
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#define PAD20_SEL_I_MSK 0x000000f0
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#define PAD20_SEL_I_I_MSK 0xffffff0f
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#define PAD20_SEL_I_SFT 4
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#define PAD20_SEL_I_HI 7
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#define PAD20_SEL_I_SZ 4
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#define PAD20_OD_MSK 0x00000100
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#define PAD20_OD_I_MSK 0xfffffeff
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#define PAD20_OD_SFT 8
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#define PAD20_OD_HI 8
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#define PAD20_OD_SZ 1
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#define PAD20_SEL_O_MSK 0x00003000
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#define PAD20_SEL_O_I_MSK 0xffffcfff
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#define PAD20_SEL_O_SFT 12
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#define PAD20_SEL_O_HI 13
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#define PAD20_SEL_O_SZ 2
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#define STRAP0_MSK 0x08000000
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#define STRAP0_I_MSK 0xf7ffffff
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#define STRAP0_SFT 27
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#define STRAP0_HI 27
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#define STRAP0_SZ 1
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#define GPIO_TEST_1_ID_MSK 0x10000000
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#define GPIO_TEST_1_ID_I_MSK 0xefffffff
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#define GPIO_TEST_1_ID_SFT 28
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#define GPIO_TEST_1_ID_HI 28
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#define GPIO_TEST_1_ID_SZ 1
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#define PAD21_OE_MSK 0x00000001
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#define PAD21_OE_I_MSK 0xfffffffe
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#define PAD21_OE_SFT 0
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#define PAD21_OE_HI 0
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#define PAD21_OE_SZ 1
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#define PAD21_PE_MSK 0x00000002
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#define PAD21_PE_I_MSK 0xfffffffd
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#define PAD21_PE_SFT 1
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#define PAD21_PE_HI 1
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#define PAD21_PE_SZ 1
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#define PAD21_DS_MSK 0x00000004
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#define PAD21_DS_I_MSK 0xfffffffb
|
#define PAD21_DS_SFT 2
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#define PAD21_DS_HI 2
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#define PAD21_DS_SZ 1
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#define PAD21_IE_MSK 0x00000008
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#define PAD21_IE_I_MSK 0xfffffff7
|
#define PAD21_IE_SFT 3
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#define PAD21_IE_HI 3
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#define PAD21_IE_SZ 1
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#define PAD21_SEL_I_MSK 0x00000070
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#define PAD21_SEL_I_I_MSK 0xffffff8f
|
#define PAD21_SEL_I_SFT 4
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#define PAD21_SEL_I_HI 6
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#define PAD21_SEL_I_SZ 3
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#define PAD21_OD_MSK 0x00000100
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#define PAD21_OD_I_MSK 0xfffffeff
|
#define PAD21_OD_SFT 8
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#define PAD21_OD_HI 8
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#define PAD21_OD_SZ 1
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#define PAD21_SEL_O_MSK 0x00003000
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#define PAD21_SEL_O_I_MSK 0xffffcfff
|
#define PAD21_SEL_O_SFT 12
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#define PAD21_SEL_O_HI 13
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#define PAD21_SEL_O_SZ 2
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#define STRAP3_MSK 0x08000000
|
#define STRAP3_I_MSK 0xf7ffffff
|
#define STRAP3_SFT 27
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#define STRAP3_HI 27
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#define STRAP3_SZ 1
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#define GPIO_TEST_2_ID_MSK 0x10000000
|
#define GPIO_TEST_2_ID_I_MSK 0xefffffff
|
#define GPIO_TEST_2_ID_SFT 28
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#define GPIO_TEST_2_ID_HI 28
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#define GPIO_TEST_2_ID_SZ 1
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#define PAD22_OE_MSK 0x00000001
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#define PAD22_OE_I_MSK 0xfffffffe
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#define PAD22_OE_SFT 0
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#define PAD22_OE_HI 0
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#define PAD22_OE_SZ 1
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#define PAD22_PE_MSK 0x00000002
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#define PAD22_PE_I_MSK 0xfffffffd
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#define PAD22_PE_SFT 1
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#define PAD22_PE_HI 1
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#define PAD22_PE_SZ 1
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#define PAD22_DS_MSK 0x00000004
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#define PAD22_DS_I_MSK 0xfffffffb
|
#define PAD22_DS_SFT 2
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#define PAD22_DS_HI 2
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#define PAD22_DS_SZ 1
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#define PAD22_IE_MSK 0x00000008
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#define PAD22_IE_I_MSK 0xfffffff7
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#define PAD22_IE_SFT 3
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#define PAD22_IE_HI 3
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#define PAD22_IE_SZ 1
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#define PAD22_SEL_I_MSK 0x00000070
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#define PAD22_SEL_I_I_MSK 0xffffff8f
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#define PAD22_SEL_I_SFT 4
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#define PAD22_SEL_I_HI 6
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#define PAD22_SEL_I_SZ 3
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#define PAD22_OD_MSK 0x00000100
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#define PAD22_OD_I_MSK 0xfffffeff
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#define PAD22_OD_SFT 8
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#define PAD22_OD_HI 8
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#define PAD22_OD_SZ 1
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#define PAD22_SEL_O_MSK 0x00007000
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#define PAD22_SEL_O_I_MSK 0xffff8fff
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#define PAD22_SEL_O_SFT 12
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#define PAD22_SEL_O_HI 14
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#define PAD22_SEL_O_SZ 3
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#define PAD22_SEL_OE_MSK 0x00100000
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#define PAD22_SEL_OE_I_MSK 0xffefffff
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#define PAD22_SEL_OE_SFT 20
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#define PAD22_SEL_OE_HI 20
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#define PAD22_SEL_OE_SZ 1
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#define GPIO_TEST_3_ID_MSK 0x10000000
|
#define GPIO_TEST_3_ID_I_MSK 0xefffffff
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#define GPIO_TEST_3_ID_SFT 28
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#define GPIO_TEST_3_ID_HI 28
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#define GPIO_TEST_3_ID_SZ 1
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#define PAD24_OE_MSK 0x00000001
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#define PAD24_OE_I_MSK 0xfffffffe
|
#define PAD24_OE_SFT 0
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#define PAD24_OE_HI 0
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#define PAD24_OE_SZ 1
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#define PAD24_PE_MSK 0x00000002
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#define PAD24_PE_I_MSK 0xfffffffd
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#define PAD24_PE_SFT 1
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#define PAD24_PE_HI 1
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#define PAD24_PE_SZ 1
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#define PAD24_DS_MSK 0x00000004
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#define PAD24_DS_I_MSK 0xfffffffb
|
#define PAD24_DS_SFT 2
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#define PAD24_DS_HI 2
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#define PAD24_DS_SZ 1
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#define PAD24_IE_MSK 0x00000008
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#define PAD24_IE_I_MSK 0xfffffff7
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#define PAD24_IE_SFT 3
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#define PAD24_IE_HI 3
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#define PAD24_IE_SZ 1
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#define PAD24_SEL_I_MSK 0x00000030
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#define PAD24_SEL_I_I_MSK 0xffffffcf
|
#define PAD24_SEL_I_SFT 4
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#define PAD24_SEL_I_HI 5
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#define PAD24_SEL_I_SZ 2
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#define PAD24_OD_MSK 0x00000100
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#define PAD24_OD_I_MSK 0xfffffeff
|
#define PAD24_OD_SFT 8
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#define PAD24_OD_HI 8
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#define PAD24_OD_SZ 1
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#define PAD24_SEL_O_MSK 0x00007000
|
#define PAD24_SEL_O_I_MSK 0xffff8fff
|
#define PAD24_SEL_O_SFT 12
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#define PAD24_SEL_O_HI 14
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#define PAD24_SEL_O_SZ 3
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#define GPIO_TEST_4_ID_MSK 0x10000000
|
#define GPIO_TEST_4_ID_I_MSK 0xefffffff
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#define GPIO_TEST_4_ID_SFT 28
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#define GPIO_TEST_4_ID_HI 28
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#define GPIO_TEST_4_ID_SZ 1
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#define PAD25_OE_MSK 0x00000001
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#define PAD25_OE_I_MSK 0xfffffffe
|
#define PAD25_OE_SFT 0
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#define PAD25_OE_HI 0
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#define PAD25_OE_SZ 1
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#define PAD25_PE_MSK 0x00000002
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#define PAD25_PE_I_MSK 0xfffffffd
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#define PAD25_PE_SFT 1
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#define PAD25_PE_HI 1
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#define PAD25_PE_SZ 1
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#define PAD25_DS_MSK 0x00000004
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#define PAD25_DS_I_MSK 0xfffffffb
|
#define PAD25_DS_SFT 2
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#define PAD25_DS_HI 2
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#define PAD25_DS_SZ 1
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#define PAD25_IE_MSK 0x00000008
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#define PAD25_IE_I_MSK 0xfffffff7
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#define PAD25_IE_SFT 3
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#define PAD25_IE_HI 3
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#define PAD25_IE_SZ 1
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#define PAD25_SEL_I_MSK 0x00000070
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#define PAD25_SEL_I_I_MSK 0xffffff8f
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#define PAD25_SEL_I_SFT 4
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#define PAD25_SEL_I_HI 6
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#define PAD25_SEL_I_SZ 3
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#define PAD25_OD_MSK 0x00000100
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#define PAD25_OD_I_MSK 0xfffffeff
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#define PAD25_OD_SFT 8
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#define PAD25_OD_HI 8
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#define PAD25_OD_SZ 1
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#define PAD25_SEL_O_MSK 0x00007000
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#define PAD25_SEL_O_I_MSK 0xffff8fff
|
#define PAD25_SEL_O_SFT 12
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#define PAD25_SEL_O_HI 14
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#define PAD25_SEL_O_SZ 3
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#define PAD25_SEL_OE_MSK 0x00100000
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#define PAD25_SEL_OE_I_MSK 0xffefffff
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#define PAD25_SEL_OE_SFT 20
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#define PAD25_SEL_OE_HI 20
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#define PAD25_SEL_OE_SZ 1
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#define STRAP1_MSK 0x08000000
|
#define STRAP1_I_MSK 0xf7ffffff
|
#define STRAP1_SFT 27
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#define STRAP1_HI 27
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#define STRAP1_SZ 1
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#define GPIO_1_ID_MSK 0x10000000
|
#define GPIO_1_ID_I_MSK 0xefffffff
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#define GPIO_1_ID_SFT 28
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#define GPIO_1_ID_HI 28
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#define GPIO_1_ID_SZ 1
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#define PAD27_OE_MSK 0x00000001
|
#define PAD27_OE_I_MSK 0xfffffffe
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#define PAD27_OE_SFT 0
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#define PAD27_OE_HI 0
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#define PAD27_OE_SZ 1
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#define PAD27_PE_MSK 0x00000002
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#define PAD27_PE_I_MSK 0xfffffffd
|
#define PAD27_PE_SFT 1
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#define PAD27_PE_HI 1
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#define PAD27_PE_SZ 1
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#define PAD27_DS_MSK 0x00000004
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#define PAD27_DS_I_MSK 0xfffffffb
|
#define PAD27_DS_SFT 2
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#define PAD27_DS_HI 2
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#define PAD27_DS_SZ 1
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#define PAD27_IE_MSK 0x00000008
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#define PAD27_IE_I_MSK 0xfffffff7
|
#define PAD27_IE_SFT 3
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#define PAD27_IE_HI 3
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#define PAD27_IE_SZ 1
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#define PAD27_SEL_I_MSK 0x00000070
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#define PAD27_SEL_I_I_MSK 0xffffff8f
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#define PAD27_SEL_I_SFT 4
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#define PAD27_SEL_I_HI 6
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#define PAD27_SEL_I_SZ 3
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#define PAD27_OD_MSK 0x00000100
|
#define PAD27_OD_I_MSK 0xfffffeff
|
#define PAD27_OD_SFT 8
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#define PAD27_OD_HI 8
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#define PAD27_OD_SZ 1
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#define PAD27_SEL_O_MSK 0x00007000
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#define PAD27_SEL_O_I_MSK 0xffff8fff
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#define PAD27_SEL_O_SFT 12
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#define PAD27_SEL_O_HI 14
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#define PAD27_SEL_O_SZ 3
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#define GPIO_2_ID_MSK 0x10000000
|
#define GPIO_2_ID_I_MSK 0xefffffff
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#define GPIO_2_ID_SFT 28
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#define GPIO_2_ID_HI 28
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#define GPIO_2_ID_SZ 1
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#define PAD28_OE_MSK 0x00000001
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#define PAD28_OE_I_MSK 0xfffffffe
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#define PAD28_OE_SFT 0
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#define PAD28_OE_HI 0
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#define PAD28_OE_SZ 1
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#define PAD28_PE_MSK 0x00000002
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#define PAD28_PE_I_MSK 0xfffffffd
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#define PAD28_PE_SFT 1
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#define PAD28_PE_HI 1
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#define PAD28_PE_SZ 1
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#define PAD28_DS_MSK 0x00000004
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#define PAD28_DS_I_MSK 0xfffffffb
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#define PAD28_DS_SFT 2
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#define PAD28_DS_HI 2
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#define PAD28_DS_SZ 1
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#define PAD28_IE_MSK 0x00000008
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#define PAD28_IE_I_MSK 0xfffffff7
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#define PAD28_IE_SFT 3
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#define PAD28_IE_HI 3
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#define PAD28_IE_SZ 1
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#define PAD28_SEL_I_MSK 0x00000070
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#define PAD28_SEL_I_I_MSK 0xffffff8f
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#define PAD28_SEL_I_SFT 4
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#define PAD28_SEL_I_HI 6
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#define PAD28_SEL_I_SZ 3
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#define PAD28_OD_MSK 0x00000100
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#define PAD28_OD_I_MSK 0xfffffeff
|
#define PAD28_OD_SFT 8
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#define PAD28_OD_HI 8
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#define PAD28_OD_SZ 1
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#define PAD28_SEL_O_MSK 0x0000f000
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#define PAD28_SEL_O_I_MSK 0xffff0fff
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#define PAD28_SEL_O_SFT 12
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#define PAD28_SEL_O_HI 15
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#define PAD28_SEL_O_SZ 4
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#define PAD28_SEL_OE_MSK 0x00100000
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#define PAD28_SEL_OE_I_MSK 0xffefffff
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#define PAD28_SEL_OE_SFT 20
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#define PAD28_SEL_OE_HI 20
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#define PAD28_SEL_OE_SZ 1
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#define GPIO_3_ID_MSK 0x10000000
|
#define GPIO_3_ID_I_MSK 0xefffffff
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#define GPIO_3_ID_SFT 28
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#define GPIO_3_ID_HI 28
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#define GPIO_3_ID_SZ 1
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#define PAD29_OE_MSK 0x00000001
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#define PAD29_OE_I_MSK 0xfffffffe
|
#define PAD29_OE_SFT 0
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#define PAD29_OE_HI 0
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#define PAD29_OE_SZ 1
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#define PAD29_PE_MSK 0x00000002
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#define PAD29_PE_I_MSK 0xfffffffd
|
#define PAD29_PE_SFT 1
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#define PAD29_PE_HI 1
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#define PAD29_PE_SZ 1
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#define PAD29_DS_MSK 0x00000004
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#define PAD29_DS_I_MSK 0xfffffffb
|
#define PAD29_DS_SFT 2
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#define PAD29_DS_HI 2
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#define PAD29_DS_SZ 1
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#define PAD29_IE_MSK 0x00000008
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#define PAD29_IE_I_MSK 0xfffffff7
|
#define PAD29_IE_SFT 3
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#define PAD29_IE_HI 3
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#define PAD29_IE_SZ 1
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#define PAD29_SEL_I_MSK 0x00000070
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#define PAD29_SEL_I_I_MSK 0xffffff8f
|
#define PAD29_SEL_I_SFT 4
|
#define PAD29_SEL_I_HI 6
|
#define PAD29_SEL_I_SZ 3
|
#define PAD29_OD_MSK 0x00000100
|
#define PAD29_OD_I_MSK 0xfffffeff
|
#define PAD29_OD_SFT 8
|
#define PAD29_OD_HI 8
|
#define PAD29_OD_SZ 1
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#define PAD29_SEL_O_MSK 0x00007000
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#define PAD29_SEL_O_I_MSK 0xffff8fff
|
#define PAD29_SEL_O_SFT 12
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#define PAD29_SEL_O_HI 14
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#define PAD29_SEL_O_SZ 3
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#define GPIO_TEST_5_ID_MSK 0x10000000
|
#define GPIO_TEST_5_ID_I_MSK 0xefffffff
|
#define GPIO_TEST_5_ID_SFT 28
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#define GPIO_TEST_5_ID_HI 28
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#define GPIO_TEST_5_ID_SZ 1
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#define PAD30_OE_MSK 0x00000001
|
#define PAD30_OE_I_MSK 0xfffffffe
|
#define PAD30_OE_SFT 0
|
#define PAD30_OE_HI 0
|
#define PAD30_OE_SZ 1
|
#define PAD30_PE_MSK 0x00000002
|
#define PAD30_PE_I_MSK 0xfffffffd
|
#define PAD30_PE_SFT 1
|
#define PAD30_PE_HI 1
|
#define PAD30_PE_SZ 1
|
#define PAD30_DS_MSK 0x00000004
|
#define PAD30_DS_I_MSK 0xfffffffb
|
#define PAD30_DS_SFT 2
|
#define PAD30_DS_HI 2
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#define PAD30_DS_SZ 1
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#define PAD30_IE_MSK 0x00000008
|
#define PAD30_IE_I_MSK 0xfffffff7
|
#define PAD30_IE_SFT 3
|
#define PAD30_IE_HI 3
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#define PAD30_IE_SZ 1
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#define PAD30_SEL_I_MSK 0x00000030
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#define PAD30_SEL_I_I_MSK 0xffffffcf
|
#define PAD30_SEL_I_SFT 4
|
#define PAD30_SEL_I_HI 5
|
#define PAD30_SEL_I_SZ 2
|
#define PAD30_OD_MSK 0x00000100
|
#define PAD30_OD_I_MSK 0xfffffeff
|
#define PAD30_OD_SFT 8
|
#define PAD30_OD_HI 8
|
#define PAD30_OD_SZ 1
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#define PAD30_SEL_O_MSK 0x00003000
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#define PAD30_SEL_O_I_MSK 0xffffcfff
|
#define PAD30_SEL_O_SFT 12
|
#define PAD30_SEL_O_HI 13
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#define PAD30_SEL_O_SZ 2
|
#define TEST_6_ID_MSK 0x10000000
|
#define TEST_6_ID_I_MSK 0xefffffff
|
#define TEST_6_ID_SFT 28
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#define TEST_6_ID_HI 28
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#define TEST_6_ID_SZ 1
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#define PAD31_OE_MSK 0x00000001
|
#define PAD31_OE_I_MSK 0xfffffffe
|
#define PAD31_OE_SFT 0
|
#define PAD31_OE_HI 0
|
#define PAD31_OE_SZ 1
|
#define PAD31_PE_MSK 0x00000002
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#define PAD31_PE_I_MSK 0xfffffffd
|
#define PAD31_PE_SFT 1
|
#define PAD31_PE_HI 1
|
#define PAD31_PE_SZ 1
|
#define PAD31_DS_MSK 0x00000004
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#define PAD31_DS_I_MSK 0xfffffffb
|
#define PAD31_DS_SFT 2
|
#define PAD31_DS_HI 2
|
#define PAD31_DS_SZ 1
|
#define PAD31_IE_MSK 0x00000008
|
#define PAD31_IE_I_MSK 0xfffffff7
|
#define PAD31_IE_SFT 3
|
#define PAD31_IE_HI 3
|
#define PAD31_IE_SZ 1
|
#define PAD31_SEL_I_MSK 0x00000030
|
#define PAD31_SEL_I_I_MSK 0xffffffcf
|
#define PAD31_SEL_I_SFT 4
|
#define PAD31_SEL_I_HI 5
|
#define PAD31_SEL_I_SZ 2
|
#define PAD31_OD_MSK 0x00000100
|
#define PAD31_OD_I_MSK 0xfffffeff
|
#define PAD31_OD_SFT 8
|
#define PAD31_OD_HI 8
|
#define PAD31_OD_SZ 1
|
#define PAD31_SEL_O_MSK 0x00003000
|
#define PAD31_SEL_O_I_MSK 0xffffcfff
|
#define PAD31_SEL_O_SFT 12
|
#define PAD31_SEL_O_HI 13
|
#define PAD31_SEL_O_SZ 2
|
#define TEST_7_ID_MSK 0x10000000
|
#define TEST_7_ID_I_MSK 0xefffffff
|
#define TEST_7_ID_SFT 28
|
#define TEST_7_ID_HI 28
|
#define TEST_7_ID_SZ 1
|
#define PAD32_OE_MSK 0x00000001
|
#define PAD32_OE_I_MSK 0xfffffffe
|
#define PAD32_OE_SFT 0
|
#define PAD32_OE_HI 0
|
#define PAD32_OE_SZ 1
|
#define PAD32_PE_MSK 0x00000002
|
#define PAD32_PE_I_MSK 0xfffffffd
|
#define PAD32_PE_SFT 1
|
#define PAD32_PE_HI 1
|
#define PAD32_PE_SZ 1
|
#define PAD32_DS_MSK 0x00000004
|
#define PAD32_DS_I_MSK 0xfffffffb
|
#define PAD32_DS_SFT 2
|
#define PAD32_DS_HI 2
|
#define PAD32_DS_SZ 1
|
#define PAD32_IE_MSK 0x00000008
|
#define PAD32_IE_I_MSK 0xfffffff7
|
#define PAD32_IE_SFT 3
|
#define PAD32_IE_HI 3
|
#define PAD32_IE_SZ 1
|
#define PAD32_SEL_I_MSK 0x00000030
|
#define PAD32_SEL_I_I_MSK 0xffffffcf
|
#define PAD32_SEL_I_SFT 4
|
#define PAD32_SEL_I_HI 5
|
#define PAD32_SEL_I_SZ 2
|
#define PAD32_OD_MSK 0x00000100
|
#define PAD32_OD_I_MSK 0xfffffeff
|
#define PAD32_OD_SFT 8
|
#define PAD32_OD_HI 8
|
#define PAD32_OD_SZ 1
|
#define PAD32_SEL_O_MSK 0x00003000
|
#define PAD32_SEL_O_I_MSK 0xffffcfff
|
#define PAD32_SEL_O_SFT 12
|
#define PAD32_SEL_O_HI 13
|
#define PAD32_SEL_O_SZ 2
|
#define TEST_8_ID_MSK 0x10000000
|
#define TEST_8_ID_I_MSK 0xefffffff
|
#define TEST_8_ID_SFT 28
|
#define TEST_8_ID_HI 28
|
#define TEST_8_ID_SZ 1
|
#define PAD33_OE_MSK 0x00000001
|
#define PAD33_OE_I_MSK 0xfffffffe
|
#define PAD33_OE_SFT 0
|
#define PAD33_OE_HI 0
|
#define PAD33_OE_SZ 1
|
#define PAD33_PE_MSK 0x00000002
|
#define PAD33_PE_I_MSK 0xfffffffd
|
#define PAD33_PE_SFT 1
|
#define PAD33_PE_HI 1
|
#define PAD33_PE_SZ 1
|
#define PAD33_DS_MSK 0x00000004
|
#define PAD33_DS_I_MSK 0xfffffffb
|
#define PAD33_DS_SFT 2
|
#define PAD33_DS_HI 2
|
#define PAD33_DS_SZ 1
|
#define PAD33_IE_MSK 0x00000008
|
#define PAD33_IE_I_MSK 0xfffffff7
|
#define PAD33_IE_SFT 3
|
#define PAD33_IE_HI 3
|
#define PAD33_IE_SZ 1
|
#define PAD33_SEL_I_MSK 0x00000030
|
#define PAD33_SEL_I_I_MSK 0xffffffcf
|
#define PAD33_SEL_I_SFT 4
|
#define PAD33_SEL_I_HI 5
|
#define PAD33_SEL_I_SZ 2
|
#define PAD33_OD_MSK 0x00000100
|
#define PAD33_OD_I_MSK 0xfffffeff
|
#define PAD33_OD_SFT 8
|
#define PAD33_OD_HI 8
|
#define PAD33_OD_SZ 1
|
#define PAD33_SEL_O_MSK 0x00003000
|
#define PAD33_SEL_O_I_MSK 0xffffcfff
|
#define PAD33_SEL_O_SFT 12
|
#define PAD33_SEL_O_HI 13
|
#define PAD33_SEL_O_SZ 2
|
#define TEST_9_ID_MSK 0x10000000
|
#define TEST_9_ID_I_MSK 0xefffffff
|
#define TEST_9_ID_SFT 28
|
#define TEST_9_ID_HI 28
|
#define TEST_9_ID_SZ 1
|
#define PAD34_OE_MSK 0x00000001
|
#define PAD34_OE_I_MSK 0xfffffffe
|
#define PAD34_OE_SFT 0
|
#define PAD34_OE_HI 0
|
#define PAD34_OE_SZ 1
|
#define PAD34_PE_MSK 0x00000002
|
#define PAD34_PE_I_MSK 0xfffffffd
|
#define PAD34_PE_SFT 1
|
#define PAD34_PE_HI 1
|
#define PAD34_PE_SZ 1
|
#define PAD34_DS_MSK 0x00000004
|
#define PAD34_DS_I_MSK 0xfffffffb
|
#define PAD34_DS_SFT 2
|
#define PAD34_DS_HI 2
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#define PAD34_DS_SZ 1
|
#define PAD34_IE_MSK 0x00000008
|
#define PAD34_IE_I_MSK 0xfffffff7
|
#define PAD34_IE_SFT 3
|
#define PAD34_IE_HI 3
|
#define PAD34_IE_SZ 1
|
#define PAD34_SEL_I_MSK 0x00000030
|
#define PAD34_SEL_I_I_MSK 0xffffffcf
|
#define PAD34_SEL_I_SFT 4
|
#define PAD34_SEL_I_HI 5
|
#define PAD34_SEL_I_SZ 2
|
#define PAD34_OD_MSK 0x00000100
|
#define PAD34_OD_I_MSK 0xfffffeff
|
#define PAD34_OD_SFT 8
|
#define PAD34_OD_HI 8
|
#define PAD34_OD_SZ 1
|
#define PAD34_SEL_O_MSK 0x00003000
|
#define PAD34_SEL_O_I_MSK 0xffffcfff
|
#define PAD34_SEL_O_SFT 12
|
#define PAD34_SEL_O_HI 13
|
#define PAD34_SEL_O_SZ 2
|
#define TEST_10_ID_MSK 0x10000000
|
#define TEST_10_ID_I_MSK 0xefffffff
|
#define TEST_10_ID_SFT 28
|
#define TEST_10_ID_HI 28
|
#define TEST_10_ID_SZ 1
|
#define PAD42_OE_MSK 0x00000001
|
#define PAD42_OE_I_MSK 0xfffffffe
|
#define PAD42_OE_SFT 0
|
#define PAD42_OE_HI 0
|
#define PAD42_OE_SZ 1
|
#define PAD42_PE_MSK 0x00000002
|
#define PAD42_PE_I_MSK 0xfffffffd
|
#define PAD42_PE_SFT 1
|
#define PAD42_PE_HI 1
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#define PAD42_PE_SZ 1
|
#define PAD42_DS_MSK 0x00000004
|
#define PAD42_DS_I_MSK 0xfffffffb
|
#define PAD42_DS_SFT 2
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#define PAD42_DS_HI 2
|
#define PAD42_DS_SZ 1
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#define PAD42_IE_MSK 0x00000008
|
#define PAD42_IE_I_MSK 0xfffffff7
|
#define PAD42_IE_SFT 3
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#define PAD42_IE_HI 3
|
#define PAD42_IE_SZ 1
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#define PAD42_SEL_I_MSK 0x00000030
|
#define PAD42_SEL_I_I_MSK 0xffffffcf
|
#define PAD42_SEL_I_SFT 4
|
#define PAD42_SEL_I_HI 5
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#define PAD42_SEL_I_SZ 2
|
#define PAD42_OD_MSK 0x00000100
|
#define PAD42_OD_I_MSK 0xfffffeff
|
#define PAD42_OD_SFT 8
|
#define PAD42_OD_HI 8
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#define PAD42_OD_SZ 1
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#define PAD42_SEL_O_MSK 0x00001000
|
#define PAD42_SEL_O_I_MSK 0xffffefff
|
#define PAD42_SEL_O_SFT 12
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#define PAD42_SEL_O_HI 12
|
#define PAD42_SEL_O_SZ 1
|
#define TEST_11_ID_MSK 0x10000000
|
#define TEST_11_ID_I_MSK 0xefffffff
|
#define TEST_11_ID_SFT 28
|
#define TEST_11_ID_HI 28
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#define TEST_11_ID_SZ 1
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#define PAD43_OE_MSK 0x00000001
|
#define PAD43_OE_I_MSK 0xfffffffe
|
#define PAD43_OE_SFT 0
|
#define PAD43_OE_HI 0
|
#define PAD43_OE_SZ 1
|
#define PAD43_PE_MSK 0x00000002
|
#define PAD43_PE_I_MSK 0xfffffffd
|
#define PAD43_PE_SFT 1
|
#define PAD43_PE_HI 1
|
#define PAD43_PE_SZ 1
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#define PAD43_DS_MSK 0x00000004
|
#define PAD43_DS_I_MSK 0xfffffffb
|
#define PAD43_DS_SFT 2
|
#define PAD43_DS_HI 2
|
#define PAD43_DS_SZ 1
|
#define PAD43_IE_MSK 0x00000008
|
#define PAD43_IE_I_MSK 0xfffffff7
|
#define PAD43_IE_SFT 3
|
#define PAD43_IE_HI 3
|
#define PAD43_IE_SZ 1
|
#define PAD43_SEL_I_MSK 0x00000030
|
#define PAD43_SEL_I_I_MSK 0xffffffcf
|
#define PAD43_SEL_I_SFT 4
|
#define PAD43_SEL_I_HI 5
|
#define PAD43_SEL_I_SZ 2
|
#define PAD43_OD_MSK 0x00000100
|
#define PAD43_OD_I_MSK 0xfffffeff
|
#define PAD43_OD_SFT 8
|
#define PAD43_OD_HI 8
|
#define PAD43_OD_SZ 1
|
#define PAD43_SEL_O_MSK 0x00001000
|
#define PAD43_SEL_O_I_MSK 0xffffefff
|
#define PAD43_SEL_O_SFT 12
|
#define PAD43_SEL_O_HI 12
|
#define PAD43_SEL_O_SZ 1
|
#define TEST_12_ID_MSK 0x10000000
|
#define TEST_12_ID_I_MSK 0xefffffff
|
#define TEST_12_ID_SFT 28
|
#define TEST_12_ID_HI 28
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#define TEST_12_ID_SZ 1
|
#define PAD44_OE_MSK 0x00000001
|
#define PAD44_OE_I_MSK 0xfffffffe
|
#define PAD44_OE_SFT 0
|
#define PAD44_OE_HI 0
|
#define PAD44_OE_SZ 1
|
#define PAD44_PE_MSK 0x00000002
|
#define PAD44_PE_I_MSK 0xfffffffd
|
#define PAD44_PE_SFT 1
|
#define PAD44_PE_HI 1
|
#define PAD44_PE_SZ 1
|
#define PAD44_DS_MSK 0x00000004
|
#define PAD44_DS_I_MSK 0xfffffffb
|
#define PAD44_DS_SFT 2
|
#define PAD44_DS_HI 2
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#define PAD44_DS_SZ 1
|
#define PAD44_IE_MSK 0x00000008
|
#define PAD44_IE_I_MSK 0xfffffff7
|
#define PAD44_IE_SFT 3
|
#define PAD44_IE_HI 3
|
#define PAD44_IE_SZ 1
|
#define PAD44_SEL_I_MSK 0x00000030
|
#define PAD44_SEL_I_I_MSK 0xffffffcf
|
#define PAD44_SEL_I_SFT 4
|
#define PAD44_SEL_I_HI 5
|
#define PAD44_SEL_I_SZ 2
|
#define PAD44_OD_MSK 0x00000100
|
#define PAD44_OD_I_MSK 0xfffffeff
|
#define PAD44_OD_SFT 8
|
#define PAD44_OD_HI 8
|
#define PAD44_OD_SZ 1
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#define PAD44_SEL_O_MSK 0x00003000
|
#define PAD44_SEL_O_I_MSK 0xffffcfff
|
#define PAD44_SEL_O_SFT 12
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#define PAD44_SEL_O_HI 13
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#define PAD44_SEL_O_SZ 2
|
#define TEST_13_ID_MSK 0x10000000
|
#define TEST_13_ID_I_MSK 0xefffffff
|
#define TEST_13_ID_SFT 28
|
#define TEST_13_ID_HI 28
|
#define TEST_13_ID_SZ 1
|
#define PAD45_OE_MSK 0x00000001
|
#define PAD45_OE_I_MSK 0xfffffffe
|
#define PAD45_OE_SFT 0
|
#define PAD45_OE_HI 0
|
#define PAD45_OE_SZ 1
|
#define PAD45_PE_MSK 0x00000002
|
#define PAD45_PE_I_MSK 0xfffffffd
|
#define PAD45_PE_SFT 1
|
#define PAD45_PE_HI 1
|
#define PAD45_PE_SZ 1
|
#define PAD45_DS_MSK 0x00000004
|
#define PAD45_DS_I_MSK 0xfffffffb
|
#define PAD45_DS_SFT 2
|
#define PAD45_DS_HI 2
|
#define PAD45_DS_SZ 1
|
#define PAD45_IE_MSK 0x00000008
|
#define PAD45_IE_I_MSK 0xfffffff7
|
#define PAD45_IE_SFT 3
|
#define PAD45_IE_HI 3
|
#define PAD45_IE_SZ 1
|
#define PAD45_SEL_I_MSK 0x00000030
|
#define PAD45_SEL_I_I_MSK 0xffffffcf
|
#define PAD45_SEL_I_SFT 4
|
#define PAD45_SEL_I_HI 5
|
#define PAD45_SEL_I_SZ 2
|
#define PAD45_OD_MSK 0x00000100
|
#define PAD45_OD_I_MSK 0xfffffeff
|
#define PAD45_OD_SFT 8
|
#define PAD45_OD_HI 8
|
#define PAD45_OD_SZ 1
|
#define PAD45_SEL_O_MSK 0x00003000
|
#define PAD45_SEL_O_I_MSK 0xffffcfff
|
#define PAD45_SEL_O_SFT 12
|
#define PAD45_SEL_O_HI 13
|
#define PAD45_SEL_O_SZ 2
|
#define TEST_14_ID_MSK 0x10000000
|
#define TEST_14_ID_I_MSK 0xefffffff
|
#define TEST_14_ID_SFT 28
|
#define TEST_14_ID_HI 28
|
#define TEST_14_ID_SZ 1
|
#define PAD46_OE_MSK 0x00000001
|
#define PAD46_OE_I_MSK 0xfffffffe
|
#define PAD46_OE_SFT 0
|
#define PAD46_OE_HI 0
|
#define PAD46_OE_SZ 1
|
#define PAD46_PE_MSK 0x00000002
|
#define PAD46_PE_I_MSK 0xfffffffd
|
#define PAD46_PE_SFT 1
|
#define PAD46_PE_HI 1
|
#define PAD46_PE_SZ 1
|
#define PAD46_DS_MSK 0x00000004
|
#define PAD46_DS_I_MSK 0xfffffffb
|
#define PAD46_DS_SFT 2
|
#define PAD46_DS_HI 2
|
#define PAD46_DS_SZ 1
|
#define PAD46_IE_MSK 0x00000008
|
#define PAD46_IE_I_MSK 0xfffffff7
|
#define PAD46_IE_SFT 3
|
#define PAD46_IE_HI 3
|
#define PAD46_IE_SZ 1
|
#define PAD46_SEL_I_MSK 0x00000030
|
#define PAD46_SEL_I_I_MSK 0xffffffcf
|
#define PAD46_SEL_I_SFT 4
|
#define PAD46_SEL_I_HI 5
|
#define PAD46_SEL_I_SZ 2
|
#define PAD46_OD_MSK 0x00000100
|
#define PAD46_OD_I_MSK 0xfffffeff
|
#define PAD46_OD_SFT 8
|
#define PAD46_OD_HI 8
|
#define PAD46_OD_SZ 1
|
#define PAD46_SEL_O_MSK 0x00003000
|
#define PAD46_SEL_O_I_MSK 0xffffcfff
|
#define PAD46_SEL_O_SFT 12
|
#define PAD46_SEL_O_HI 13
|
#define PAD46_SEL_O_SZ 2
|
#define TEST_15_ID_MSK 0x10000000
|
#define TEST_15_ID_I_MSK 0xefffffff
|
#define TEST_15_ID_SFT 28
|
#define TEST_15_ID_HI 28
|
#define TEST_15_ID_SZ 1
|
#define PAD47_OE_MSK 0x00000001
|
#define PAD47_OE_I_MSK 0xfffffffe
|
#define PAD47_OE_SFT 0
|
#define PAD47_OE_HI 0
|
#define PAD47_OE_SZ 1
|
#define PAD47_PE_MSK 0x00000002
|
#define PAD47_PE_I_MSK 0xfffffffd
|
#define PAD47_PE_SFT 1
|
#define PAD47_PE_HI 1
|
#define PAD47_PE_SZ 1
|
#define PAD47_DS_MSK 0x00000004
|
#define PAD47_DS_I_MSK 0xfffffffb
|
#define PAD47_DS_SFT 2
|
#define PAD47_DS_HI 2
|
#define PAD47_DS_SZ 1
|
#define PAD47_SEL_I_MSK 0x00000030
|
#define PAD47_SEL_I_I_MSK 0xffffffcf
|
#define PAD47_SEL_I_SFT 4
|
#define PAD47_SEL_I_HI 5
|
#define PAD47_SEL_I_SZ 2
|
#define PAD47_OD_MSK 0x00000100
|
#define PAD47_OD_I_MSK 0xfffffeff
|
#define PAD47_OD_SFT 8
|
#define PAD47_OD_HI 8
|
#define PAD47_OD_SZ 1
|
#define PAD47_SEL_O_MSK 0x00003000
|
#define PAD47_SEL_O_I_MSK 0xffffcfff
|
#define PAD47_SEL_O_SFT 12
|
#define PAD47_SEL_O_HI 13
|
#define PAD47_SEL_O_SZ 2
|
#define PAD47_SEL_OE_MSK 0x00100000
|
#define PAD47_SEL_OE_I_MSK 0xffefffff
|
#define PAD47_SEL_OE_SFT 20
|
#define PAD47_SEL_OE_HI 20
|
#define PAD47_SEL_OE_SZ 1
|
#define GPIO_9_ID_MSK 0x10000000
|
#define GPIO_9_ID_I_MSK 0xefffffff
|
#define GPIO_9_ID_SFT 28
|
#define GPIO_9_ID_HI 28
|
#define GPIO_9_ID_SZ 1
|
#define PAD48_OE_MSK 0x00000001
|
#define PAD48_OE_I_MSK 0xfffffffe
|
#define PAD48_OE_SFT 0
|
#define PAD48_OE_HI 0
|
#define PAD48_OE_SZ 1
|
#define PAD48_PE_MSK 0x00000002
|
#define PAD48_PE_I_MSK 0xfffffffd
|
#define PAD48_PE_SFT 1
|
#define PAD48_PE_HI 1
|
#define PAD48_PE_SZ 1
|
#define PAD48_DS_MSK 0x00000004
|
#define PAD48_DS_I_MSK 0xfffffffb
|
#define PAD48_DS_SFT 2
|
#define PAD48_DS_HI 2
|
#define PAD48_DS_SZ 1
|
#define PAD48_IE_MSK 0x00000008
|
#define PAD48_IE_I_MSK 0xfffffff7
|
#define PAD48_IE_SFT 3
|
#define PAD48_IE_HI 3
|
#define PAD48_IE_SZ 1
|
#define PAD48_SEL_I_MSK 0x00000070
|
#define PAD48_SEL_I_I_MSK 0xffffff8f
|
#define PAD48_SEL_I_SFT 4
|
#define PAD48_SEL_I_HI 6
|
#define PAD48_SEL_I_SZ 3
|
#define PAD48_OD_MSK 0x00000100
|
#define PAD48_OD_I_MSK 0xfffffeff
|
#define PAD48_OD_SFT 8
|
#define PAD48_OD_HI 8
|
#define PAD48_OD_SZ 1
|
#define PAD48_PE_SEL_MSK 0x00000800
|
#define PAD48_PE_SEL_I_MSK 0xfffff7ff
|
#define PAD48_PE_SEL_SFT 11
|
#define PAD48_PE_SEL_HI 11
|
#define PAD48_PE_SEL_SZ 1
|
#define PAD48_SEL_O_MSK 0x00003000
|
#define PAD48_SEL_O_I_MSK 0xffffcfff
|
#define PAD48_SEL_O_SFT 12
|
#define PAD48_SEL_O_HI 13
|
#define PAD48_SEL_O_SZ 2
|
#define PAD48_SEL_OE_MSK 0x00100000
|
#define PAD48_SEL_OE_I_MSK 0xffefffff
|
#define PAD48_SEL_OE_SFT 20
|
#define PAD48_SEL_OE_HI 20
|
#define PAD48_SEL_OE_SZ 1
|
#define GPIO_10_ID_MSK 0x10000000
|
#define GPIO_10_ID_I_MSK 0xefffffff
|
#define GPIO_10_ID_SFT 28
|
#define GPIO_10_ID_HI 28
|
#define GPIO_10_ID_SZ 1
|
#define PAD49_OE_MSK 0x00000001
|
#define PAD49_OE_I_MSK 0xfffffffe
|
#define PAD49_OE_SFT 0
|
#define PAD49_OE_HI 0
|
#define PAD49_OE_SZ 1
|
#define PAD49_PE_MSK 0x00000002
|
#define PAD49_PE_I_MSK 0xfffffffd
|
#define PAD49_PE_SFT 1
|
#define PAD49_PE_HI 1
|
#define PAD49_PE_SZ 1
|
#define PAD49_DS_MSK 0x00000004
|
#define PAD49_DS_I_MSK 0xfffffffb
|
#define PAD49_DS_SFT 2
|
#define PAD49_DS_HI 2
|
#define PAD49_DS_SZ 1
|
#define PAD49_IE_MSK 0x00000008
|
#define PAD49_IE_I_MSK 0xfffffff7
|
#define PAD49_IE_SFT 3
|
#define PAD49_IE_HI 3
|
#define PAD49_IE_SZ 1
|
#define PAD49_SEL_I_MSK 0x00000070
|
#define PAD49_SEL_I_I_MSK 0xffffff8f
|
#define PAD49_SEL_I_SFT 4
|
#define PAD49_SEL_I_HI 6
|
#define PAD49_SEL_I_SZ 3
|
#define PAD49_OD_MSK 0x00000100
|
#define PAD49_OD_I_MSK 0xfffffeff
|
#define PAD49_OD_SFT 8
|
#define PAD49_OD_HI 8
|
#define PAD49_OD_SZ 1
|
#define PAD49_SEL_O_MSK 0x00003000
|
#define PAD49_SEL_O_I_MSK 0xffffcfff
|
#define PAD49_SEL_O_SFT 12
|
#define PAD49_SEL_O_HI 13
|
#define PAD49_SEL_O_SZ 2
|
#define PAD49_SEL_OE_MSK 0x00100000
|
#define PAD49_SEL_OE_I_MSK 0xffefffff
|
#define PAD49_SEL_OE_SFT 20
|
#define PAD49_SEL_OE_HI 20
|
#define PAD49_SEL_OE_SZ 1
|
#define GPIO_11_ID_MSK 0x10000000
|
#define GPIO_11_ID_I_MSK 0xefffffff
|
#define GPIO_11_ID_SFT 28
|
#define GPIO_11_ID_HI 28
|
#define GPIO_11_ID_SZ 1
|
#define PAD50_OE_MSK 0x00000001
|
#define PAD50_OE_I_MSK 0xfffffffe
|
#define PAD50_OE_SFT 0
|
#define PAD50_OE_HI 0
|
#define PAD50_OE_SZ 1
|
#define PAD50_PE_MSK 0x00000002
|
#define PAD50_PE_I_MSK 0xfffffffd
|
#define PAD50_PE_SFT 1
|
#define PAD50_PE_HI 1
|
#define PAD50_PE_SZ 1
|
#define PAD50_DS_MSK 0x00000004
|
#define PAD50_DS_I_MSK 0xfffffffb
|
#define PAD50_DS_SFT 2
|
#define PAD50_DS_HI 2
|
#define PAD50_DS_SZ 1
|
#define PAD50_IE_MSK 0x00000008
|
#define PAD50_IE_I_MSK 0xfffffff7
|
#define PAD50_IE_SFT 3
|
#define PAD50_IE_HI 3
|
#define PAD50_IE_SZ 1
|
#define PAD50_SEL_I_MSK 0x00000070
|
#define PAD50_SEL_I_I_MSK 0xffffff8f
|
#define PAD50_SEL_I_SFT 4
|
#define PAD50_SEL_I_HI 6
|
#define PAD50_SEL_I_SZ 3
|
#define PAD50_OD_MSK 0x00000100
|
#define PAD50_OD_I_MSK 0xfffffeff
|
#define PAD50_OD_SFT 8
|
#define PAD50_OD_HI 8
|
#define PAD50_OD_SZ 1
|
#define PAD50_SEL_O_MSK 0x00003000
|
#define PAD50_SEL_O_I_MSK 0xffffcfff
|
#define PAD50_SEL_O_SFT 12
|
#define PAD50_SEL_O_HI 13
|
#define PAD50_SEL_O_SZ 2
|
#define PAD50_SEL_OE_MSK 0x00100000
|
#define PAD50_SEL_OE_I_MSK 0xffefffff
|
#define PAD50_SEL_OE_SFT 20
|
#define PAD50_SEL_OE_HI 20
|
#define PAD50_SEL_OE_SZ 1
|
#define GPIO_12_ID_MSK 0x10000000
|
#define GPIO_12_ID_I_MSK 0xefffffff
|
#define GPIO_12_ID_SFT 28
|
#define GPIO_12_ID_HI 28
|
#define GPIO_12_ID_SZ 1
|
#define PAD51_OE_MSK 0x00000001
|
#define PAD51_OE_I_MSK 0xfffffffe
|
#define PAD51_OE_SFT 0
|
#define PAD51_OE_HI 0
|
#define PAD51_OE_SZ 1
|
#define PAD51_PE_MSK 0x00000002
|
#define PAD51_PE_I_MSK 0xfffffffd
|
#define PAD51_PE_SFT 1
|
#define PAD51_PE_HI 1
|
#define PAD51_PE_SZ 1
|
#define PAD51_DS_MSK 0x00000004
|
#define PAD51_DS_I_MSK 0xfffffffb
|
#define PAD51_DS_SFT 2
|
#define PAD51_DS_HI 2
|
#define PAD51_DS_SZ 1
|
#define PAD51_IE_MSK 0x00000008
|
#define PAD51_IE_I_MSK 0xfffffff7
|
#define PAD51_IE_SFT 3
|
#define PAD51_IE_HI 3
|
#define PAD51_IE_SZ 1
|
#define PAD51_SEL_I_MSK 0x00000030
|
#define PAD51_SEL_I_I_MSK 0xffffffcf
|
#define PAD51_SEL_I_SFT 4
|
#define PAD51_SEL_I_HI 5
|
#define PAD51_SEL_I_SZ 2
|
#define PAD51_OD_MSK 0x00000100
|
#define PAD51_OD_I_MSK 0xfffffeff
|
#define PAD51_OD_SFT 8
|
#define PAD51_OD_HI 8
|
#define PAD51_OD_SZ 1
|
#define PAD51_SEL_O_MSK 0x00001000
|
#define PAD51_SEL_O_I_MSK 0xffffefff
|
#define PAD51_SEL_O_SFT 12
|
#define PAD51_SEL_O_HI 12
|
#define PAD51_SEL_O_SZ 1
|
#define PAD51_SEL_OE_MSK 0x00100000
|
#define PAD51_SEL_OE_I_MSK 0xffefffff
|
#define PAD51_SEL_OE_SFT 20
|
#define PAD51_SEL_OE_HI 20
|
#define PAD51_SEL_OE_SZ 1
|
#define GPIO_13_ID_MSK 0x10000000
|
#define GPIO_13_ID_I_MSK 0xefffffff
|
#define GPIO_13_ID_SFT 28
|
#define GPIO_13_ID_HI 28
|
#define GPIO_13_ID_SZ 1
|
#define PAD52_OE_MSK 0x00000001
|
#define PAD52_OE_I_MSK 0xfffffffe
|
#define PAD52_OE_SFT 0
|
#define PAD52_OE_HI 0
|
#define PAD52_OE_SZ 1
|
#define PAD52_PE_MSK 0x00000002
|
#define PAD52_PE_I_MSK 0xfffffffd
|
#define PAD52_PE_SFT 1
|
#define PAD52_PE_HI 1
|
#define PAD52_PE_SZ 1
|
#define PAD52_DS_MSK 0x00000004
|
#define PAD52_DS_I_MSK 0xfffffffb
|
#define PAD52_DS_SFT 2
|
#define PAD52_DS_HI 2
|
#define PAD52_DS_SZ 1
|
#define PAD52_SEL_I_MSK 0x00000030
|
#define PAD52_SEL_I_I_MSK 0xffffffcf
|
#define PAD52_SEL_I_SFT 4
|
#define PAD52_SEL_I_HI 5
|
#define PAD52_SEL_I_SZ 2
|
#define PAD52_OD_MSK 0x00000100
|
#define PAD52_OD_I_MSK 0xfffffeff
|
#define PAD52_OD_SFT 8
|
#define PAD52_OD_HI 8
|
#define PAD52_OD_SZ 1
|
#define PAD52_SEL_O_MSK 0x00001000
|
#define PAD52_SEL_O_I_MSK 0xffffefff
|
#define PAD52_SEL_O_SFT 12
|
#define PAD52_SEL_O_HI 12
|
#define PAD52_SEL_O_SZ 1
|
#define PAD52_SEL_OE_MSK 0x00100000
|
#define PAD52_SEL_OE_I_MSK 0xffefffff
|
#define PAD52_SEL_OE_SFT 20
|
#define PAD52_SEL_OE_HI 20
|
#define PAD52_SEL_OE_SZ 1
|
#define GPIO_14_ID_MSK 0x10000000
|
#define GPIO_14_ID_I_MSK 0xefffffff
|
#define GPIO_14_ID_SFT 28
|
#define GPIO_14_ID_HI 28
|
#define GPIO_14_ID_SZ 1
|
#define PAD53_OE_MSK 0x00000001
|
#define PAD53_OE_I_MSK 0xfffffffe
|
#define PAD53_OE_SFT 0
|
#define PAD53_OE_HI 0
|
#define PAD53_OE_SZ 1
|
#define PAD53_PE_MSK 0x00000002
|
#define PAD53_PE_I_MSK 0xfffffffd
|
#define PAD53_PE_SFT 1
|
#define PAD53_PE_HI 1
|
#define PAD53_PE_SZ 1
|
#define PAD53_DS_MSK 0x00000004
|
#define PAD53_DS_I_MSK 0xfffffffb
|
#define PAD53_DS_SFT 2
|
#define PAD53_DS_HI 2
|
#define PAD53_DS_SZ 1
|
#define PAD53_IE_MSK 0x00000008
|
#define PAD53_IE_I_MSK 0xfffffff7
|
#define PAD53_IE_SFT 3
|
#define PAD53_IE_HI 3
|
#define PAD53_IE_SZ 1
|
#define PAD53_SEL_I_MSK 0x00000030
|
#define PAD53_SEL_I_I_MSK 0xffffffcf
|
#define PAD53_SEL_I_SFT 4
|
#define PAD53_SEL_I_HI 5
|
#define PAD53_SEL_I_SZ 2
|
#define PAD53_OD_MSK 0x00000100
|
#define PAD53_OD_I_MSK 0xfffffeff
|
#define PAD53_OD_SFT 8
|
#define PAD53_OD_HI 8
|
#define PAD53_OD_SZ 1
|
#define PAD53_SEL_O_MSK 0x00001000
|
#define PAD53_SEL_O_I_MSK 0xffffefff
|
#define PAD53_SEL_O_SFT 12
|
#define PAD53_SEL_O_HI 12
|
#define PAD53_SEL_O_SZ 1
|
#define JTAG_TMS_ID_MSK 0x10000000
|
#define JTAG_TMS_ID_I_MSK 0xefffffff
|
#define JTAG_TMS_ID_SFT 28
|
#define JTAG_TMS_ID_HI 28
|
#define JTAG_TMS_ID_SZ 1
|
#define PAD54_OE_MSK 0x00000001
|
#define PAD54_OE_I_MSK 0xfffffffe
|
#define PAD54_OE_SFT 0
|
#define PAD54_OE_HI 0
|
#define PAD54_OE_SZ 1
|
#define PAD54_PE_MSK 0x00000002
|
#define PAD54_PE_I_MSK 0xfffffffd
|
#define PAD54_PE_SFT 1
|
#define PAD54_PE_HI 1
|
#define PAD54_PE_SZ 1
|
#define PAD54_DS_MSK 0x00000004
|
#define PAD54_DS_I_MSK 0xfffffffb
|
#define PAD54_DS_SFT 2
|
#define PAD54_DS_HI 2
|
#define PAD54_DS_SZ 1
|
#define PAD54_OD_MSK 0x00000100
|
#define PAD54_OD_I_MSK 0xfffffeff
|
#define PAD54_OD_SFT 8
|
#define PAD54_OD_HI 8
|
#define PAD54_OD_SZ 1
|
#define PAD54_SEL_O_MSK 0x00003000
|
#define PAD54_SEL_O_I_MSK 0xffffcfff
|
#define PAD54_SEL_O_SFT 12
|
#define PAD54_SEL_O_HI 13
|
#define PAD54_SEL_O_SZ 2
|
#define JTAG_TCK_ID_MSK 0x10000000
|
#define JTAG_TCK_ID_I_MSK 0xefffffff
|
#define JTAG_TCK_ID_SFT 28
|
#define JTAG_TCK_ID_HI 28
|
#define JTAG_TCK_ID_SZ 1
|
#define PAD56_PE_MSK 0x00000002
|
#define PAD56_PE_I_MSK 0xfffffffd
|
#define PAD56_PE_SFT 1
|
#define PAD56_PE_HI 1
|
#define PAD56_PE_SZ 1
|
#define PAD56_DS_MSK 0x00000004
|
#define PAD56_DS_I_MSK 0xfffffffb
|
#define PAD56_DS_SFT 2
|
#define PAD56_DS_HI 2
|
#define PAD56_DS_SZ 1
|
#define PAD56_SEL_I_MSK 0x00000010
|
#define PAD56_SEL_I_I_MSK 0xffffffef
|
#define PAD56_SEL_I_SFT 4
|
#define PAD56_SEL_I_HI 4
|
#define PAD56_SEL_I_SZ 1
|
#define PAD56_OD_MSK 0x00000100
|
#define PAD56_OD_I_MSK 0xfffffeff
|
#define PAD56_OD_SFT 8
|
#define PAD56_OD_HI 8
|
#define PAD56_OD_SZ 1
|
#define JTAG_TDI_ID_MSK 0x10000000
|
#define JTAG_TDI_ID_I_MSK 0xefffffff
|
#define JTAG_TDI_ID_SFT 28
|
#define JTAG_TDI_ID_HI 28
|
#define JTAG_TDI_ID_SZ 1
|
#define PAD57_OE_MSK 0x00000001
|
#define PAD57_OE_I_MSK 0xfffffffe
|
#define PAD57_OE_SFT 0
|
#define PAD57_OE_HI 0
|
#define PAD57_OE_SZ 1
|
#define PAD57_PE_MSK 0x00000002
|
#define PAD57_PE_I_MSK 0xfffffffd
|
#define PAD57_PE_SFT 1
|
#define PAD57_PE_HI 1
|
#define PAD57_PE_SZ 1
|
#define PAD57_DS_MSK 0x00000004
|
#define PAD57_DS_I_MSK 0xfffffffb
|
#define PAD57_DS_SFT 2
|
#define PAD57_DS_HI 2
|
#define PAD57_DS_SZ 1
|
#define PAD57_IE_MSK 0x00000008
|
#define PAD57_IE_I_MSK 0xfffffff7
|
#define PAD57_IE_SFT 3
|
#define PAD57_IE_HI 3
|
#define PAD57_IE_SZ 1
|
#define PAD57_SEL_I_MSK 0x00000030
|
#define PAD57_SEL_I_I_MSK 0xffffffcf
|
#define PAD57_SEL_I_SFT 4
|
#define PAD57_SEL_I_HI 5
|
#define PAD57_SEL_I_SZ 2
|
#define PAD57_OD_MSK 0x00000100
|
#define PAD57_OD_I_MSK 0xfffffeff
|
#define PAD57_OD_SFT 8
|
#define PAD57_OD_HI 8
|
#define PAD57_OD_SZ 1
|
#define PAD57_SEL_O_MSK 0x00003000
|
#define PAD57_SEL_O_I_MSK 0xffffcfff
|
#define PAD57_SEL_O_SFT 12
|
#define PAD57_SEL_O_HI 13
|
#define PAD57_SEL_O_SZ 2
|
#define PAD57_SEL_OE_MSK 0x00100000
|
#define PAD57_SEL_OE_I_MSK 0xffefffff
|
#define PAD57_SEL_OE_SFT 20
|
#define PAD57_SEL_OE_HI 20
|
#define PAD57_SEL_OE_SZ 1
|
#define JTAG_TDO_ID_MSK 0x10000000
|
#define JTAG_TDO_ID_I_MSK 0xefffffff
|
#define JTAG_TDO_ID_SFT 28
|
#define JTAG_TDO_ID_HI 28
|
#define JTAG_TDO_ID_SZ 1
|
#define PAD58_OE_MSK 0x00000001
|
#define PAD58_OE_I_MSK 0xfffffffe
|
#define PAD58_OE_SFT 0
|
#define PAD58_OE_HI 0
|
#define PAD58_OE_SZ 1
|
#define PAD58_PE_MSK 0x00000002
|
#define PAD58_PE_I_MSK 0xfffffffd
|
#define PAD58_PE_SFT 1
|
#define PAD58_PE_HI 1
|
#define PAD58_PE_SZ 1
|
#define PAD58_DS_MSK 0x00000004
|
#define PAD58_DS_I_MSK 0xfffffffb
|
#define PAD58_DS_SFT 2
|
#define PAD58_DS_HI 2
|
#define PAD58_DS_SZ 1
|
#define PAD58_IE_MSK 0x00000008
|
#define PAD58_IE_I_MSK 0xfffffff7
|
#define PAD58_IE_SFT 3
|
#define PAD58_IE_HI 3
|
#define PAD58_IE_SZ 1
|
#define PAD58_SEL_I_MSK 0x00000030
|
#define PAD58_SEL_I_I_MSK 0xffffffcf
|
#define PAD58_SEL_I_SFT 4
|
#define PAD58_SEL_I_HI 5
|
#define PAD58_SEL_I_SZ 2
|
#define PAD58_OD_MSK 0x00000100
|
#define PAD58_OD_I_MSK 0xfffffeff
|
#define PAD58_OD_SFT 8
|
#define PAD58_OD_HI 8
|
#define PAD58_OD_SZ 1
|
#define PAD58_SEL_O_MSK 0x00001000
|
#define PAD58_SEL_O_I_MSK 0xffffefff
|
#define PAD58_SEL_O_SFT 12
|
#define PAD58_SEL_O_HI 12
|
#define PAD58_SEL_O_SZ 1
|
#define TEST_16_ID_MSK 0x10000000
|
#define TEST_16_ID_I_MSK 0xefffffff
|
#define TEST_16_ID_SFT 28
|
#define TEST_16_ID_HI 28
|
#define TEST_16_ID_SZ 1
|
#define PAD59_OE_MSK 0x00000001
|
#define PAD59_OE_I_MSK 0xfffffffe
|
#define PAD59_OE_SFT 0
|
#define PAD59_OE_HI 0
|
#define PAD59_OE_SZ 1
|
#define PAD59_PE_MSK 0x00000002
|
#define PAD59_PE_I_MSK 0xfffffffd
|
#define PAD59_PE_SFT 1
|
#define PAD59_PE_HI 1
|
#define PAD59_PE_SZ 1
|
#define PAD59_DS_MSK 0x00000004
|
#define PAD59_DS_I_MSK 0xfffffffb
|
#define PAD59_DS_SFT 2
|
#define PAD59_DS_HI 2
|
#define PAD59_DS_SZ 1
|
#define PAD59_IE_MSK 0x00000008
|
#define PAD59_IE_I_MSK 0xfffffff7
|
#define PAD59_IE_SFT 3
|
#define PAD59_IE_HI 3
|
#define PAD59_IE_SZ 1
|
#define PAD59_SEL_I_MSK 0x00000030
|
#define PAD59_SEL_I_I_MSK 0xffffffcf
|
#define PAD59_SEL_I_SFT 4
|
#define PAD59_SEL_I_HI 5
|
#define PAD59_SEL_I_SZ 2
|
#define PAD59_OD_MSK 0x00000100
|
#define PAD59_OD_I_MSK 0xfffffeff
|
#define PAD59_OD_SFT 8
|
#define PAD59_OD_HI 8
|
#define PAD59_OD_SZ 1
|
#define PAD59_SEL_O_MSK 0x00001000
|
#define PAD59_SEL_O_I_MSK 0xffffefff
|
#define PAD59_SEL_O_SFT 12
|
#define PAD59_SEL_O_HI 12
|
#define PAD59_SEL_O_SZ 1
|
#define TEST_17_ID_MSK 0x10000000
|
#define TEST_17_ID_I_MSK 0xefffffff
|
#define TEST_17_ID_SFT 28
|
#define TEST_17_ID_HI 28
|
#define TEST_17_ID_SZ 1
|
#define PAD60_OE_MSK 0x00000001
|
#define PAD60_OE_I_MSK 0xfffffffe
|
#define PAD60_OE_SFT 0
|
#define PAD60_OE_HI 0
|
#define PAD60_OE_SZ 1
|
#define PAD60_PE_MSK 0x00000002
|
#define PAD60_PE_I_MSK 0xfffffffd
|
#define PAD60_PE_SFT 1
|
#define PAD60_PE_HI 1
|
#define PAD60_PE_SZ 1
|
#define PAD60_DS_MSK 0x00000004
|
#define PAD60_DS_I_MSK 0xfffffffb
|
#define PAD60_DS_SFT 2
|
#define PAD60_DS_HI 2
|
#define PAD60_DS_SZ 1
|
#define PAD60_IE_MSK 0x00000008
|
#define PAD60_IE_I_MSK 0xfffffff7
|
#define PAD60_IE_SFT 3
|
#define PAD60_IE_HI 3
|
#define PAD60_IE_SZ 1
|
#define PAD60_SEL_I_MSK 0x00000030
|
#define PAD60_SEL_I_I_MSK 0xffffffcf
|
#define PAD60_SEL_I_SFT 4
|
#define PAD60_SEL_I_HI 5
|
#define PAD60_SEL_I_SZ 2
|
#define PAD60_OD_MSK 0x00000100
|
#define PAD60_OD_I_MSK 0xfffffeff
|
#define PAD60_OD_SFT 8
|
#define PAD60_OD_HI 8
|
#define PAD60_OD_SZ 1
|
#define PAD60_SEL_O_MSK 0x00001000
|
#define PAD60_SEL_O_I_MSK 0xffffefff
|
#define PAD60_SEL_O_SFT 12
|
#define PAD60_SEL_O_HI 12
|
#define PAD60_SEL_O_SZ 1
|
#define TEST_18_ID_MSK 0x10000000
|
#define TEST_18_ID_I_MSK 0xefffffff
|
#define TEST_18_ID_SFT 28
|
#define TEST_18_ID_HI 28
|
#define TEST_18_ID_SZ 1
|
#define PAD61_OE_MSK 0x00000001
|
#define PAD61_OE_I_MSK 0xfffffffe
|
#define PAD61_OE_SFT 0
|
#define PAD61_OE_HI 0
|
#define PAD61_OE_SZ 1
|
#define PAD61_PE_MSK 0x00000002
|
#define PAD61_PE_I_MSK 0xfffffffd
|
#define PAD61_PE_SFT 1
|
#define PAD61_PE_HI 1
|
#define PAD61_PE_SZ 1
|
#define PAD61_DS_MSK 0x00000004
|
#define PAD61_DS_I_MSK 0xfffffffb
|
#define PAD61_DS_SFT 2
|
#define PAD61_DS_HI 2
|
#define PAD61_DS_SZ 1
|
#define PAD61_IE_MSK 0x00000008
|
#define PAD61_IE_I_MSK 0xfffffff7
|
#define PAD61_IE_SFT 3
|
#define PAD61_IE_HI 3
|
#define PAD61_IE_SZ 1
|
#define PAD61_SEL_I_MSK 0x00000010
|
#define PAD61_SEL_I_I_MSK 0xffffffef
|
#define PAD61_SEL_I_SFT 4
|
#define PAD61_SEL_I_HI 4
|
#define PAD61_SEL_I_SZ 1
|
#define PAD61_OD_MSK 0x00000100
|
#define PAD61_OD_I_MSK 0xfffffeff
|
#define PAD61_OD_SFT 8
|
#define PAD61_OD_HI 8
|
#define PAD61_OD_SZ 1
|
#define PAD61_SEL_O_MSK 0x00003000
|
#define PAD61_SEL_O_I_MSK 0xffffcfff
|
#define PAD61_SEL_O_SFT 12
|
#define PAD61_SEL_O_HI 13
|
#define PAD61_SEL_O_SZ 2
|
#define TEST_19_ID_MSK 0x10000000
|
#define TEST_19_ID_I_MSK 0xefffffff
|
#define TEST_19_ID_SFT 28
|
#define TEST_19_ID_HI 28
|
#define TEST_19_ID_SZ 1
|
#define PAD62_OE_MSK 0x00000001
|
#define PAD62_OE_I_MSK 0xfffffffe
|
#define PAD62_OE_SFT 0
|
#define PAD62_OE_HI 0
|
#define PAD62_OE_SZ 1
|
#define PAD62_PE_MSK 0x00000002
|
#define PAD62_PE_I_MSK 0xfffffffd
|
#define PAD62_PE_SFT 1
|
#define PAD62_PE_HI 1
|
#define PAD62_PE_SZ 1
|
#define PAD62_DS_MSK 0x00000004
|
#define PAD62_DS_I_MSK 0xfffffffb
|
#define PAD62_DS_SFT 2
|
#define PAD62_DS_HI 2
|
#define PAD62_DS_SZ 1
|
#define PAD62_IE_MSK 0x00000008
|
#define PAD62_IE_I_MSK 0xfffffff7
|
#define PAD62_IE_SFT 3
|
#define PAD62_IE_HI 3
|
#define PAD62_IE_SZ 1
|
#define PAD62_SEL_I_MSK 0x00000010
|
#define PAD62_SEL_I_I_MSK 0xffffffef
|
#define PAD62_SEL_I_SFT 4
|
#define PAD62_SEL_I_HI 4
|
#define PAD62_SEL_I_SZ 1
|
#define PAD62_OD_MSK 0x00000100
|
#define PAD62_OD_I_MSK 0xfffffeff
|
#define PAD62_OD_SFT 8
|
#define PAD62_OD_HI 8
|
#define PAD62_OD_SZ 1
|
#define PAD62_SEL_O_MSK 0x00001000
|
#define PAD62_SEL_O_I_MSK 0xffffefff
|
#define PAD62_SEL_O_SFT 12
|
#define PAD62_SEL_O_HI 12
|
#define PAD62_SEL_O_SZ 1
|
#define TEST_20_ID_MSK 0x10000000
|
#define TEST_20_ID_I_MSK 0xefffffff
|
#define TEST_20_ID_SFT 28
|
#define TEST_20_ID_HI 28
|
#define TEST_20_ID_SZ 1
|
#define PAD64_OE_MSK 0x00000001
|
#define PAD64_OE_I_MSK 0xfffffffe
|
#define PAD64_OE_SFT 0
|
#define PAD64_OE_HI 0
|
#define PAD64_OE_SZ 1
|
#define PAD64_PE_MSK 0x00000002
|
#define PAD64_PE_I_MSK 0xfffffffd
|
#define PAD64_PE_SFT 1
|
#define PAD64_PE_HI 1
|
#define PAD64_PE_SZ 1
|
#define PAD64_DS_MSK 0x00000004
|
#define PAD64_DS_I_MSK 0xfffffffb
|
#define PAD64_DS_SFT 2
|
#define PAD64_DS_HI 2
|
#define PAD64_DS_SZ 1
|
#define PAD64_IE_MSK 0x00000008
|
#define PAD64_IE_I_MSK 0xfffffff7
|
#define PAD64_IE_SFT 3
|
#define PAD64_IE_HI 3
|
#define PAD64_IE_SZ 1
|
#define PAD64_SEL_I_MSK 0x00000070
|
#define PAD64_SEL_I_I_MSK 0xffffff8f
|
#define PAD64_SEL_I_SFT 4
|
#define PAD64_SEL_I_HI 6
|
#define PAD64_SEL_I_SZ 3
|
#define PAD64_OD_MSK 0x00000100
|
#define PAD64_OD_I_MSK 0xfffffeff
|
#define PAD64_OD_SFT 8
|
#define PAD64_OD_HI 8
|
#define PAD64_OD_SZ 1
|
#define PAD64_SEL_O_MSK 0x00003000
|
#define PAD64_SEL_O_I_MSK 0xffffcfff
|
#define PAD64_SEL_O_SFT 12
|
#define PAD64_SEL_O_HI 13
|
#define PAD64_SEL_O_SZ 2
|
#define PAD64_SEL_OE_MSK 0x00100000
|
#define PAD64_SEL_OE_I_MSK 0xffefffff
|
#define PAD64_SEL_OE_SFT 20
|
#define PAD64_SEL_OE_HI 20
|
#define PAD64_SEL_OE_SZ 1
|
#define GPIO_15_IP_ID_MSK 0x10000000
|
#define GPIO_15_IP_ID_I_MSK 0xefffffff
|
#define GPIO_15_IP_ID_SFT 28
|
#define GPIO_15_IP_ID_HI 28
|
#define GPIO_15_IP_ID_SZ 1
|
#define PAD65_OE_MSK 0x00000001
|
#define PAD65_OE_I_MSK 0xfffffffe
|
#define PAD65_OE_SFT 0
|
#define PAD65_OE_HI 0
|
#define PAD65_OE_SZ 1
|
#define PAD65_PE_MSK 0x00000002
|
#define PAD65_PE_I_MSK 0xfffffffd
|
#define PAD65_PE_SFT 1
|
#define PAD65_PE_HI 1
|
#define PAD65_PE_SZ 1
|
#define PAD65_DS_MSK 0x00000004
|
#define PAD65_DS_I_MSK 0xfffffffb
|
#define PAD65_DS_SFT 2
|
#define PAD65_DS_HI 2
|
#define PAD65_DS_SZ 1
|
#define PAD65_IE_MSK 0x00000008
|
#define PAD65_IE_I_MSK 0xfffffff7
|
#define PAD65_IE_SFT 3
|
#define PAD65_IE_HI 3
|
#define PAD65_IE_SZ 1
|
#define PAD65_SEL_I_MSK 0x00000070
|
#define PAD65_SEL_I_I_MSK 0xffffff8f
|
#define PAD65_SEL_I_SFT 4
|
#define PAD65_SEL_I_HI 6
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#define PAD65_SEL_I_SZ 3
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#define PAD65_OD_MSK 0x00000100
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#define PAD65_OD_I_MSK 0xfffffeff
|
#define PAD65_OD_SFT 8
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#define PAD65_OD_HI 8
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#define PAD65_OD_SZ 1
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#define PAD65_SEL_O_MSK 0x00001000
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#define PAD65_SEL_O_I_MSK 0xffffefff
|
#define PAD65_SEL_O_SFT 12
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#define PAD65_SEL_O_HI 12
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#define PAD65_SEL_O_SZ 1
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#define GPIO_TEST_7_IN_ID_MSK 0x10000000
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#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
|
#define GPIO_TEST_7_IN_ID_SFT 28
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#define GPIO_TEST_7_IN_ID_HI 28
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#define GPIO_TEST_7_IN_ID_SZ 1
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#define PAD66_OE_MSK 0x00000001
|
#define PAD66_OE_I_MSK 0xfffffffe
|
#define PAD66_OE_SFT 0
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#define PAD66_OE_HI 0
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#define PAD66_OE_SZ 1
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#define PAD66_PE_MSK 0x00000002
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#define PAD66_PE_I_MSK 0xfffffffd
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#define PAD66_PE_SFT 1
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#define PAD66_PE_HI 1
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#define PAD66_PE_SZ 1
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#define PAD66_DS_MSK 0x00000004
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#define PAD66_DS_I_MSK 0xfffffffb
|
#define PAD66_DS_SFT 2
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#define PAD66_DS_HI 2
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#define PAD66_DS_SZ 1
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#define PAD66_IE_MSK 0x00000008
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#define PAD66_IE_I_MSK 0xfffffff7
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#define PAD66_IE_SFT 3
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#define PAD66_IE_HI 3
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#define PAD66_IE_SZ 1
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#define PAD66_SEL_I_MSK 0x00000030
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#define PAD66_SEL_I_I_MSK 0xffffffcf
|
#define PAD66_SEL_I_SFT 4
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#define PAD66_SEL_I_HI 5
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#define PAD66_SEL_I_SZ 2
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#define PAD66_OD_MSK 0x00000100
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#define PAD66_OD_I_MSK 0xfffffeff
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#define PAD66_OD_SFT 8
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#define PAD66_OD_HI 8
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#define PAD66_OD_SZ 1
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#define PAD66_SEL_O_MSK 0x00003000
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#define PAD66_SEL_O_I_MSK 0xffffcfff
|
#define PAD66_SEL_O_SFT 12
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#define PAD66_SEL_O_HI 13
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#define PAD66_SEL_O_SZ 2
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#define GPIO_17_QP_ID_MSK 0x10000000
|
#define GPIO_17_QP_ID_I_MSK 0xefffffff
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#define GPIO_17_QP_ID_SFT 28
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#define GPIO_17_QP_ID_HI 28
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#define GPIO_17_QP_ID_SZ 1
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#define PAD68_OE_MSK 0x00000001
|
#define PAD68_OE_I_MSK 0xfffffffe
|
#define PAD68_OE_SFT 0
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#define PAD68_OE_HI 0
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#define PAD68_OE_SZ 1
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#define PAD68_PE_MSK 0x00000002
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#define PAD68_PE_I_MSK 0xfffffffd
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#define PAD68_PE_SFT 1
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#define PAD68_PE_HI 1
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#define PAD68_PE_SZ 1
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#define PAD68_DS_MSK 0x00000004
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#define PAD68_DS_I_MSK 0xfffffffb
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#define PAD68_DS_SFT 2
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#define PAD68_DS_HI 2
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#define PAD68_DS_SZ 1
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#define PAD68_IE_MSK 0x00000008
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#define PAD68_IE_I_MSK 0xfffffff7
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#define PAD68_IE_SFT 3
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#define PAD68_IE_HI 3
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#define PAD68_IE_SZ 1
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#define PAD68_OD_MSK 0x00000100
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#define PAD68_OD_I_MSK 0xfffffeff
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#define PAD68_OD_SFT 8
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#define PAD68_OD_HI 8
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#define PAD68_OD_SZ 1
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#define PAD68_SEL_O_MSK 0x00001000
|
#define PAD68_SEL_O_I_MSK 0xffffefff
|
#define PAD68_SEL_O_SFT 12
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#define PAD68_SEL_O_HI 12
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#define PAD68_SEL_O_SZ 1
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#define GPIO_19_ID_MSK 0x10000000
|
#define GPIO_19_ID_I_MSK 0xefffffff
|
#define GPIO_19_ID_SFT 28
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#define GPIO_19_ID_HI 28
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#define GPIO_19_ID_SZ 1
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#define PAD67_OE_MSK 0x00000001
|
#define PAD67_OE_I_MSK 0xfffffffe
|
#define PAD67_OE_SFT 0
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#define PAD67_OE_HI 0
|
#define PAD67_OE_SZ 1
|
#define PAD67_PE_MSK 0x00000002
|
#define PAD67_PE_I_MSK 0xfffffffd
|
#define PAD67_PE_SFT 1
|
#define PAD67_PE_HI 1
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#define PAD67_PE_SZ 1
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#define PAD67_DS_MSK 0x00000004
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#define PAD67_DS_I_MSK 0xfffffffb
|
#define PAD67_DS_SFT 2
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#define PAD67_DS_HI 2
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#define PAD67_DS_SZ 1
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#define PAD67_IE_MSK 0x00000008
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#define PAD67_IE_I_MSK 0xfffffff7
|
#define PAD67_IE_SFT 3
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#define PAD67_IE_HI 3
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#define PAD67_IE_SZ 1
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#define PAD67_SEL_I_MSK 0x00000070
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#define PAD67_SEL_I_I_MSK 0xffffff8f
|
#define PAD67_SEL_I_SFT 4
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#define PAD67_SEL_I_HI 6
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#define PAD67_SEL_I_SZ 3
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#define PAD67_OD_MSK 0x00000100
|
#define PAD67_OD_I_MSK 0xfffffeff
|
#define PAD67_OD_SFT 8
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#define PAD67_OD_HI 8
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#define PAD67_OD_SZ 1
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#define PAD67_SEL_O_MSK 0x00003000
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#define PAD67_SEL_O_I_MSK 0xffffcfff
|
#define PAD67_SEL_O_SFT 12
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#define PAD67_SEL_O_HI 13
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#define PAD67_SEL_O_SZ 2
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#define GPIO_TEST_8_QN_ID_MSK 0x10000000
|
#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
|
#define GPIO_TEST_8_QN_ID_SFT 28
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#define GPIO_TEST_8_QN_ID_HI 28
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#define GPIO_TEST_8_QN_ID_SZ 1
|
#define PAD69_OE_MSK 0x00000001
|
#define PAD69_OE_I_MSK 0xfffffffe
|
#define PAD69_OE_SFT 0
|
#define PAD69_OE_HI 0
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#define PAD69_OE_SZ 1
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#define PAD69_PE_MSK 0x00000002
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#define PAD69_PE_I_MSK 0xfffffffd
|
#define PAD69_PE_SFT 1
|
#define PAD69_PE_HI 1
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#define PAD69_PE_SZ 1
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#define PAD69_DS_MSK 0x00000004
|
#define PAD69_DS_I_MSK 0xfffffffb
|
#define PAD69_DS_SFT 2
|
#define PAD69_DS_HI 2
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#define PAD69_DS_SZ 1
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#define PAD69_IE_MSK 0x00000008
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#define PAD69_IE_I_MSK 0xfffffff7
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#define PAD69_IE_SFT 3
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#define PAD69_IE_HI 3
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#define PAD69_IE_SZ 1
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#define PAD69_SEL_I_MSK 0x00000030
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#define PAD69_SEL_I_I_MSK 0xffffffcf
|
#define PAD69_SEL_I_SFT 4
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#define PAD69_SEL_I_HI 5
|
#define PAD69_SEL_I_SZ 2
|
#define PAD69_OD_MSK 0x00000100
|
#define PAD69_OD_I_MSK 0xfffffeff
|
#define PAD69_OD_SFT 8
|
#define PAD69_OD_HI 8
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#define PAD69_OD_SZ 1
|
#define PAD69_SEL_O_MSK 0x00001000
|
#define PAD69_SEL_O_I_MSK 0xffffefff
|
#define PAD69_SEL_O_SFT 12
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#define PAD69_SEL_O_HI 12
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#define PAD69_SEL_O_SZ 1
|
#define STRAP2_MSK 0x08000000
|
#define STRAP2_I_MSK 0xf7ffffff
|
#define STRAP2_SFT 27
|
#define STRAP2_HI 27
|
#define STRAP2_SZ 1
|
#define GPIO_20_ID_MSK 0x10000000
|
#define GPIO_20_ID_I_MSK 0xefffffff
|
#define GPIO_20_ID_SFT 28
|
#define GPIO_20_ID_HI 28
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#define GPIO_20_ID_SZ 1
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#define PAD70_OE_MSK 0x00000001
|
#define PAD70_OE_I_MSK 0xfffffffe
|
#define PAD70_OE_SFT 0
|
#define PAD70_OE_HI 0
|
#define PAD70_OE_SZ 1
|
#define PAD70_PE_MSK 0x00000002
|
#define PAD70_PE_I_MSK 0xfffffffd
|
#define PAD70_PE_SFT 1
|
#define PAD70_PE_HI 1
|
#define PAD70_PE_SZ 1
|
#define PAD70_DS_MSK 0x00000004
|
#define PAD70_DS_I_MSK 0xfffffffb
|
#define PAD70_DS_SFT 2
|
#define PAD70_DS_HI 2
|
#define PAD70_DS_SZ 1
|
#define PAD70_IE_MSK 0x00000008
|
#define PAD70_IE_I_MSK 0xfffffff7
|
#define PAD70_IE_SFT 3
|
#define PAD70_IE_HI 3
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#define PAD70_IE_SZ 1
|
#define PAD70_SEL_I_MSK 0x00000030
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#define PAD70_SEL_I_I_MSK 0xffffffcf
|
#define PAD70_SEL_I_SFT 4
|
#define PAD70_SEL_I_HI 5
|
#define PAD70_SEL_I_SZ 2
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#define PAD70_OD_MSK 0x00000100
|
#define PAD70_OD_I_MSK 0xfffffeff
|
#define PAD70_OD_SFT 8
|
#define PAD70_OD_HI 8
|
#define PAD70_OD_SZ 1
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#define PAD70_SEL_O_MSK 0x00007000
|
#define PAD70_SEL_O_I_MSK 0xffff8fff
|
#define PAD70_SEL_O_SFT 12
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#define PAD70_SEL_O_HI 14
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#define PAD70_SEL_O_SZ 3
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#define GPIO_21_ID_MSK 0x10000000
|
#define GPIO_21_ID_I_MSK 0xefffffff
|
#define GPIO_21_ID_SFT 28
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#define GPIO_21_ID_HI 28
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#define GPIO_21_ID_SZ 1
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#define PAD231_OE_MSK 0x00000001
|
#define PAD231_OE_I_MSK 0xfffffffe
|
#define PAD231_OE_SFT 0
|
#define PAD231_OE_HI 0
|
#define PAD231_OE_SZ 1
|
#define PAD231_PE_MSK 0x00000002
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#define PAD231_PE_I_MSK 0xfffffffd
|
#define PAD231_PE_SFT 1
|
#define PAD231_PE_HI 1
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#define PAD231_PE_SZ 1
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#define PAD231_DS_MSK 0x00000004
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#define PAD231_DS_I_MSK 0xfffffffb
|
#define PAD231_DS_SFT 2
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#define PAD231_DS_HI 2
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#define PAD231_DS_SZ 1
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#define PAD231_IE_MSK 0x00000008
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#define PAD231_IE_I_MSK 0xfffffff7
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#define PAD231_IE_SFT 3
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#define PAD231_IE_HI 3
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#define PAD231_IE_SZ 1
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#define PAD231_OD_MSK 0x00000100
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#define PAD231_OD_I_MSK 0xfffffeff
|
#define PAD231_OD_SFT 8
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#define PAD231_OD_HI 8
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#define PAD231_OD_SZ 1
|
#define PIN_40_OR_56_ID_MSK 0x10000000
|
#define PIN_40_OR_56_ID_I_MSK 0xefffffff
|
#define PIN_40_OR_56_ID_SFT 28
|
#define PIN_40_OR_56_ID_HI 28
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#define PIN_40_OR_56_ID_SZ 1
|
#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
|
#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
|
#define MP_PHY2RX_DATA__0_SEL_SFT 0
|
#define MP_PHY2RX_DATA__0_SEL_HI 0
|
#define MP_PHY2RX_DATA__0_SEL_SZ 1
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#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
|
#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
|
#define MP_PHY2RX_DATA__1_SEL_SFT 1
|
#define MP_PHY2RX_DATA__1_SEL_HI 1
|
#define MP_PHY2RX_DATA__1_SEL_SZ 1
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#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
|
#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
|
#define MP_TX_FF_RPTR__1_SEL_SFT 2
|
#define MP_TX_FF_RPTR__1_SEL_HI 2
|
#define MP_TX_FF_RPTR__1_SEL_SZ 1
|
#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
|
#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
|
#define MP_RX_FF_WPTR__2_SEL_SFT 3
|
#define MP_RX_FF_WPTR__2_SEL_HI 3
|
#define MP_RX_FF_WPTR__2_SEL_SZ 1
|
#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
|
#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
|
#define MP_RX_FF_WPTR__1_SEL_SFT 4
|
#define MP_RX_FF_WPTR__1_SEL_HI 4
|
#define MP_RX_FF_WPTR__1_SEL_SZ 1
|
#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
|
#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
|
#define MP_RX_FF_WPTR__0_SEL_SFT 5
|
#define MP_RX_FF_WPTR__0_SEL_HI 5
|
#define MP_RX_FF_WPTR__0_SEL_SZ 1
|
#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
|
#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
|
#define MP_PHY2RX_DATA__2_SEL_SFT 6
|
#define MP_PHY2RX_DATA__2_SEL_HI 6
|
#define MP_PHY2RX_DATA__2_SEL_SZ 1
|
#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
|
#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
|
#define MP_PHY2RX_DATA__4_SEL_SFT 7
|
#define MP_PHY2RX_DATA__4_SEL_HI 7
|
#define MP_PHY2RX_DATA__4_SEL_SZ 1
|
#define I2CM_SDA_ID_SEL_MSK 0x00000300
|
#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
|
#define I2CM_SDA_ID_SEL_SFT 8
|
#define I2CM_SDA_ID_SEL_HI 9
|
#define I2CM_SDA_ID_SEL_SZ 2
|
#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
|
#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
|
#define CRYSTAL_OUT_REQ_SEL_SFT 10
|
#define CRYSTAL_OUT_REQ_SEL_HI 10
|
#define CRYSTAL_OUT_REQ_SEL_SZ 1
|
#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
|
#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
|
#define MP_PHY2RX_DATA__5_SEL_SFT 11
|
#define MP_PHY2RX_DATA__5_SEL_HI 11
|
#define MP_PHY2RX_DATA__5_SEL_SZ 1
|
#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
|
#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
|
#define MP_PHY2RX_DATA__3_SEL_SFT 12
|
#define MP_PHY2RX_DATA__3_SEL_HI 12
|
#define MP_PHY2RX_DATA__3_SEL_SZ 1
|
#define UART_RXD_SEL_MSK 0x00006000
|
#define UART_RXD_SEL_I_MSK 0xffff9fff
|
#define UART_RXD_SEL_SFT 13
|
#define UART_RXD_SEL_HI 14
|
#define UART_RXD_SEL_SZ 2
|
#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
|
#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
|
#define MP_PHY2RX_DATA__6_SEL_SFT 15
|
#define MP_PHY2RX_DATA__6_SEL_HI 15
|
#define MP_PHY2RX_DATA__6_SEL_SZ 1
|
#define DAT_UART_NCTS_SEL_MSK 0x00010000
|
#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
|
#define DAT_UART_NCTS_SEL_SFT 16
|
#define DAT_UART_NCTS_SEL_HI 16
|
#define DAT_UART_NCTS_SEL_SZ 1
|
#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
|
#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
|
#define GPIO_LOG_STOP_SEL_SFT 17
|
#define GPIO_LOG_STOP_SEL_HI 19
|
#define GPIO_LOG_STOP_SEL_SZ 3
|
#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
|
#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
|
#define MP_TX_FF_RPTR__0_SEL_SFT 20
|
#define MP_TX_FF_RPTR__0_SEL_HI 20
|
#define MP_TX_FF_RPTR__0_SEL_SZ 1
|
#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
|
#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
|
#define MP_PHY_RX_WRST_N_SEL_SFT 21
|
#define MP_PHY_RX_WRST_N_SEL_HI 21
|
#define MP_PHY_RX_WRST_N_SEL_SZ 1
|
#define EXT_32K_SEL_MSK 0x00c00000
|
#define EXT_32K_SEL_I_MSK 0xff3fffff
|
#define EXT_32K_SEL_SFT 22
|
#define EXT_32K_SEL_HI 23
|
#define EXT_32K_SEL_SZ 2
|
#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
|
#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
|
#define MP_PHY2RX_DATA__7_SEL_SFT 24
|
#define MP_PHY2RX_DATA__7_SEL_HI 24
|
#define MP_PHY2RX_DATA__7_SEL_SZ 1
|
#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
|
#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
|
#define MP_TX_FF_RPTR__2_SEL_SFT 25
|
#define MP_TX_FF_RPTR__2_SEL_HI 25
|
#define MP_TX_FF_RPTR__2_SEL_SZ 1
|
#define PMUINT_WAKE_SEL_MSK 0x1c000000
|
#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
|
#define PMUINT_WAKE_SEL_SFT 26
|
#define PMUINT_WAKE_SEL_HI 28
|
#define PMUINT_WAKE_SEL_SZ 3
|
#define I2CM_SCL_ID_SEL_MSK 0x20000000
|
#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
|
#define I2CM_SCL_ID_SEL_SFT 29
|
#define I2CM_SCL_ID_SEL_HI 29
|
#define I2CM_SCL_ID_SEL_SZ 1
|
#define MP_MRX_RX_EN_SEL_MSK 0x40000000
|
#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
|
#define MP_MRX_RX_EN_SEL_SFT 30
|
#define MP_MRX_RX_EN_SEL_HI 30
|
#define MP_MRX_RX_EN_SEL_SZ 1
|
#define DAT_UART_RXD_SEL_0_MSK 0x80000000
|
#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
|
#define DAT_UART_RXD_SEL_0_SFT 31
|
#define DAT_UART_RXD_SEL_0_HI 31
|
#define DAT_UART_RXD_SEL_0_SZ 1
|
#define DAT_UART_RXD_SEL_1_MSK 0x00000001
|
#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
|
#define DAT_UART_RXD_SEL_1_SFT 0
|
#define DAT_UART_RXD_SEL_1_HI 0
|
#define DAT_UART_RXD_SEL_1_SZ 1
|
#define SPI_DI_SEL_MSK 0x00000002
|
#define SPI_DI_SEL_I_MSK 0xfffffffd
|
#define SPI_DI_SEL_SFT 1
|
#define SPI_DI_SEL_HI 1
|
#define SPI_DI_SEL_SZ 1
|
#define IO_PORT_REG_MSK 0x0001ffff
|
#define IO_PORT_REG_I_MSK 0xfffe0000
|
#define IO_PORT_REG_SFT 0
|
#define IO_PORT_REG_HI 16
|
#define IO_PORT_REG_SZ 17
|
#define MASK_RX_INT_MSK 0x00000001
|
#define MASK_RX_INT_I_MSK 0xfffffffe
|
#define MASK_RX_INT_SFT 0
|
#define MASK_RX_INT_HI 0
|
#define MASK_RX_INT_SZ 1
|
#define MASK_TX_INT_MSK 0x00000002
|
#define MASK_TX_INT_I_MSK 0xfffffffd
|
#define MASK_TX_INT_SFT 1
|
#define MASK_TX_INT_HI 1
|
#define MASK_TX_INT_SZ 1
|
#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
|
#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
|
#define MASK_SOC_SYSTEM_INT_SFT 2
|
#define MASK_SOC_SYSTEM_INT_HI 2
|
#define MASK_SOC_SYSTEM_INT_SZ 1
|
#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
|
#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
|
#define EDCA0_LOW_THR_INT_MASK_SFT 3
|
#define EDCA0_LOW_THR_INT_MASK_HI 3
|
#define EDCA0_LOW_THR_INT_MASK_SZ 1
|
#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
|
#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
|
#define EDCA1_LOW_THR_INT_MASK_SFT 4
|
#define EDCA1_LOW_THR_INT_MASK_HI 4
|
#define EDCA1_LOW_THR_INT_MASK_SZ 1
|
#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
|
#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
|
#define EDCA2_LOW_THR_INT_MASK_SFT 5
|
#define EDCA2_LOW_THR_INT_MASK_HI 5
|
#define EDCA2_LOW_THR_INT_MASK_SZ 1
|
#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
|
#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
|
#define EDCA3_LOW_THR_INT_MASK_SFT 6
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#define EDCA3_LOW_THR_INT_MASK_HI 6
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#define EDCA3_LOW_THR_INT_MASK_SZ 1
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#define TX_LIMIT_INT_MASK_MSK 0x00000080
|
#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
|
#define TX_LIMIT_INT_MASK_SFT 7
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#define TX_LIMIT_INT_MASK_HI 7
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#define TX_LIMIT_INT_MASK_SZ 1
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#define RX_INT_MSK 0x00000001
|
#define RX_INT_I_MSK 0xfffffffe
|
#define RX_INT_SFT 0
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#define RX_INT_HI 0
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#define RX_INT_SZ 1
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#define TX_COMPLETE_INT_MSK 0x00000002
|
#define TX_COMPLETE_INT_I_MSK 0xfffffffd
|
#define TX_COMPLETE_INT_SFT 1
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#define TX_COMPLETE_INT_HI 1
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#define TX_COMPLETE_INT_SZ 1
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#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
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#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
|
#define SOC_SYSTEM_INT_STATUS_SFT 2
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#define SOC_SYSTEM_INT_STATUS_HI 2
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#define SOC_SYSTEM_INT_STATUS_SZ 1
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#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
|
#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
|
#define EDCA0_LOW_THR_INT_STS_SFT 3
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#define EDCA0_LOW_THR_INT_STS_HI 3
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#define EDCA0_LOW_THR_INT_STS_SZ 1
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#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
|
#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
|
#define EDCA1_LOW_THR_INT_STS_SFT 4
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#define EDCA1_LOW_THR_INT_STS_HI 4
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#define EDCA1_LOW_THR_INT_STS_SZ 1
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#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
|
#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
|
#define EDCA2_LOW_THR_INT_STS_SFT 5
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#define EDCA2_LOW_THR_INT_STS_HI 5
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#define EDCA2_LOW_THR_INT_STS_SZ 1
|
#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
|
#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
|
#define EDCA3_LOW_THR_INT_STS_SFT 6
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#define EDCA3_LOW_THR_INT_STS_HI 6
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#define EDCA3_LOW_THR_INT_STS_SZ 1
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#define TX_LIMIT_INT_STS_MSK 0x00000080
|
#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
|
#define TX_LIMIT_INT_STS_SFT 7
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#define TX_LIMIT_INT_STS_HI 7
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#define TX_LIMIT_INT_STS_SZ 1
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#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
|
#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
|
#define HOST_TRIGGERED_RX_INT_SFT 8
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#define HOST_TRIGGERED_RX_INT_HI 8
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#define HOST_TRIGGERED_RX_INT_SZ 1
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#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
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#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
|
#define HOST_TRIGGERED_TX_INT_SFT 9
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#define HOST_TRIGGERED_TX_INT_HI 9
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#define HOST_TRIGGERED_TX_INT_SZ 1
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#define SOC_TRIGGER_RX_INT_MSK 0x00000400
|
#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
|
#define SOC_TRIGGER_RX_INT_SFT 10
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#define SOC_TRIGGER_RX_INT_HI 10
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#define SOC_TRIGGER_RX_INT_SZ 1
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#define SOC_TRIGGER_TX_INT_MSK 0x00000800
|
#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
|
#define SOC_TRIGGER_TX_INT_SFT 11
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#define SOC_TRIGGER_TX_INT_HI 11
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#define SOC_TRIGGER_TX_INT_SZ 1
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#define RDY_FOR_TX_RX_MSK 0x00000001
|
#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
|
#define RDY_FOR_TX_RX_SFT 0
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#define RDY_FOR_TX_RX_HI 0
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#define RDY_FOR_TX_RX_SZ 1
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#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
|
#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
|
#define RDY_FOR_FW_DOWNLOAD_SFT 1
|
#define RDY_FOR_FW_DOWNLOAD_HI 1
|
#define RDY_FOR_FW_DOWNLOAD_SZ 1
|
#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
|
#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
|
#define ILLEGAL_CMD_RESP_OPTION_SFT 2
|
#define ILLEGAL_CMD_RESP_OPTION_HI 2
|
#define ILLEGAL_CMD_RESP_OPTION_SZ 1
|
#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
|
#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
|
#define SDIO_TRX_DATA_SEQUENCE_SFT 3
|
#define SDIO_TRX_DATA_SEQUENCE_HI 3
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#define SDIO_TRX_DATA_SEQUENCE_SZ 1
|
#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
|
#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
|
#define GPIO_INT_TRIGGER_OPTION_SFT 4
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#define GPIO_INT_TRIGGER_OPTION_HI 4
|
#define GPIO_INT_TRIGGER_OPTION_SZ 1
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#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
|
#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
|
#define TRIGGER_FUNCTION_SETTING_SFT 5
|
#define TRIGGER_FUNCTION_SETTING_HI 6
|
#define TRIGGER_FUNCTION_SETTING_SZ 2
|
#define CMD52_ABORT_RESPONSE_MSK 0x00000080
|
#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
|
#define CMD52_ABORT_RESPONSE_SFT 7
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#define CMD52_ABORT_RESPONSE_HI 7
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#define CMD52_ABORT_RESPONSE_SZ 1
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#define RX_PACKET_LENGTH_MSK 0x0000ffff
|
#define RX_PACKET_LENGTH_I_MSK 0xffff0000
|
#define RX_PACKET_LENGTH_SFT 0
|
#define RX_PACKET_LENGTH_HI 15
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#define RX_PACKET_LENGTH_SZ 16
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#define CARD_FW_DL_STATUS_MSK 0x00ff0000
|
#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
|
#define CARD_FW_DL_STATUS_SFT 16
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#define CARD_FW_DL_STATUS_HI 23
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#define CARD_FW_DL_STATUS_SZ 8
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#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
|
#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
|
#define TX_RX_LOOP_BACK_TEST_SFT 24
|
#define TX_RX_LOOP_BACK_TEST_HI 24
|
#define TX_RX_LOOP_BACK_TEST_SZ 1
|
#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
|
#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
|
#define SDIO_LOOP_BACK_TEST_SFT 25
|
#define SDIO_LOOP_BACK_TEST_HI 25
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#define SDIO_LOOP_BACK_TEST_SZ 1
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#define CMD52_ABORT_ACTIVE_MSK 0x10000000
|
#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
|
#define CMD52_ABORT_ACTIVE_SFT 28
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#define CMD52_ABORT_ACTIVE_HI 28
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#define CMD52_ABORT_ACTIVE_SZ 1
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#define CMD52_RESET_ACTIVE_MSK 0x20000000
|
#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
|
#define CMD52_RESET_ACTIVE_SFT 29
|
#define CMD52_RESET_ACTIVE_HI 29
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#define CMD52_RESET_ACTIVE_SZ 1
|
#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
|
#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
|
#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
|
#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
|
#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
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#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
|
#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
|
#define SDIO_ALL_RESE_ACTIVE_SFT 31
|
#define SDIO_ALL_RESE_ACTIVE_HI 31
|
#define SDIO_ALL_RESE_ACTIVE_SZ 1
|
#define RX_PACKET_LENGTH2_MSK 0x0000ffff
|
#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
|
#define RX_PACKET_LENGTH2_SFT 0
|
#define RX_PACKET_LENGTH2_HI 15
|
#define RX_PACKET_LENGTH2_SZ 16
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#define RX_INT1_MSK 0x00010000
|
#define RX_INT1_I_MSK 0xfffeffff
|
#define RX_INT1_SFT 16
|
#define RX_INT1_HI 16
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#define RX_INT1_SZ 1
|
#define TX_DONE_MSK 0x00020000
|
#define TX_DONE_I_MSK 0xfffdffff
|
#define TX_DONE_SFT 17
|
#define TX_DONE_HI 17
|
#define TX_DONE_SZ 1
|
#define HCI_TRX_FINISH_MSK 0x00040000
|
#define HCI_TRX_FINISH_I_MSK 0xfffbffff
|
#define HCI_TRX_FINISH_SFT 18
|
#define HCI_TRX_FINISH_HI 18
|
#define HCI_TRX_FINISH_SZ 1
|
#define ALLOCATE_STATUS_MSK 0x00080000
|
#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
|
#define ALLOCATE_STATUS_SFT 19
|
#define ALLOCATE_STATUS_HI 19
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#define ALLOCATE_STATUS_SZ 1
|
#define HCI_INPUT_FF_CNT_MSK 0x00f00000
|
#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
|
#define HCI_INPUT_FF_CNT_SFT 20
|
#define HCI_INPUT_FF_CNT_HI 23
|
#define HCI_INPUT_FF_CNT_SZ 4
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#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
|
#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
|
#define HCI_OUTPUT_FF_CNT_SFT 24
|
#define HCI_OUTPUT_FF_CNT_HI 28
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#define HCI_OUTPUT_FF_CNT_SZ 5
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#define AHB_HANG4_MSK 0x20000000
|
#define AHB_HANG4_I_MSK 0xdfffffff
|
#define AHB_HANG4_SFT 29
|
#define AHB_HANG4_HI 29
|
#define AHB_HANG4_SZ 1
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#define HCI_IN_QUE_EMPTY_MSK 0x40000000
|
#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
|
#define HCI_IN_QUE_EMPTY_SFT 30
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#define HCI_IN_QUE_EMPTY_HI 30
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#define HCI_IN_QUE_EMPTY_SZ 1
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#define SYSTEM_INT_MSK 0x80000000
|
#define SYSTEM_INT_I_MSK 0x7fffffff
|
#define SYSTEM_INT_SFT 31
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#define SYSTEM_INT_HI 31
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#define SYSTEM_INT_SZ 1
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#define CARD_RCA_REG_MSK 0x0000ffff
|
#define CARD_RCA_REG_I_MSK 0xffff0000
|
#define CARD_RCA_REG_SFT 0
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#define CARD_RCA_REG_HI 15
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#define CARD_RCA_REG_SZ 16
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#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
|
#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
|
#define SDIO_FIFO_WR_THLD_REG_SFT 0
|
#define SDIO_FIFO_WR_THLD_REG_HI 8
|
#define SDIO_FIFO_WR_THLD_REG_SZ 9
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#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
|
#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
|
#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
|
#define SDIO_FIFO_WR_LIMIT_REG_HI 8
|
#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
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#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
|
#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
|
#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
|
#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
|
#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
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#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
|
#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
|
#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
|
#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
|
#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
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#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
|
#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
|
#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
|
#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
|
#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
|
#define START_BYTE_VALUE_MSK 0x000000ff
|
#define START_BYTE_VALUE_I_MSK 0xffffff00
|
#define START_BYTE_VALUE_SFT 0
|
#define START_BYTE_VALUE_HI 7
|
#define START_BYTE_VALUE_SZ 8
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#define END_BYTE_VALUE_MSK 0x0000ff00
|
#define END_BYTE_VALUE_I_MSK 0xffff00ff
|
#define END_BYTE_VALUE_SFT 8
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#define END_BYTE_VALUE_HI 15
|
#define END_BYTE_VALUE_SZ 8
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#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
|
#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
|
#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
|
#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
|
#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
|
#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
|
#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
|
#define SDIO_LAST_CMD_INDEX_REG_SFT 0
|
#define SDIO_LAST_CMD_INDEX_REG_HI 5
|
#define SDIO_LAST_CMD_INDEX_REG_SZ 6
|
#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
|
#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
|
#define SDIO_LAST_CMD_CRC_REG_SFT 8
|
#define SDIO_LAST_CMD_CRC_REG_HI 14
|
#define SDIO_LAST_CMD_CRC_REG_SZ 7
|
#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
|
#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
|
#define SDIO_LAST_CMD_ARG_REG_SFT 0
|
#define SDIO_LAST_CMD_ARG_REG_HI 31
|
#define SDIO_LAST_CMD_ARG_REG_SZ 32
|
#define SDIO_BUS_STATE_REG_MSK 0x0000001f
|
#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
|
#define SDIO_BUS_STATE_REG_SFT 0
|
#define SDIO_BUS_STATE_REG_HI 4
|
#define SDIO_BUS_STATE_REG_SZ 5
|
#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
|
#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
|
#define SDIO_BUSY_LONG_CNT_SFT 16
|
#define SDIO_BUSY_LONG_CNT_HI 31
|
#define SDIO_BUSY_LONG_CNT_SZ 16
|
#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
|
#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
|
#define SDIO_CARD_STATUS_REG_SFT 0
|
#define SDIO_CARD_STATUS_REG_HI 31
|
#define SDIO_CARD_STATUS_REG_SZ 32
|
#define R5_RESPONSE_FLAG_MSK 0x000000ff
|
#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
|
#define R5_RESPONSE_FLAG_SFT 0
|
#define R5_RESPONSE_FLAG_HI 7
|
#define R5_RESPONSE_FLAG_SZ 8
|
#define RESP_OUT_EDGE_MSK 0x00000100
|
#define RESP_OUT_EDGE_I_MSK 0xfffffeff
|
#define RESP_OUT_EDGE_SFT 8
|
#define RESP_OUT_EDGE_HI 8
|
#define RESP_OUT_EDGE_SZ 1
|
#define DAT_OUT_EDGE_MSK 0x00000200
|
#define DAT_OUT_EDGE_I_MSK 0xfffffdff
|
#define DAT_OUT_EDGE_SFT 9
|
#define DAT_OUT_EDGE_HI 9
|
#define DAT_OUT_EDGE_SZ 1
|
#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
|
#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
|
#define MCU_TO_SDIO_INFO_MASK_SFT 16
|
#define MCU_TO_SDIO_INFO_MASK_HI 16
|
#define MCU_TO_SDIO_INFO_MASK_SZ 1
|
#define INT_THROUGH_PIN_MSK 0x00020000
|
#define INT_THROUGH_PIN_I_MSK 0xfffdffff
|
#define INT_THROUGH_PIN_SFT 17
|
#define INT_THROUGH_PIN_HI 17
|
#define INT_THROUGH_PIN_SZ 1
|
#define WRITE_DATA_MSK 0x000000ff
|
#define WRITE_DATA_I_MSK 0xffffff00
|
#define WRITE_DATA_SFT 0
|
#define WRITE_DATA_HI 7
|
#define WRITE_DATA_SZ 8
|
#define WRITE_ADDRESS_MSK 0x0000ff00
|
#define WRITE_ADDRESS_I_MSK 0xffff00ff
|
#define WRITE_ADDRESS_SFT 8
|
#define WRITE_ADDRESS_HI 15
|
#define WRITE_ADDRESS_SZ 8
|
#define READ_DATA_MSK 0x00ff0000
|
#define READ_DATA_I_MSK 0xff00ffff
|
#define READ_DATA_SFT 16
|
#define READ_DATA_HI 23
|
#define READ_DATA_SZ 8
|
#define READ_ADDRESS_MSK 0xff000000
|
#define READ_ADDRESS_I_MSK 0x00ffffff
|
#define READ_ADDRESS_SFT 24
|
#define READ_ADDRESS_HI 31
|
#define READ_ADDRESS_SZ 8
|
#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
|
#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
|
#define FN1_DMA_START_ADDR_REG_SFT 0
|
#define FN1_DMA_START_ADDR_REG_HI 31
|
#define FN1_DMA_START_ADDR_REG_SZ 32
|
#define SDIO_TO_MCU_INFO_MSK 0x000000ff
|
#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
|
#define SDIO_TO_MCU_INFO_SFT 0
|
#define SDIO_TO_MCU_INFO_HI 7
|
#define SDIO_TO_MCU_INFO_SZ 8
|
#define SDIO_PARTIAL_RESET_MSK 0x00000100
|
#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
|
#define SDIO_PARTIAL_RESET_SFT 8
|
#define SDIO_PARTIAL_RESET_HI 8
|
#define SDIO_PARTIAL_RESET_SZ 1
|
#define SDIO_ALL_RESET_MSK 0x00000200
|
#define SDIO_ALL_RESET_I_MSK 0xfffffdff
|
#define SDIO_ALL_RESET_SFT 9
|
#define SDIO_ALL_RESET_HI 9
|
#define SDIO_ALL_RESET_SZ 1
|
#define PERI_MAC_ALL_RESET_MSK 0x00000400
|
#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
|
#define PERI_MAC_ALL_RESET_SFT 10
|
#define PERI_MAC_ALL_RESET_HI 10
|
#define PERI_MAC_ALL_RESET_SZ 1
|
#define MAC_ALL_RESET_MSK 0x00000800
|
#define MAC_ALL_RESET_I_MSK 0xfffff7ff
|
#define MAC_ALL_RESET_SFT 11
|
#define MAC_ALL_RESET_HI 11
|
#define MAC_ALL_RESET_SZ 1
|
#define AHB_BRIDGE_RESET_MSK 0x00001000
|
#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
|
#define AHB_BRIDGE_RESET_SFT 12
|
#define AHB_BRIDGE_RESET_HI 12
|
#define AHB_BRIDGE_RESET_SZ 1
|
#define IO_REG_PORT_REG_MSK 0x0001ffff
|
#define IO_REG_PORT_REG_I_MSK 0xfffe0000
|
#define IO_REG_PORT_REG_SFT 0
|
#define IO_REG_PORT_REG_HI 16
|
#define IO_REG_PORT_REG_SZ 17
|
#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
|
#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
|
#define SDIO_FIFO_EMPTY_CNT_SFT 0
|
#define SDIO_FIFO_EMPTY_CNT_HI 15
|
#define SDIO_FIFO_EMPTY_CNT_SZ 16
|
#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
|
#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
|
#define SDIO_FIFO_FULL_CNT_SFT 16
|
#define SDIO_FIFO_FULL_CNT_HI 31
|
#define SDIO_FIFO_FULL_CNT_SZ 16
|
#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
|
#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
|
#define SDIO_CRC7_ERROR_CNT_SFT 0
|
#define SDIO_CRC7_ERROR_CNT_HI 15
|
#define SDIO_CRC7_ERROR_CNT_SZ 16
|
#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
|
#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
|
#define SDIO_CRC16_ERROR_CNT_SFT 16
|
#define SDIO_CRC16_ERROR_CNT_HI 31
|
#define SDIO_CRC16_ERROR_CNT_SZ 16
|
#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
|
#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
|
#define SDIO_RD_BLOCK_CNT_SFT 0
|
#define SDIO_RD_BLOCK_CNT_HI 8
|
#define SDIO_RD_BLOCK_CNT_SZ 9
|
#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
|
#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
|
#define SDIO_WR_BLOCK_CNT_SFT 16
|
#define SDIO_WR_BLOCK_CNT_HI 24
|
#define SDIO_WR_BLOCK_CNT_SZ 9
|
#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
|
#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
|
#define CMD52_RD_ABORT_CNT_SFT 16
|
#define CMD52_RD_ABORT_CNT_HI 19
|
#define CMD52_RD_ABORT_CNT_SZ 4
|
#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
|
#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
|
#define CMD52_WR_ABORT_CNT_SFT 20
|
#define CMD52_WR_ABORT_CNT_HI 23
|
#define CMD52_WR_ABORT_CNT_SZ 4
|
#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
|
#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
|
#define SDIO_FIFO_WR_PTR_REG_SFT 0
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#define SDIO_FIFO_WR_PTR_REG_HI 7
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#define SDIO_FIFO_WR_PTR_REG_SZ 8
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#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
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#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
|
#define SDIO_FIFO_RD_PTR_REG_SFT 8
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#define SDIO_FIFO_RD_PTR_REG_HI 15
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#define SDIO_FIFO_RD_PTR_REG_SZ 8
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#define SDIO_READ_DATA_CTRL_MSK 0x00010000
|
#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
|
#define SDIO_READ_DATA_CTRL_SFT 16
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#define SDIO_READ_DATA_CTRL_HI 16
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#define SDIO_READ_DATA_CTRL_SZ 1
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#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
|
#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
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#define TX_SIZE_BEFORE_SHIFT_SFT 0
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#define TX_SIZE_BEFORE_SHIFT_HI 7
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#define TX_SIZE_BEFORE_SHIFT_SZ 8
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#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
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#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
|
#define TX_SIZE_SHIFT_BITS_SFT 8
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#define TX_SIZE_SHIFT_BITS_HI 10
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#define TX_SIZE_SHIFT_BITS_SZ 3
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#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
|
#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
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#define SDIO_TX_ALLOC_STATE_SFT 12
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#define SDIO_TX_ALLOC_STATE_HI 12
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#define SDIO_TX_ALLOC_STATE_SZ 1
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#define ALLOCATE_STATUS2_MSK 0x00010000
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#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
|
#define ALLOCATE_STATUS2_SFT 16
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#define ALLOCATE_STATUS2_HI 16
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#define ALLOCATE_STATUS2_SZ 1
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#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
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#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
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#define NO_ALLOCATE_SEND_ERROR_SFT 17
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#define NO_ALLOCATE_SEND_ERROR_HI 17
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#define NO_ALLOCATE_SEND_ERROR_SZ 1
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#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
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#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
|
#define DOUBLE_ALLOCATE_ERROR_SFT 18
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#define DOUBLE_ALLOCATE_ERROR_HI 18
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#define DOUBLE_ALLOCATE_ERROR_SZ 1
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#define TX_DONE_STATUS_MSK 0x00080000
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#define TX_DONE_STATUS_I_MSK 0xfff7ffff
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#define TX_DONE_STATUS_SFT 19
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#define TX_DONE_STATUS_HI 19
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#define TX_DONE_STATUS_SZ 1
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#define AHB_HANG2_MSK 0x00100000
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#define AHB_HANG2_I_MSK 0xffefffff
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#define AHB_HANG2_SFT 20
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#define AHB_HANG2_HI 20
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#define AHB_HANG2_SZ 1
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#define HCI_TRX_FINISH2_MSK 0x00200000
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#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
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#define HCI_TRX_FINISH2_SFT 21
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#define HCI_TRX_FINISH2_HI 21
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#define HCI_TRX_FINISH2_SZ 1
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#define INTR_RX_MSK 0x00400000
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#define INTR_RX_I_MSK 0xffbfffff
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#define INTR_RX_SFT 22
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#define INTR_RX_HI 22
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#define INTR_RX_SZ 1
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#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
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#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
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#define HCI_INPUT_QUEUE_FULL_SFT 23
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#define HCI_INPUT_QUEUE_FULL_HI 23
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#define HCI_INPUT_QUEUE_FULL_SZ 1
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#define ALLOCATESTATUS_MSK 0x00000001
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#define ALLOCATESTATUS_I_MSK 0xfffffffe
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#define ALLOCATESTATUS_SFT 0
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#define ALLOCATESTATUS_HI 0
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#define ALLOCATESTATUS_SZ 1
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#define HCI_TRX_FINISH3_MSK 0x00000002
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#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
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#define HCI_TRX_FINISH3_SFT 1
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#define HCI_TRX_FINISH3_HI 1
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#define HCI_TRX_FINISH3_SZ 1
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#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
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#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
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#define HCI_IN_QUE_EMPTY2_SFT 2
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#define HCI_IN_QUE_EMPTY2_HI 2
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#define HCI_IN_QUE_EMPTY2_SZ 1
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#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
|
#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
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#define MTX_MNG_UPTHOLD_INT_SFT 3
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#define MTX_MNG_UPTHOLD_INT_HI 3
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#define MTX_MNG_UPTHOLD_INT_SZ 1
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#define EDCA0_UPTHOLD_INT_MSK 0x00000010
|
#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
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#define EDCA0_UPTHOLD_INT_SFT 4
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#define EDCA0_UPTHOLD_INT_HI 4
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#define EDCA0_UPTHOLD_INT_SZ 1
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#define EDCA1_UPTHOLD_INT_MSK 0x00000020
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#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
|
#define EDCA1_UPTHOLD_INT_SFT 5
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#define EDCA1_UPTHOLD_INT_HI 5
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#define EDCA1_UPTHOLD_INT_SZ 1
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#define EDCA2_UPTHOLD_INT_MSK 0x00000040
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#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
|
#define EDCA2_UPTHOLD_INT_SFT 6
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#define EDCA2_UPTHOLD_INT_HI 6
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#define EDCA2_UPTHOLD_INT_SZ 1
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#define EDCA3_UPTHOLD_INT_MSK 0x00000080
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#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
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#define EDCA3_UPTHOLD_INT_SFT 7
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#define EDCA3_UPTHOLD_INT_HI 7
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#define EDCA3_UPTHOLD_INT_SZ 1
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#define TX_PAGE_REMAIN2_MSK 0x0000ff00
|
#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
|
#define TX_PAGE_REMAIN2_SFT 8
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#define TX_PAGE_REMAIN2_HI 15
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#define TX_PAGE_REMAIN2_SZ 8
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#define TX_ID_REMAIN3_MSK 0x007f0000
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#define TX_ID_REMAIN3_I_MSK 0xff80ffff
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#define TX_ID_REMAIN3_SFT 16
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#define TX_ID_REMAIN3_HI 22
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#define TX_ID_REMAIN3_SZ 7
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#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
|
#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
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#define HCI_OUTPUT_FF_CNT_0_SFT 23
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#define HCI_OUTPUT_FF_CNT_0_HI 23
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#define HCI_OUTPUT_FF_CNT_0_SZ 1
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#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
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#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
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#define HCI_OUTPUT_FF_CNT2_SFT 24
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#define HCI_OUTPUT_FF_CNT2_HI 27
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#define HCI_OUTPUT_FF_CNT2_SZ 4
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#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
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#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
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#define HCI_INPUT_FF_CNT2_SFT 28
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#define HCI_INPUT_FF_CNT2_HI 31
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#define HCI_INPUT_FF_CNT2_SZ 4
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#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
|
#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
|
#define F1_BLOCK_SIZE_0_REG_SFT 0
|
#define F1_BLOCK_SIZE_0_REG_HI 11
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#define F1_BLOCK_SIZE_0_REG_SZ 12
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#define START_BYTE_VALUE2_MSK 0x000000ff
|
#define START_BYTE_VALUE2_I_MSK 0xffffff00
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#define START_BYTE_VALUE2_SFT 0
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#define START_BYTE_VALUE2_HI 7
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#define START_BYTE_VALUE2_SZ 8
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#define COMMAND_COUNTER_MSK 0x0000ff00
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#define COMMAND_COUNTER_I_MSK 0xffff00ff
|
#define COMMAND_COUNTER_SFT 8
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#define COMMAND_COUNTER_HI 15
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#define COMMAND_COUNTER_SZ 8
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#define CMD_LOG_PART1_MSK 0xffff0000
|
#define CMD_LOG_PART1_I_MSK 0x0000ffff
|
#define CMD_LOG_PART1_SFT 16
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#define CMD_LOG_PART1_HI 31
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#define CMD_LOG_PART1_SZ 16
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#define CMD_LOG_PART2_MSK 0x00ffffff
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#define CMD_LOG_PART2_I_MSK 0xff000000
|
#define CMD_LOG_PART2_SFT 0
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#define CMD_LOG_PART2_HI 23
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#define CMD_LOG_PART2_SZ 24
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#define END_BYTE_VALUE2_MSK 0xff000000
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#define END_BYTE_VALUE2_I_MSK 0x00ffffff
|
#define END_BYTE_VALUE2_SFT 24
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#define END_BYTE_VALUE2_HI 31
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#define END_BYTE_VALUE2_SZ 8
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#define RX_PACKET_LENGTH3_MSK 0x0000ffff
|
#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
|
#define RX_PACKET_LENGTH3_SFT 0
|
#define RX_PACKET_LENGTH3_HI 15
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#define RX_PACKET_LENGTH3_SZ 16
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#define RX_INT3_MSK 0x00010000
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#define RX_INT3_I_MSK 0xfffeffff
|
#define RX_INT3_SFT 16
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#define RX_INT3_HI 16
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#define RX_INT3_SZ 1
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#define TX_ID_REMAIN2_MSK 0x00fe0000
|
#define TX_ID_REMAIN2_I_MSK 0xff01ffff
|
#define TX_ID_REMAIN2_SFT 17
|
#define TX_ID_REMAIN2_HI 23
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#define TX_ID_REMAIN2_SZ 7
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#define TX_PAGE_REMAIN3_MSK 0xff000000
|
#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
|
#define TX_PAGE_REMAIN3_SFT 24
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#define TX_PAGE_REMAIN3_HI 31
|
#define TX_PAGE_REMAIN3_SZ 8
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#define CCCR_00H_REG_MSK 0x000000ff
|
#define CCCR_00H_REG_I_MSK 0xffffff00
|
#define CCCR_00H_REG_SFT 0
|
#define CCCR_00H_REG_HI 7
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#define CCCR_00H_REG_SZ 8
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#define CCCR_02H_REG_MSK 0x00ff0000
|
#define CCCR_02H_REG_I_MSK 0xff00ffff
|
#define CCCR_02H_REG_SFT 16
|
#define CCCR_02H_REG_HI 23
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#define CCCR_02H_REG_SZ 8
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#define CCCR_03H_REG_MSK 0xff000000
|
#define CCCR_03H_REG_I_MSK 0x00ffffff
|
#define CCCR_03H_REG_SFT 24
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#define CCCR_03H_REG_HI 31
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#define CCCR_03H_REG_SZ 8
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#define CCCR_04H_REG_MSK 0x000000ff
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#define CCCR_04H_REG_I_MSK 0xffffff00
|
#define CCCR_04H_REG_SFT 0
|
#define CCCR_04H_REG_HI 7
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#define CCCR_04H_REG_SZ 8
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#define CCCR_05H_REG_MSK 0x0000ff00
|
#define CCCR_05H_REG_I_MSK 0xffff00ff
|
#define CCCR_05H_REG_SFT 8
|
#define CCCR_05H_REG_HI 15
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#define CCCR_05H_REG_SZ 8
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#define CCCR_06H_REG_MSK 0x000f0000
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#define CCCR_06H_REG_I_MSK 0xfff0ffff
|
#define CCCR_06H_REG_SFT 16
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#define CCCR_06H_REG_HI 19
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#define CCCR_06H_REG_SZ 4
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#define CCCR_07H_REG_MSK 0xff000000
|
#define CCCR_07H_REG_I_MSK 0x00ffffff
|
#define CCCR_07H_REG_SFT 24
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#define CCCR_07H_REG_HI 31
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#define CCCR_07H_REG_SZ 8
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#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
|
#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
|
#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
|
#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
|
#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
|
#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
|
#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
|
#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
|
#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
|
#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
|
#define SUPPORT_READ_WAIT_MSK 0x00000004
|
#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
|
#define SUPPORT_READ_WAIT_SFT 2
|
#define SUPPORT_READ_WAIT_HI 2
|
#define SUPPORT_READ_WAIT_SZ 1
|
#define SUPPORT_BUS_CONTROL_MSK 0x00000008
|
#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
|
#define SUPPORT_BUS_CONTROL_SFT 3
|
#define SUPPORT_BUS_CONTROL_HI 3
|
#define SUPPORT_BUS_CONTROL_SZ 1
|
#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
|
#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
|
#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
|
#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
|
#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
|
#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
|
#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
|
#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
|
#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
|
#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
|
#define LOW_SPEED_CARD_MSK 0x00000040
|
#define LOW_SPEED_CARD_I_MSK 0xffffffbf
|
#define LOW_SPEED_CARD_SFT 6
|
#define LOW_SPEED_CARD_HI 6
|
#define LOW_SPEED_CARD_SZ 1
|
#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
|
#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
|
#define LOW_SPEED_CARD_4BIT_SFT 7
|
#define LOW_SPEED_CARD_4BIT_HI 7
|
#define LOW_SPEED_CARD_4BIT_SZ 1
|
#define COMMON_CIS_PONTER_MSK 0x01ffff00
|
#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
|
#define COMMON_CIS_PONTER_SFT 8
|
#define COMMON_CIS_PONTER_HI 24
|
#define COMMON_CIS_PONTER_SZ 17
|
#define SUPPORT_HIGH_SPEED_MSK 0x01000000
|
#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
|
#define SUPPORT_HIGH_SPEED_SFT 24
|
#define SUPPORT_HIGH_SPEED_HI 24
|
#define SUPPORT_HIGH_SPEED_SZ 1
|
#define BSS_MSK 0x0e000000
|
#define BSS_I_MSK 0xf1ffffff
|
#define BSS_SFT 25
|
#define BSS_HI 27
|
#define BSS_SZ 3
|
#define FBR_100H_REG_MSK 0x0000000f
|
#define FBR_100H_REG_I_MSK 0xfffffff0
|
#define FBR_100H_REG_SFT 0
|
#define FBR_100H_REG_HI 3
|
#define FBR_100H_REG_SZ 4
|
#define CSASUPPORT_MSK 0x00000040
|
#define CSASUPPORT_I_MSK 0xffffffbf
|
#define CSASUPPORT_SFT 6
|
#define CSASUPPORT_HI 6
|
#define CSASUPPORT_SZ 1
|
#define ENABLECSA_MSK 0x00000080
|
#define ENABLECSA_I_MSK 0xffffff7f
|
#define ENABLECSA_SFT 7
|
#define ENABLECSA_HI 7
|
#define ENABLECSA_SZ 1
|
#define FBR_101H_REG_MSK 0x0000ff00
|
#define FBR_101H_REG_I_MSK 0xffff00ff
|
#define FBR_101H_REG_SFT 8
|
#define FBR_101H_REG_HI 15
|
#define FBR_101H_REG_SZ 8
|
#define FBR_109H_REG_MSK 0x01ffff00
|
#define FBR_109H_REG_I_MSK 0xfe0000ff
|
#define FBR_109H_REG_SFT 8
|
#define FBR_109H_REG_HI 24
|
#define FBR_109H_REG_SZ 17
|
#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_31_0_SFT 0
|
#define F0_CIS_CONTENT_REG_31_0_HI 31
|
#define F0_CIS_CONTENT_REG_31_0_SZ 32
|
#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_63_32_SFT 0
|
#define F0_CIS_CONTENT_REG_63_32_HI 31
|
#define F0_CIS_CONTENT_REG_63_32_SZ 32
|
#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_95_64_SFT 0
|
#define F0_CIS_CONTENT_REG_95_64_HI 31
|
#define F0_CIS_CONTENT_REG_95_64_SZ 32
|
#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_127_96_SFT 0
|
#define F0_CIS_CONTENT_REG_127_96_HI 31
|
#define F0_CIS_CONTENT_REG_127_96_SZ 32
|
#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_159_128_SFT 0
|
#define F0_CIS_CONTENT_REG_159_128_HI 31
|
#define F0_CIS_CONTENT_REG_159_128_SZ 32
|
#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_191_160_SFT 0
|
#define F0_CIS_CONTENT_REG_191_160_HI 31
|
#define F0_CIS_CONTENT_REG_191_160_SZ 32
|
#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_223_192_SFT 0
|
#define F0_CIS_CONTENT_REG_223_192_HI 31
|
#define F0_CIS_CONTENT_REG_223_192_SZ 32
|
#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_255_224_SFT 0
|
#define F0_CIS_CONTENT_REG_255_224_HI 31
|
#define F0_CIS_CONTENT_REG_255_224_SZ 32
|
#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_287_256_SFT 0
|
#define F0_CIS_CONTENT_REG_287_256_HI 31
|
#define F0_CIS_CONTENT_REG_287_256_SZ 32
|
#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_319_288_SFT 0
|
#define F0_CIS_CONTENT_REG_319_288_HI 31
|
#define F0_CIS_CONTENT_REG_319_288_SZ 32
|
#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_351_320_SFT 0
|
#define F0_CIS_CONTENT_REG_351_320_HI 31
|
#define F0_CIS_CONTENT_REG_351_320_SZ 32
|
#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_383_352_SFT 0
|
#define F0_CIS_CONTENT_REG_383_352_HI 31
|
#define F0_CIS_CONTENT_REG_383_352_SZ 32
|
#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_415_384_SFT 0
|
#define F0_CIS_CONTENT_REG_415_384_HI 31
|
#define F0_CIS_CONTENT_REG_415_384_SZ 32
|
#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_447_416_SFT 0
|
#define F0_CIS_CONTENT_REG_447_416_HI 31
|
#define F0_CIS_CONTENT_REG_447_416_SZ 32
|
#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_479_448_SFT 0
|
#define F0_CIS_CONTENT_REG_479_448_HI 31
|
#define F0_CIS_CONTENT_REG_479_448_SZ 32
|
#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
|
#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
|
#define F0_CIS_CONTENT_REG_511_480_SFT 0
|
#define F0_CIS_CONTENT_REG_511_480_HI 31
|
#define F0_CIS_CONTENT_REG_511_480_SZ 32
|
#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_31_0_SFT 0
|
#define F1_CIS_CONTENT_REG_31_0_HI 31
|
#define F1_CIS_CONTENT_REG_31_0_SZ 32
|
#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_63_32_SFT 0
|
#define F1_CIS_CONTENT_REG_63_32_HI 31
|
#define F1_CIS_CONTENT_REG_63_32_SZ 32
|
#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_95_64_SFT 0
|
#define F1_CIS_CONTENT_REG_95_64_HI 31
|
#define F1_CIS_CONTENT_REG_95_64_SZ 32
|
#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_127_96_SFT 0
|
#define F1_CIS_CONTENT_REG_127_96_HI 31
|
#define F1_CIS_CONTENT_REG_127_96_SZ 32
|
#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_159_128_SFT 0
|
#define F1_CIS_CONTENT_REG_159_128_HI 31
|
#define F1_CIS_CONTENT_REG_159_128_SZ 32
|
#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_191_160_SFT 0
|
#define F1_CIS_CONTENT_REG_191_160_HI 31
|
#define F1_CIS_CONTENT_REG_191_160_SZ 32
|
#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_223_192_SFT 0
|
#define F1_CIS_CONTENT_REG_223_192_HI 31
|
#define F1_CIS_CONTENT_REG_223_192_SZ 32
|
#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_255_224_SFT 0
|
#define F1_CIS_CONTENT_REG_255_224_HI 31
|
#define F1_CIS_CONTENT_REG_255_224_SZ 32
|
#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_287_256_SFT 0
|
#define F1_CIS_CONTENT_REG_287_256_HI 31
|
#define F1_CIS_CONTENT_REG_287_256_SZ 32
|
#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_319_288_SFT 0
|
#define F1_CIS_CONTENT_REG_319_288_HI 31
|
#define F1_CIS_CONTENT_REG_319_288_SZ 32
|
#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_351_320_SFT 0
|
#define F1_CIS_CONTENT_REG_351_320_HI 31
|
#define F1_CIS_CONTENT_REG_351_320_SZ 32
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#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_383_352_SFT 0
|
#define F1_CIS_CONTENT_REG_383_352_HI 31
|
#define F1_CIS_CONTENT_REG_383_352_SZ 32
|
#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_415_384_SFT 0
|
#define F1_CIS_CONTENT_REG_415_384_HI 31
|
#define F1_CIS_CONTENT_REG_415_384_SZ 32
|
#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_447_416_SFT 0
|
#define F1_CIS_CONTENT_REG_447_416_HI 31
|
#define F1_CIS_CONTENT_REG_447_416_SZ 32
|
#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_479_448_SFT 0
|
#define F1_CIS_CONTENT_REG_479_448_HI 31
|
#define F1_CIS_CONTENT_REG_479_448_SZ 32
|
#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
|
#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
|
#define F1_CIS_CONTENT_REG_511_480_SFT 0
|
#define F1_CIS_CONTENT_REG_511_480_HI 31
|
#define F1_CIS_CONTENT_REG_511_480_SZ 32
|
#define SPI_MODE_MSK 0xffffffff
|
#define SPI_MODE_I_MSK 0x00000000
|
#define SPI_MODE_SFT 0
|
#define SPI_MODE_HI 31
|
#define SPI_MODE_SZ 32
|
#define RX_QUOTA_MSK 0x0000ffff
|
#define RX_QUOTA_I_MSK 0xffff0000
|
#define RX_QUOTA_SFT 0
|
#define RX_QUOTA_HI 15
|
#define RX_QUOTA_SZ 16
|
#define CONDI_NUM_MSK 0x000000ff
|
#define CONDI_NUM_I_MSK 0xffffff00
|
#define CONDI_NUM_SFT 0
|
#define CONDI_NUM_HI 7
|
#define CONDI_NUM_SZ 8
|
#define HOST_PATH_MSK 0x00000001
|
#define HOST_PATH_I_MSK 0xfffffffe
|
#define HOST_PATH_SFT 0
|
#define HOST_PATH_HI 0
|
#define HOST_PATH_SZ 1
|
#define TX_SEG_MSK 0xffffffff
|
#define TX_SEG_I_MSK 0x00000000
|
#define TX_SEG_SFT 0
|
#define TX_SEG_HI 31
|
#define TX_SEG_SZ 32
|
#define BRST_MODE_MSK 0x00000001
|
#define BRST_MODE_I_MSK 0xfffffffe
|
#define BRST_MODE_SFT 0
|
#define BRST_MODE_HI 0
|
#define BRST_MODE_SZ 1
|
#define CLK_WIDTH_MSK 0x0000ffff
|
#define CLK_WIDTH_I_MSK 0xffff0000
|
#define CLK_WIDTH_SFT 0
|
#define CLK_WIDTH_HI 15
|
#define CLK_WIDTH_SZ 16
|
#define CSN_INTER_MSK 0xffff0000
|
#define CSN_INTER_I_MSK 0x0000ffff
|
#define CSN_INTER_SFT 16
|
#define CSN_INTER_HI 31
|
#define CSN_INTER_SZ 16
|
#define BACK_DLY_MSK 0x0000ffff
|
#define BACK_DLY_I_MSK 0xffff0000
|
#define BACK_DLY_SFT 0
|
#define BACK_DLY_HI 15
|
#define BACK_DLY_SZ 16
|
#define FRONT_DLY_MSK 0xffff0000
|
#define FRONT_DLY_I_MSK 0x0000ffff
|
#define FRONT_DLY_SFT 16
|
#define FRONT_DLY_HI 31
|
#define FRONT_DLY_SZ 16
|
#define RX_FIFO_FAIL_MSK 0x00000002
|
#define RX_FIFO_FAIL_I_MSK 0xfffffffd
|
#define RX_FIFO_FAIL_SFT 1
|
#define RX_FIFO_FAIL_HI 1
|
#define RX_FIFO_FAIL_SZ 1
|
#define RX_HOST_FAIL_MSK 0x00000004
|
#define RX_HOST_FAIL_I_MSK 0xfffffffb
|
#define RX_HOST_FAIL_SFT 2
|
#define RX_HOST_FAIL_HI 2
|
#define RX_HOST_FAIL_SZ 1
|
#define TX_FIFO_FAIL_MSK 0x00000008
|
#define TX_FIFO_FAIL_I_MSK 0xfffffff7
|
#define TX_FIFO_FAIL_SFT 3
|
#define TX_FIFO_FAIL_HI 3
|
#define TX_FIFO_FAIL_SZ 1
|
#define TX_HOST_FAIL_MSK 0x00000010
|
#define TX_HOST_FAIL_I_MSK 0xffffffef
|
#define TX_HOST_FAIL_SFT 4
|
#define TX_HOST_FAIL_HI 4
|
#define TX_HOST_FAIL_SZ 1
|
#define SPI_DOUBLE_ALLOC_MSK 0x00000020
|
#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
|
#define SPI_DOUBLE_ALLOC_SFT 5
|
#define SPI_DOUBLE_ALLOC_HI 5
|
#define SPI_DOUBLE_ALLOC_SZ 1
|
#define SPI_TX_NO_ALLOC_MSK 0x00000040
|
#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
|
#define SPI_TX_NO_ALLOC_SFT 6
|
#define SPI_TX_NO_ALLOC_HI 6
|
#define SPI_TX_NO_ALLOC_SZ 1
|
#define RDATA_RDY_MSK 0x00000080
|
#define RDATA_RDY_I_MSK 0xffffff7f
|
#define RDATA_RDY_SFT 7
|
#define RDATA_RDY_HI 7
|
#define RDATA_RDY_SZ 1
|
#define SPI_ALLOC_STATUS_MSK 0x00000100
|
#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
|
#define SPI_ALLOC_STATUS_SFT 8
|
#define SPI_ALLOC_STATUS_HI 8
|
#define SPI_ALLOC_STATUS_SZ 1
|
#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
|
#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
|
#define SPI_DBG_WR_FIFO_FULL_SFT 9
|
#define SPI_DBG_WR_FIFO_FULL_HI 9
|
#define SPI_DBG_WR_FIFO_FULL_SZ 1
|
#define RX_LEN_MSK 0xffff0000
|
#define RX_LEN_I_MSK 0x0000ffff
|
#define RX_LEN_SFT 16
|
#define RX_LEN_HI 31
|
#define RX_LEN_SZ 16
|
#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
|
#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
|
#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
|
#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
|
#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
|
#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
|
#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
|
#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
|
#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
|
#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
|
#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
|
#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
|
#define SPI_TX_ALLOC_SIZE_SFT 0
|
#define SPI_TX_ALLOC_SIZE_HI 7
|
#define SPI_TX_ALLOC_SIZE_SZ 8
|
#define RD_DAT_CNT_MSK 0x0000ffff
|
#define RD_DAT_CNT_I_MSK 0xffff0000
|
#define RD_DAT_CNT_SFT 0
|
#define RD_DAT_CNT_HI 15
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#define RD_DAT_CNT_SZ 16
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#define RD_STS_CNT_MSK 0xffff0000
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#define RD_STS_CNT_I_MSK 0x0000ffff
|
#define RD_STS_CNT_SFT 16
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#define RD_STS_CNT_HI 31
|
#define RD_STS_CNT_SZ 16
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#define JUDGE_CNT_MSK 0x0000ffff
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#define JUDGE_CNT_I_MSK 0xffff0000
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#define JUDGE_CNT_SFT 0
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#define JUDGE_CNT_HI 15
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#define JUDGE_CNT_SZ 16
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#define RD_STS_CNT_CLR_MSK 0x00010000
|
#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
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#define RD_STS_CNT_CLR_SFT 16
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#define RD_STS_CNT_CLR_HI 16
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#define RD_STS_CNT_CLR_SZ 1
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#define RD_DAT_CNT_CLR_MSK 0x00020000
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#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
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#define RD_DAT_CNT_CLR_SFT 17
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#define RD_DAT_CNT_CLR_HI 17
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#define RD_DAT_CNT_CLR_SZ 1
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#define JUDGE_CNT_CLR_MSK 0x00040000
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#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
|
#define JUDGE_CNT_CLR_SFT 18
|
#define JUDGE_CNT_CLR_HI 18
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#define JUDGE_CNT_CLR_SZ 1
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#define TX_DONE_CNT_MSK 0x0000ffff
|
#define TX_DONE_CNT_I_MSK 0xffff0000
|
#define TX_DONE_CNT_SFT 0
|
#define TX_DONE_CNT_HI 15
|
#define TX_DONE_CNT_SZ 16
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#define TX_DISCARD_CNT_MSK 0xffff0000
|
#define TX_DISCARD_CNT_I_MSK 0x0000ffff
|
#define TX_DISCARD_CNT_SFT 16
|
#define TX_DISCARD_CNT_HI 31
|
#define TX_DISCARD_CNT_SZ 16
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#define TX_SET_CNT_MSK 0x0000ffff
|
#define TX_SET_CNT_I_MSK 0xffff0000
|
#define TX_SET_CNT_SFT 0
|
#define TX_SET_CNT_HI 15
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#define TX_SET_CNT_SZ 16
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#define TX_DISCARD_CNT_CLR_MSK 0x00010000
|
#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
|
#define TX_DISCARD_CNT_CLR_SFT 16
|
#define TX_DISCARD_CNT_CLR_HI 16
|
#define TX_DISCARD_CNT_CLR_SZ 1
|
#define TX_DONE_CNT_CLR_MSK 0x00020000
|
#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
|
#define TX_DONE_CNT_CLR_SFT 17
|
#define TX_DONE_CNT_CLR_HI 17
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#define TX_DONE_CNT_CLR_SZ 1
|
#define TX_SET_CNT_CLR_MSK 0x00040000
|
#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
|
#define TX_SET_CNT_CLR_SFT 18
|
#define TX_SET_CNT_CLR_HI 18
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#define TX_SET_CNT_CLR_SZ 1
|
#define DAT_MODE_OFF_MSK 0x00080000
|
#define DAT_MODE_OFF_I_MSK 0xfff7ffff
|
#define DAT_MODE_OFF_SFT 19
|
#define DAT_MODE_OFF_HI 19
|
#define DAT_MODE_OFF_SZ 1
|
#define TX_FIFO_RESIDUE_MSK 0x00700000
|
#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
|
#define TX_FIFO_RESIDUE_SFT 20
|
#define TX_FIFO_RESIDUE_HI 22
|
#define TX_FIFO_RESIDUE_SZ 3
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#define RX_FIFO_RESIDUE_MSK 0x07000000
|
#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
|
#define RX_FIFO_RESIDUE_SFT 24
|
#define RX_FIFO_RESIDUE_HI 26
|
#define RX_FIFO_RESIDUE_SZ 3
|
#define RX_RDY_MSK 0x00000001
|
#define RX_RDY_I_MSK 0xfffffffe
|
#define RX_RDY_SFT 0
|
#define RX_RDY_HI 0
|
#define RX_RDY_SZ 1
|
#define SDIO_SYS_INT_MSK 0x00000004
|
#define SDIO_SYS_INT_I_MSK 0xfffffffb
|
#define SDIO_SYS_INT_SFT 2
|
#define SDIO_SYS_INT_HI 2
|
#define SDIO_SYS_INT_SZ 1
|
#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
|
#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
|
#define EDCA0_LOWTHOLD_INT_SFT 3
|
#define EDCA0_LOWTHOLD_INT_HI 3
|
#define EDCA0_LOWTHOLD_INT_SZ 1
|
#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
|
#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
|
#define EDCA1_LOWTHOLD_INT_SFT 4
|
#define EDCA1_LOWTHOLD_INT_HI 4
|
#define EDCA1_LOWTHOLD_INT_SZ 1
|
#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
|
#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
|
#define EDCA2_LOWTHOLD_INT_SFT 5
|
#define EDCA2_LOWTHOLD_INT_HI 5
|
#define EDCA2_LOWTHOLD_INT_SZ 1
|
#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
|
#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
|
#define EDCA3_LOWTHOLD_INT_SFT 6
|
#define EDCA3_LOWTHOLD_INT_HI 6
|
#define EDCA3_LOWTHOLD_INT_SZ 1
|
#define TX_LIMIT_INT_IN_MSK 0x00000080
|
#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
|
#define TX_LIMIT_INT_IN_SFT 7
|
#define TX_LIMIT_INT_IN_HI 7
|
#define TX_LIMIT_INT_IN_SZ 1
|
#define SPI_FN1_MSK 0x00007f00
|
#define SPI_FN1_I_MSK 0xffff80ff
|
#define SPI_FN1_SFT 8
|
#define SPI_FN1_HI 14
|
#define SPI_FN1_SZ 7
|
#define SPI_CLK_EN_INT_MSK 0x00008000
|
#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
|
#define SPI_CLK_EN_INT_SFT 15
|
#define SPI_CLK_EN_INT_HI 15
|
#define SPI_CLK_EN_INT_SZ 1
|
#define SPI_HOST_MASK_MSK 0x00ff0000
|
#define SPI_HOST_MASK_I_MSK 0xff00ffff
|
#define SPI_HOST_MASK_SFT 16
|
#define SPI_HOST_MASK_HI 23
|
#define SPI_HOST_MASK_SZ 8
|
#define I2CM_INT_WDONE_MSK 0x00000001
|
#define I2CM_INT_WDONE_I_MSK 0xfffffffe
|
#define I2CM_INT_WDONE_SFT 0
|
#define I2CM_INT_WDONE_HI 0
|
#define I2CM_INT_WDONE_SZ 1
|
#define I2CM_INT_RDONE_MSK 0x00000002
|
#define I2CM_INT_RDONE_I_MSK 0xfffffffd
|
#define I2CM_INT_RDONE_SFT 1
|
#define I2CM_INT_RDONE_HI 1
|
#define I2CM_INT_RDONE_SZ 1
|
#define I2CM_IDLE_MSK 0x00000004
|
#define I2CM_IDLE_I_MSK 0xfffffffb
|
#define I2CM_IDLE_SFT 2
|
#define I2CM_IDLE_HI 2
|
#define I2CM_IDLE_SZ 1
|
#define I2CM_INT_MISMATCH_MSK 0x00000008
|
#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
|
#define I2CM_INT_MISMATCH_SFT 3
|
#define I2CM_INT_MISMATCH_HI 3
|
#define I2CM_INT_MISMATCH_SZ 1
|
#define I2CM_PSCL_MSK 0x00003ff0
|
#define I2CM_PSCL_I_MSK 0xffffc00f
|
#define I2CM_PSCL_SFT 4
|
#define I2CM_PSCL_HI 13
|
#define I2CM_PSCL_SZ 10
|
#define I2CM_MANUAL_MODE_MSK 0x00010000
|
#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
|
#define I2CM_MANUAL_MODE_SFT 16
|
#define I2CM_MANUAL_MODE_HI 16
|
#define I2CM_MANUAL_MODE_SZ 1
|
#define I2CM_INT_WDATA_NEED_MSK 0x00020000
|
#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
|
#define I2CM_INT_WDATA_NEED_SFT 17
|
#define I2CM_INT_WDATA_NEED_HI 17
|
#define I2CM_INT_WDATA_NEED_SZ 1
|
#define I2CM_INT_RDATA_NEED_MSK 0x00040000
|
#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
|
#define I2CM_INT_RDATA_NEED_SFT 18
|
#define I2CM_INT_RDATA_NEED_HI 18
|
#define I2CM_INT_RDATA_NEED_SZ 1
|
#define I2CM_DEV_A_MSK 0x000003ff
|
#define I2CM_DEV_A_I_MSK 0xfffffc00
|
#define I2CM_DEV_A_SFT 0
|
#define I2CM_DEV_A_HI 9
|
#define I2CM_DEV_A_SZ 10
|
#define I2CM_DEV_A10B_MSK 0x00004000
|
#define I2CM_DEV_A10B_I_MSK 0xffffbfff
|
#define I2CM_DEV_A10B_SFT 14
|
#define I2CM_DEV_A10B_HI 14
|
#define I2CM_DEV_A10B_SZ 1
|
#define I2CM_RX_MSK 0x00008000
|
#define I2CM_RX_I_MSK 0xffff7fff
|
#define I2CM_RX_SFT 15
|
#define I2CM_RX_HI 15
|
#define I2CM_RX_SZ 1
|
#define I2CM_LEN_MSK 0x0000ffff
|
#define I2CM_LEN_I_MSK 0xffff0000
|
#define I2CM_LEN_SFT 0
|
#define I2CM_LEN_HI 15
|
#define I2CM_LEN_SZ 16
|
#define I2CM_T_LEFT_MSK 0x00070000
|
#define I2CM_T_LEFT_I_MSK 0xfff8ffff
|
#define I2CM_T_LEFT_SFT 16
|
#define I2CM_T_LEFT_HI 18
|
#define I2CM_T_LEFT_SZ 3
|
#define I2CM_R_GET_MSK 0x07000000
|
#define I2CM_R_GET_I_MSK 0xf8ffffff
|
#define I2CM_R_GET_SFT 24
|
#define I2CM_R_GET_HI 26
|
#define I2CM_R_GET_SZ 3
|
#define I2CM_WDAT_MSK 0xffffffff
|
#define I2CM_WDAT_I_MSK 0x00000000
|
#define I2CM_WDAT_SFT 0
|
#define I2CM_WDAT_HI 31
|
#define I2CM_WDAT_SZ 32
|
#define I2CM_RDAT_MSK 0xffffffff
|
#define I2CM_RDAT_I_MSK 0x00000000
|
#define I2CM_RDAT_SFT 0
|
#define I2CM_RDAT_HI 31
|
#define I2CM_RDAT_SZ 32
|
#define I2CM_SR_LEN_MSK 0x0000ffff
|
#define I2CM_SR_LEN_I_MSK 0xffff0000
|
#define I2CM_SR_LEN_SFT 0
|
#define I2CM_SR_LEN_HI 15
|
#define I2CM_SR_LEN_SZ 16
|
#define I2CM_SR_RX_MSK 0x00010000
|
#define I2CM_SR_RX_I_MSK 0xfffeffff
|
#define I2CM_SR_RX_SFT 16
|
#define I2CM_SR_RX_HI 16
|
#define I2CM_SR_RX_SZ 1
|
#define I2CM_REPEAT_START_MSK 0x00020000
|
#define I2CM_REPEAT_START_I_MSK 0xfffdffff
|
#define I2CM_REPEAT_START_SFT 17
|
#define I2CM_REPEAT_START_HI 17
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#define I2CM_REPEAT_START_SZ 1
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#define UART_DATA_MSK 0x000000ff
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#define UART_DATA_I_MSK 0xffffff00
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#define UART_DATA_SFT 0
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#define UART_DATA_HI 7
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#define UART_DATA_SZ 8
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#define DATA_RDY_IE_MSK 0x00000001
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#define DATA_RDY_IE_I_MSK 0xfffffffe
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#define DATA_RDY_IE_SFT 0
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#define DATA_RDY_IE_HI 0
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#define DATA_RDY_IE_SZ 1
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#define THR_EMPTY_IE_MSK 0x00000002
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#define THR_EMPTY_IE_I_MSK 0xfffffffd
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#define THR_EMPTY_IE_SFT 1
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#define THR_EMPTY_IE_HI 1
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#define THR_EMPTY_IE_SZ 1
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#define RX_LINESTS_IE_MSK 0x00000004
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#define RX_LINESTS_IE_I_MSK 0xfffffffb
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#define RX_LINESTS_IE_SFT 2
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#define RX_LINESTS_IE_HI 2
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#define RX_LINESTS_IE_SZ 1
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#define MDM_STS_IE_MSK 0x00000008
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#define MDM_STS_IE_I_MSK 0xfffffff7
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#define MDM_STS_IE_SFT 3
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#define MDM_STS_IE_HI 3
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#define MDM_STS_IE_SZ 1
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#define DMA_RXEND_IE_MSK 0x00000040
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#define DMA_RXEND_IE_I_MSK 0xffffffbf
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#define DMA_RXEND_IE_SFT 6
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#define DMA_RXEND_IE_HI 6
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#define DMA_RXEND_IE_SZ 1
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#define DMA_TXEND_IE_MSK 0x00000080
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#define DMA_TXEND_IE_I_MSK 0xffffff7f
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#define DMA_TXEND_IE_SFT 7
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#define DMA_TXEND_IE_HI 7
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#define DMA_TXEND_IE_SZ 1
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#define FIFO_EN_MSK 0x00000001
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#define FIFO_EN_I_MSK 0xfffffffe
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#define FIFO_EN_SFT 0
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#define FIFO_EN_HI 0
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#define FIFO_EN_SZ 1
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#define RXFIFO_RST_MSK 0x00000002
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#define RXFIFO_RST_I_MSK 0xfffffffd
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#define RXFIFO_RST_SFT 1
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#define RXFIFO_RST_HI 1
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#define RXFIFO_RST_SZ 1
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#define TXFIFO_RST_MSK 0x00000004
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#define TXFIFO_RST_I_MSK 0xfffffffb
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#define TXFIFO_RST_SFT 2
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#define TXFIFO_RST_HI 2
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#define TXFIFO_RST_SZ 1
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#define DMA_MODE_MSK 0x00000008
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#define DMA_MODE_I_MSK 0xfffffff7
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#define DMA_MODE_SFT 3
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#define DMA_MODE_HI 3
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#define DMA_MODE_SZ 1
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#define EN_AUTO_RTS_MSK 0x00000010
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#define EN_AUTO_RTS_I_MSK 0xffffffef
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#define EN_AUTO_RTS_SFT 4
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#define EN_AUTO_RTS_HI 4
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#define EN_AUTO_RTS_SZ 1
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#define EN_AUTO_CTS_MSK 0x00000020
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#define EN_AUTO_CTS_I_MSK 0xffffffdf
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#define EN_AUTO_CTS_SFT 5
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#define EN_AUTO_CTS_HI 5
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#define EN_AUTO_CTS_SZ 1
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#define RXFIFO_TRGLVL_MSK 0x000000c0
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#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
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#define RXFIFO_TRGLVL_SFT 6
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#define RXFIFO_TRGLVL_HI 7
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#define RXFIFO_TRGLVL_SZ 2
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#define WORD_LEN_MSK 0x00000003
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#define WORD_LEN_I_MSK 0xfffffffc
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#define WORD_LEN_SFT 0
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#define WORD_LEN_HI 1
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#define WORD_LEN_SZ 2
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#define STOP_BIT_MSK 0x00000004
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#define STOP_BIT_I_MSK 0xfffffffb
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#define STOP_BIT_SFT 2
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#define STOP_BIT_HI 2
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#define STOP_BIT_SZ 1
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#define PARITY_EN_MSK 0x00000008
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#define PARITY_EN_I_MSK 0xfffffff7
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#define PARITY_EN_SFT 3
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#define PARITY_EN_HI 3
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#define PARITY_EN_SZ 1
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#define EVEN_PARITY_MSK 0x00000010
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#define EVEN_PARITY_I_MSK 0xffffffef
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#define EVEN_PARITY_SFT 4
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#define EVEN_PARITY_HI 4
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#define EVEN_PARITY_SZ 1
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#define FORCE_PARITY_MSK 0x00000020
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#define FORCE_PARITY_I_MSK 0xffffffdf
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#define FORCE_PARITY_SFT 5
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#define FORCE_PARITY_HI 5
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#define FORCE_PARITY_SZ 1
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#define SET_BREAK_MSK 0x00000040
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#define SET_BREAK_I_MSK 0xffffffbf
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#define SET_BREAK_SFT 6
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#define SET_BREAK_HI 6
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#define SET_BREAK_SZ 1
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#define DLAB_MSK 0x00000080
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#define DLAB_I_MSK 0xffffff7f
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#define DLAB_SFT 7
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#define DLAB_HI 7
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#define DLAB_SZ 1
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#define DTR_MSK 0x00000001
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#define DTR_I_MSK 0xfffffffe
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#define DTR_SFT 0
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#define DTR_HI 0
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#define DTR_SZ 1
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#define RTS_MSK 0x00000002
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#define RTS_I_MSK 0xfffffffd
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#define RTS_SFT 1
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#define RTS_HI 1
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#define RTS_SZ 1
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#define OUT_1_MSK 0x00000004
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#define OUT_1_I_MSK 0xfffffffb
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#define OUT_1_SFT 2
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#define OUT_1_HI 2
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#define OUT_1_SZ 1
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#define OUT_2_MSK 0x00000008
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#define OUT_2_I_MSK 0xfffffff7
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#define OUT_2_SFT 3
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#define OUT_2_HI 3
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#define OUT_2_SZ 1
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#define LOOP_BACK_MSK 0x00000010
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#define LOOP_BACK_I_MSK 0xffffffef
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#define LOOP_BACK_SFT 4
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#define LOOP_BACK_HI 4
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#define LOOP_BACK_SZ 1
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#define DATA_RDY_MSK 0x00000001
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#define DATA_RDY_I_MSK 0xfffffffe
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#define DATA_RDY_SFT 0
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#define DATA_RDY_HI 0
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#define DATA_RDY_SZ 1
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#define OVERRUN_ERR_MSK 0x00000002
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#define OVERRUN_ERR_I_MSK 0xfffffffd
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#define OVERRUN_ERR_SFT 1
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#define OVERRUN_ERR_HI 1
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#define OVERRUN_ERR_SZ 1
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#define PARITY_ERR_MSK 0x00000004
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#define PARITY_ERR_I_MSK 0xfffffffb
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#define PARITY_ERR_SFT 2
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#define PARITY_ERR_HI 2
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#define PARITY_ERR_SZ 1
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#define FRAMING_ERR_MSK 0x00000008
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#define FRAMING_ERR_I_MSK 0xfffffff7
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#define FRAMING_ERR_SFT 3
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#define FRAMING_ERR_HI 3
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#define FRAMING_ERR_SZ 1
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#define BREAK_INT_MSK 0x00000010
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#define BREAK_INT_I_MSK 0xffffffef
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#define BREAK_INT_SFT 4
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#define BREAK_INT_HI 4
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#define BREAK_INT_SZ 1
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#define THR_EMPTY_MSK 0x00000020
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#define THR_EMPTY_I_MSK 0xffffffdf
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#define THR_EMPTY_SFT 5
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#define THR_EMPTY_HI 5
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#define THR_EMPTY_SZ 1
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#define TX_EMPTY_MSK 0x00000040
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#define TX_EMPTY_I_MSK 0xffffffbf
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#define TX_EMPTY_SFT 6
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#define TX_EMPTY_HI 6
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#define TX_EMPTY_SZ 1
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#define FIFODATA_ERR_MSK 0x00000080
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#define FIFODATA_ERR_I_MSK 0xffffff7f
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#define FIFODATA_ERR_SFT 7
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#define FIFODATA_ERR_HI 7
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#define FIFODATA_ERR_SZ 1
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#define DELTA_CTS_MSK 0x00000001
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#define DELTA_CTS_I_MSK 0xfffffffe
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#define DELTA_CTS_SFT 0
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#define DELTA_CTS_HI 0
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#define DELTA_CTS_SZ 1
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#define DELTA_DSR_MSK 0x00000002
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#define DELTA_DSR_I_MSK 0xfffffffd
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#define DELTA_DSR_SFT 1
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#define DELTA_DSR_HI 1
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#define DELTA_DSR_SZ 1
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#define TRAILEDGE_RI_MSK 0x00000004
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#define TRAILEDGE_RI_I_MSK 0xfffffffb
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#define TRAILEDGE_RI_SFT 2
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#define TRAILEDGE_RI_HI 2
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#define TRAILEDGE_RI_SZ 1
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#define DELTA_CD_MSK 0x00000008
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#define DELTA_CD_I_MSK 0xfffffff7
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#define DELTA_CD_SFT 3
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#define DELTA_CD_HI 3
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#define DELTA_CD_SZ 1
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#define CTS_MSK 0x00000010
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#define CTS_I_MSK 0xffffffef
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#define CTS_SFT 4
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#define CTS_HI 4
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#define CTS_SZ 1
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#define DSR_MSK 0x00000020
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#define DSR_I_MSK 0xffffffdf
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#define DSR_SFT 5
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#define DSR_HI 5
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#define DSR_SZ 1
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#define RI_MSK 0x00000040
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#define RI_I_MSK 0xffffffbf
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#define RI_SFT 6
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#define RI_HI 6
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#define RI_SZ 1
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#define CD_MSK 0x00000080
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#define CD_I_MSK 0xffffff7f
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#define CD_SFT 7
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#define CD_HI 7
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#define CD_SZ 1
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#define BRDC_DIV_MSK 0x0000ffff
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#define BRDC_DIV_I_MSK 0xffff0000
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#define BRDC_DIV_SFT 0
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#define BRDC_DIV_HI 15
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#define BRDC_DIV_SZ 16
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#define RTHR_L_MSK 0x0000000f
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#define RTHR_L_I_MSK 0xfffffff0
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#define RTHR_L_SFT 0
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#define RTHR_L_HI 3
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#define RTHR_L_SZ 4
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#define RTHR_H_MSK 0x000000f0
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#define RTHR_H_I_MSK 0xffffff0f
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#define RTHR_H_SFT 4
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#define RTHR_H_HI 7
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#define RTHR_H_SZ 4
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#define INT_IDCODE_MSK 0x0000000f
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#define INT_IDCODE_I_MSK 0xfffffff0
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#define INT_IDCODE_SFT 0
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#define INT_IDCODE_HI 3
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#define INT_IDCODE_SZ 4
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#define FIFOS_ENABLED_MSK 0x000000c0
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#define FIFOS_ENABLED_I_MSK 0xffffff3f
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#define FIFOS_ENABLED_SFT 6
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#define FIFOS_ENABLED_HI 7
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#define FIFOS_ENABLED_SZ 2
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#define DAT_UART_DATA_MSK 0x000000ff
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#define DAT_UART_DATA_I_MSK 0xffffff00
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#define DAT_UART_DATA_SFT 0
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#define DAT_UART_DATA_HI 7
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#define DAT_UART_DATA_SZ 8
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#define DAT_DATA_RDY_IE_MSK 0x00000001
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#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
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#define DAT_DATA_RDY_IE_SFT 0
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#define DAT_DATA_RDY_IE_HI 0
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#define DAT_DATA_RDY_IE_SZ 1
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#define DAT_THR_EMPTY_IE_MSK 0x00000002
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#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
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#define DAT_THR_EMPTY_IE_SFT 1
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#define DAT_THR_EMPTY_IE_HI 1
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#define DAT_THR_EMPTY_IE_SZ 1
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#define DAT_RX_LINESTS_IE_MSK 0x00000004
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#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
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#define DAT_RX_LINESTS_IE_SFT 2
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#define DAT_RX_LINESTS_IE_HI 2
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#define DAT_RX_LINESTS_IE_SZ 1
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#define DAT_MDM_STS_IE_MSK 0x00000008
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#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
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#define DAT_MDM_STS_IE_SFT 3
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#define DAT_MDM_STS_IE_HI 3
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#define DAT_MDM_STS_IE_SZ 1
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#define DAT_DMA_RXEND_IE_MSK 0x00000040
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#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
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#define DAT_DMA_RXEND_IE_SFT 6
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#define DAT_DMA_RXEND_IE_HI 6
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#define DAT_DMA_RXEND_IE_SZ 1
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#define DAT_DMA_TXEND_IE_MSK 0x00000080
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#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
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#define DAT_DMA_TXEND_IE_SFT 7
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#define DAT_DMA_TXEND_IE_HI 7
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#define DAT_DMA_TXEND_IE_SZ 1
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#define DAT_FIFO_EN_MSK 0x00000001
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#define DAT_FIFO_EN_I_MSK 0xfffffffe
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#define DAT_FIFO_EN_SFT 0
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#define DAT_FIFO_EN_HI 0
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#define DAT_FIFO_EN_SZ 1
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#define DAT_RXFIFO_RST_MSK 0x00000002
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#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
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#define DAT_RXFIFO_RST_SFT 1
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#define DAT_RXFIFO_RST_HI 1
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#define DAT_RXFIFO_RST_SZ 1
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#define DAT_TXFIFO_RST_MSK 0x00000004
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#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
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#define DAT_TXFIFO_RST_SFT 2
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#define DAT_TXFIFO_RST_HI 2
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#define DAT_TXFIFO_RST_SZ 1
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#define DAT_DMA_MODE_MSK 0x00000008
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#define DAT_DMA_MODE_I_MSK 0xfffffff7
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#define DAT_DMA_MODE_SFT 3
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#define DAT_DMA_MODE_HI 3
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#define DAT_DMA_MODE_SZ 1
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#define DAT_EN_AUTO_RTS_MSK 0x00000010
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#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
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#define DAT_EN_AUTO_RTS_SFT 4
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#define DAT_EN_AUTO_RTS_HI 4
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#define DAT_EN_AUTO_RTS_SZ 1
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#define DAT_EN_AUTO_CTS_MSK 0x00000020
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#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
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#define DAT_EN_AUTO_CTS_SFT 5
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#define DAT_EN_AUTO_CTS_HI 5
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#define DAT_EN_AUTO_CTS_SZ 1
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#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
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#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
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#define DAT_RXFIFO_TRGLVL_SFT 6
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#define DAT_RXFIFO_TRGLVL_HI 7
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#define DAT_RXFIFO_TRGLVL_SZ 2
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#define DAT_WORD_LEN_MSK 0x00000003
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#define DAT_WORD_LEN_I_MSK 0xfffffffc
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#define DAT_WORD_LEN_SFT 0
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#define DAT_WORD_LEN_HI 1
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#define DAT_WORD_LEN_SZ 2
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#define DAT_STOP_BIT_MSK 0x00000004
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#define DAT_STOP_BIT_I_MSK 0xfffffffb
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#define DAT_STOP_BIT_SFT 2
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#define DAT_STOP_BIT_HI 2
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#define DAT_STOP_BIT_SZ 1
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#define DAT_PARITY_EN_MSK 0x00000008
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#define DAT_PARITY_EN_I_MSK 0xfffffff7
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#define DAT_PARITY_EN_SFT 3
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#define DAT_PARITY_EN_HI 3
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#define DAT_PARITY_EN_SZ 1
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#define DAT_EVEN_PARITY_MSK 0x00000010
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#define DAT_EVEN_PARITY_I_MSK 0xffffffef
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#define DAT_EVEN_PARITY_SFT 4
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#define DAT_EVEN_PARITY_HI 4
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#define DAT_EVEN_PARITY_SZ 1
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#define DAT_FORCE_PARITY_MSK 0x00000020
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#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
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#define DAT_FORCE_PARITY_SFT 5
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#define DAT_FORCE_PARITY_HI 5
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#define DAT_FORCE_PARITY_SZ 1
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#define DAT_SET_BREAK_MSK 0x00000040
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#define DAT_SET_BREAK_I_MSK 0xffffffbf
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#define DAT_SET_BREAK_SFT 6
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#define DAT_SET_BREAK_HI 6
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#define DAT_SET_BREAK_SZ 1
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#define DAT_DLAB_MSK 0x00000080
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#define DAT_DLAB_I_MSK 0xffffff7f
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#define DAT_DLAB_SFT 7
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#define DAT_DLAB_HI 7
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#define DAT_DLAB_SZ 1
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#define DAT_DTR_MSK 0x00000001
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#define DAT_DTR_I_MSK 0xfffffffe
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#define DAT_DTR_SFT 0
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#define DAT_DTR_HI 0
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#define DAT_DTR_SZ 1
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#define DAT_RTS_MSK 0x00000002
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#define DAT_RTS_I_MSK 0xfffffffd
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#define DAT_RTS_SFT 1
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#define DAT_RTS_HI 1
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#define DAT_RTS_SZ 1
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#define DAT_OUT_1_MSK 0x00000004
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#define DAT_OUT_1_I_MSK 0xfffffffb
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#define DAT_OUT_1_SFT 2
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#define DAT_OUT_1_HI 2
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#define DAT_OUT_1_SZ 1
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#define DAT_OUT_2_MSK 0x00000008
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#define DAT_OUT_2_I_MSK 0xfffffff7
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#define DAT_OUT_2_SFT 3
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#define DAT_OUT_2_HI 3
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#define DAT_OUT_2_SZ 1
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#define DAT_LOOP_BACK_MSK 0x00000010
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#define DAT_LOOP_BACK_I_MSK 0xffffffef
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#define DAT_LOOP_BACK_SFT 4
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#define DAT_LOOP_BACK_HI 4
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#define DAT_LOOP_BACK_SZ 1
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#define DAT_DATA_RDY_MSK 0x00000001
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#define DAT_DATA_RDY_I_MSK 0xfffffffe
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#define DAT_DATA_RDY_SFT 0
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#define DAT_DATA_RDY_HI 0
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#define DAT_DATA_RDY_SZ 1
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#define DAT_OVERRUN_ERR_MSK 0x00000002
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#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
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#define DAT_OVERRUN_ERR_SFT 1
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#define DAT_OVERRUN_ERR_HI 1
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#define DAT_OVERRUN_ERR_SZ 1
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#define DAT_PARITY_ERR_MSK 0x00000004
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#define DAT_PARITY_ERR_I_MSK 0xfffffffb
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#define DAT_PARITY_ERR_SFT 2
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#define DAT_PARITY_ERR_HI 2
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#define DAT_PARITY_ERR_SZ 1
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#define DAT_FRAMING_ERR_MSK 0x00000008
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#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
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#define DAT_FRAMING_ERR_SFT 3
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#define DAT_FRAMING_ERR_HI 3
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#define DAT_FRAMING_ERR_SZ 1
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#define DAT_BREAK_INT_MSK 0x00000010
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#define DAT_BREAK_INT_I_MSK 0xffffffef
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#define DAT_BREAK_INT_SFT 4
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#define DAT_BREAK_INT_HI 4
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#define DAT_BREAK_INT_SZ 1
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#define DAT_THR_EMPTY_MSK 0x00000020
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#define DAT_THR_EMPTY_I_MSK 0xffffffdf
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#define DAT_THR_EMPTY_SFT 5
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#define DAT_THR_EMPTY_HI 5
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#define DAT_THR_EMPTY_SZ 1
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#define DAT_TX_EMPTY_MSK 0x00000040
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#define DAT_TX_EMPTY_I_MSK 0xffffffbf
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#define DAT_TX_EMPTY_SFT 6
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#define DAT_TX_EMPTY_HI 6
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#define DAT_TX_EMPTY_SZ 1
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#define DAT_FIFODATA_ERR_MSK 0x00000080
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#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
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#define DAT_FIFODATA_ERR_SFT 7
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#define DAT_FIFODATA_ERR_HI 7
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#define DAT_FIFODATA_ERR_SZ 1
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#define DAT_DELTA_CTS_MSK 0x00000001
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#define DAT_DELTA_CTS_I_MSK 0xfffffffe
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#define DAT_DELTA_CTS_SFT 0
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#define DAT_DELTA_CTS_HI 0
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#define DAT_DELTA_CTS_SZ 1
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#define DAT_DELTA_DSR_MSK 0x00000002
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#define DAT_DELTA_DSR_I_MSK 0xfffffffd
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#define DAT_DELTA_DSR_SFT 1
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#define DAT_DELTA_DSR_HI 1
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#define DAT_DELTA_DSR_SZ 1
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#define DAT_TRAILEDGE_RI_MSK 0x00000004
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#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
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#define DAT_TRAILEDGE_RI_SFT 2
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#define DAT_TRAILEDGE_RI_HI 2
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#define DAT_TRAILEDGE_RI_SZ 1
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#define DAT_DELTA_CD_MSK 0x00000008
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#define DAT_DELTA_CD_I_MSK 0xfffffff7
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#define DAT_DELTA_CD_SFT 3
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#define DAT_DELTA_CD_HI 3
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#define DAT_DELTA_CD_SZ 1
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#define DAT_CTS_MSK 0x00000010
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#define DAT_CTS_I_MSK 0xffffffef
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#define DAT_CTS_SFT 4
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#define DAT_CTS_HI 4
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#define DAT_CTS_SZ 1
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#define DAT_DSR_MSK 0x00000020
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#define DAT_DSR_I_MSK 0xffffffdf
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#define DAT_DSR_SFT 5
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#define DAT_DSR_HI 5
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#define DAT_DSR_SZ 1
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#define DAT_RI_MSK 0x00000040
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#define DAT_RI_I_MSK 0xffffffbf
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#define DAT_RI_SFT 6
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#define DAT_RI_HI 6
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#define DAT_RI_SZ 1
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#define DAT_CD_MSK 0x00000080
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#define DAT_CD_I_MSK 0xffffff7f
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#define DAT_CD_SFT 7
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#define DAT_CD_HI 7
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#define DAT_CD_SZ 1
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#define DAT_BRDC_DIV_MSK 0x0000ffff
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#define DAT_BRDC_DIV_I_MSK 0xffff0000
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#define DAT_BRDC_DIV_SFT 0
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#define DAT_BRDC_DIV_HI 15
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#define DAT_BRDC_DIV_SZ 16
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#define DAT_RTHR_L_MSK 0x0000000f
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#define DAT_RTHR_L_I_MSK 0xfffffff0
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#define DAT_RTHR_L_SFT 0
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#define DAT_RTHR_L_HI 3
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#define DAT_RTHR_L_SZ 4
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#define DAT_RTHR_H_MSK 0x000000f0
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#define DAT_RTHR_H_I_MSK 0xffffff0f
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#define DAT_RTHR_H_SFT 4
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#define DAT_RTHR_H_HI 7
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#define DAT_RTHR_H_SZ 4
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#define DAT_INT_IDCODE_MSK 0x0000000f
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#define DAT_INT_IDCODE_I_MSK 0xfffffff0
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#define DAT_INT_IDCODE_SFT 0
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#define DAT_INT_IDCODE_HI 3
|
#define DAT_INT_IDCODE_SZ 4
|
#define DAT_FIFOS_ENABLED_MSK 0x000000c0
|
#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
|
#define DAT_FIFOS_ENABLED_SFT 6
|
#define DAT_FIFOS_ENABLED_HI 7
|
#define DAT_FIFOS_ENABLED_SZ 2
|
#define MASK_TOP_MSK 0xffffffff
|
#define MASK_TOP_I_MSK 0x00000000
|
#define MASK_TOP_SFT 0
|
#define MASK_TOP_HI 31
|
#define MASK_TOP_SZ 32
|
#define INT_MODE_MSK 0xffffffff
|
#define INT_MODE_I_MSK 0x00000000
|
#define INT_MODE_SFT 0
|
#define INT_MODE_HI 31
|
#define INT_MODE_SZ 32
|
#define IRQ_PHY_0_MSK 0x00000001
|
#define IRQ_PHY_0_I_MSK 0xfffffffe
|
#define IRQ_PHY_0_SFT 0
|
#define IRQ_PHY_0_HI 0
|
#define IRQ_PHY_0_SZ 1
|
#define IRQ_PHY_1_MSK 0x00000002
|
#define IRQ_PHY_1_I_MSK 0xfffffffd
|
#define IRQ_PHY_1_SFT 1
|
#define IRQ_PHY_1_HI 1
|
#define IRQ_PHY_1_SZ 1
|
#define IRQ_SDIO_MSK 0x00000004
|
#define IRQ_SDIO_I_MSK 0xfffffffb
|
#define IRQ_SDIO_SFT 2
|
#define IRQ_SDIO_HI 2
|
#define IRQ_SDIO_SZ 1
|
#define IRQ_BEACON_DONE_MSK 0x00000008
|
#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
|
#define IRQ_BEACON_DONE_SFT 3
|
#define IRQ_BEACON_DONE_HI 3
|
#define IRQ_BEACON_DONE_SZ 1
|
#define IRQ_BEACON_MSK 0x00000010
|
#define IRQ_BEACON_I_MSK 0xffffffef
|
#define IRQ_BEACON_SFT 4
|
#define IRQ_BEACON_HI 4
|
#define IRQ_BEACON_SZ 1
|
#define IRQ_PRE_BEACON_MSK 0x00000020
|
#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
|
#define IRQ_PRE_BEACON_SFT 5
|
#define IRQ_PRE_BEACON_HI 5
|
#define IRQ_PRE_BEACON_SZ 1
|
#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
|
#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
|
#define IRQ_EDCA0_TX_DONE_SFT 6
|
#define IRQ_EDCA0_TX_DONE_HI 6
|
#define IRQ_EDCA0_TX_DONE_SZ 1
|
#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
|
#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
|
#define IRQ_EDCA1_TX_DONE_SFT 7
|
#define IRQ_EDCA1_TX_DONE_HI 7
|
#define IRQ_EDCA1_TX_DONE_SZ 1
|
#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
|
#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
|
#define IRQ_EDCA2_TX_DONE_SFT 8
|
#define IRQ_EDCA2_TX_DONE_HI 8
|
#define IRQ_EDCA2_TX_DONE_SZ 1
|
#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
|
#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
|
#define IRQ_EDCA3_TX_DONE_SFT 9
|
#define IRQ_EDCA3_TX_DONE_HI 9
|
#define IRQ_EDCA3_TX_DONE_SZ 1
|
#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
|
#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
|
#define IRQ_EDCA4_TX_DONE_SFT 10
|
#define IRQ_EDCA4_TX_DONE_HI 10
|
#define IRQ_EDCA4_TX_DONE_SZ 1
|
#define IRQ_BEACON_DTIM_MSK 0x00001000
|
#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
|
#define IRQ_BEACON_DTIM_SFT 12
|
#define IRQ_BEACON_DTIM_HI 12
|
#define IRQ_BEACON_DTIM_SZ 1
|
#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
|
#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
|
#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
|
#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
|
#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
|
#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
|
#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
|
#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
|
#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
|
#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
|
#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
|
#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
|
#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
|
#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
|
#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
|
#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
|
#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
|
#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
|
#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
|
#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
|
#define IRQ_FENCE_HIT_INT_MSK 0x00020000
|
#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
|
#define IRQ_FENCE_HIT_INT_SFT 17
|
#define IRQ_FENCE_HIT_INT_HI 17
|
#define IRQ_FENCE_HIT_INT_SZ 1
|
#define IRQ_ILL_ADDR_INT_MSK 0x00040000
|
#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
|
#define IRQ_ILL_ADDR_INT_SFT 18
|
#define IRQ_ILL_ADDR_INT_HI 18
|
#define IRQ_ILL_ADDR_INT_SZ 1
|
#define IRQ_MBOX_MSK 0x00080000
|
#define IRQ_MBOX_I_MSK 0xfff7ffff
|
#define IRQ_MBOX_SFT 19
|
#define IRQ_MBOX_HI 19
|
#define IRQ_MBOX_SZ 1
|
#define IRQ_US_TIMER0_MSK 0x00100000
|
#define IRQ_US_TIMER0_I_MSK 0xffefffff
|
#define IRQ_US_TIMER0_SFT 20
|
#define IRQ_US_TIMER0_HI 20
|
#define IRQ_US_TIMER0_SZ 1
|
#define IRQ_US_TIMER1_MSK 0x00200000
|
#define IRQ_US_TIMER1_I_MSK 0xffdfffff
|
#define IRQ_US_TIMER1_SFT 21
|
#define IRQ_US_TIMER1_HI 21
|
#define IRQ_US_TIMER1_SZ 1
|
#define IRQ_US_TIMER2_MSK 0x00400000
|
#define IRQ_US_TIMER2_I_MSK 0xffbfffff
|
#define IRQ_US_TIMER2_SFT 22
|
#define IRQ_US_TIMER2_HI 22
|
#define IRQ_US_TIMER2_SZ 1
|
#define IRQ_US_TIMER3_MSK 0x00800000
|
#define IRQ_US_TIMER3_I_MSK 0xff7fffff
|
#define IRQ_US_TIMER3_SFT 23
|
#define IRQ_US_TIMER3_HI 23
|
#define IRQ_US_TIMER3_SZ 1
|
#define IRQ_MS_TIMER0_MSK 0x01000000
|
#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
|
#define IRQ_MS_TIMER0_SFT 24
|
#define IRQ_MS_TIMER0_HI 24
|
#define IRQ_MS_TIMER0_SZ 1
|
#define IRQ_MS_TIMER1_MSK 0x02000000
|
#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
|
#define IRQ_MS_TIMER1_SFT 25
|
#define IRQ_MS_TIMER1_HI 25
|
#define IRQ_MS_TIMER1_SZ 1
|
#define IRQ_MS_TIMER2_MSK 0x04000000
|
#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
|
#define IRQ_MS_TIMER2_SFT 26
|
#define IRQ_MS_TIMER2_HI 26
|
#define IRQ_MS_TIMER2_SZ 1
|
#define IRQ_MS_TIMER3_MSK 0x08000000
|
#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
|
#define IRQ_MS_TIMER3_SFT 27
|
#define IRQ_MS_TIMER3_HI 27
|
#define IRQ_MS_TIMER3_SZ 1
|
#define IRQ_TX_LIMIT_INT_MSK 0x10000000
|
#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
|
#define IRQ_TX_LIMIT_INT_SFT 28
|
#define IRQ_TX_LIMIT_INT_HI 28
|
#define IRQ_TX_LIMIT_INT_SZ 1
|
#define IRQ_DMA0_MSK 0x20000000
|
#define IRQ_DMA0_I_MSK 0xdfffffff
|
#define IRQ_DMA0_SFT 29
|
#define IRQ_DMA0_HI 29
|
#define IRQ_DMA0_SZ 1
|
#define IRQ_CO_DMA_MSK 0x40000000
|
#define IRQ_CO_DMA_I_MSK 0xbfffffff
|
#define IRQ_CO_DMA_SFT 30
|
#define IRQ_CO_DMA_HI 30
|
#define IRQ_CO_DMA_SZ 1
|
#define IRQ_PERI_GROUP_MSK 0x80000000
|
#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
|
#define IRQ_PERI_GROUP_SFT 31
|
#define IRQ_PERI_GROUP_HI 31
|
#define IRQ_PERI_GROUP_SZ 1
|
#define FIQ_STATUS_MSK 0xffffffff
|
#define FIQ_STATUS_I_MSK 0x00000000
|
#define FIQ_STATUS_SFT 0
|
#define FIQ_STATUS_HI 31
|
#define FIQ_STATUS_SZ 32
|
#define IRQ_RAW_MSK 0xffffffff
|
#define IRQ_RAW_I_MSK 0x00000000
|
#define IRQ_RAW_SFT 0
|
#define IRQ_RAW_HI 31
|
#define IRQ_RAW_SZ 32
|
#define FIQ_RAW_MSK 0xffffffff
|
#define FIQ_RAW_I_MSK 0x00000000
|
#define FIQ_RAW_SFT 0
|
#define FIQ_RAW_HI 31
|
#define FIQ_RAW_SZ 32
|
#define INT_PERI_MASK_MSK 0xffffffff
|
#define INT_PERI_MASK_I_MSK 0x00000000
|
#define INT_PERI_MASK_SFT 0
|
#define INT_PERI_MASK_HI 31
|
#define INT_PERI_MASK_SZ 32
|
#define PERI_RTC_MSK 0x00000001
|
#define PERI_RTC_I_MSK 0xfffffffe
|
#define PERI_RTC_SFT 0
|
#define PERI_RTC_HI 0
|
#define PERI_RTC_SZ 1
|
#define IRQ_UART0_TX_MSK 0x00000002
|
#define IRQ_UART0_TX_I_MSK 0xfffffffd
|
#define IRQ_UART0_TX_SFT 1
|
#define IRQ_UART0_TX_HI 1
|
#define IRQ_UART0_TX_SZ 1
|
#define IRQ_UART0_RX_MSK 0x00000004
|
#define IRQ_UART0_RX_I_MSK 0xfffffffb
|
#define IRQ_UART0_RX_SFT 2
|
#define IRQ_UART0_RX_HI 2
|
#define IRQ_UART0_RX_SZ 1
|
#define PERI_GPI_2_MSK 0x00000008
|
#define PERI_GPI_2_I_MSK 0xfffffff7
|
#define PERI_GPI_2_SFT 3
|
#define PERI_GPI_2_HI 3
|
#define PERI_GPI_2_SZ 1
|
#define IRQ_SPI_IPC_MSK 0x00000010
|
#define IRQ_SPI_IPC_I_MSK 0xffffffef
|
#define IRQ_SPI_IPC_SFT 4
|
#define IRQ_SPI_IPC_HI 4
|
#define IRQ_SPI_IPC_SZ 1
|
#define PERI_GPI_1_0_MSK 0x00000060
|
#define PERI_GPI_1_0_I_MSK 0xffffff9f
|
#define PERI_GPI_1_0_SFT 5
|
#define PERI_GPI_1_0_HI 6
|
#define PERI_GPI_1_0_SZ 2
|
#define SCRT_INT_1_MSK 0x00000080
|
#define SCRT_INT_1_I_MSK 0xffffff7f
|
#define SCRT_INT_1_SFT 7
|
#define SCRT_INT_1_HI 7
|
#define SCRT_INT_1_SZ 1
|
#define MMU_ALC_ERR_MSK 0x00000100
|
#define MMU_ALC_ERR_I_MSK 0xfffffeff
|
#define MMU_ALC_ERR_SFT 8
|
#define MMU_ALC_ERR_HI 8
|
#define MMU_ALC_ERR_SZ 1
|
#define MMU_RLS_ERR_MSK 0x00000200
|
#define MMU_RLS_ERR_I_MSK 0xfffffdff
|
#define MMU_RLS_ERR_SFT 9
|
#define MMU_RLS_ERR_HI 9
|
#define MMU_RLS_ERR_SZ 1
|
#define ID_MNG_INT_1_MSK 0x00000400
|
#define ID_MNG_INT_1_I_MSK 0xfffffbff
|
#define ID_MNG_INT_1_SFT 10
|
#define ID_MNG_INT_1_HI 10
|
#define ID_MNG_INT_1_SZ 1
|
#define MBOX_INT_1_MSK 0x00000800
|
#define MBOX_INT_1_I_MSK 0xfffff7ff
|
#define MBOX_INT_1_SFT 11
|
#define MBOX_INT_1_HI 11
|
#define MBOX_INT_1_SZ 1
|
#define MBOX_INT_2_MSK 0x00001000
|
#define MBOX_INT_2_I_MSK 0xffffefff
|
#define MBOX_INT_2_SFT 12
|
#define MBOX_INT_2_HI 12
|
#define MBOX_INT_2_SZ 1
|
#define MBOX_INT_3_MSK 0x00002000
|
#define MBOX_INT_3_I_MSK 0xffffdfff
|
#define MBOX_INT_3_SFT 13
|
#define MBOX_INT_3_HI 13
|
#define MBOX_INT_3_SZ 1
|
#define HCI_INT_1_MSK 0x00004000
|
#define HCI_INT_1_I_MSK 0xffffbfff
|
#define HCI_INT_1_SFT 14
|
#define HCI_INT_1_HI 14
|
#define HCI_INT_1_SZ 1
|
#define UART_RX_TIMEOUT_MSK 0x00008000
|
#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
|
#define UART_RX_TIMEOUT_SFT 15
|
#define UART_RX_TIMEOUT_HI 15
|
#define UART_RX_TIMEOUT_SZ 1
|
#define UART_MULTI_IRQ_MSK 0x00010000
|
#define UART_MULTI_IRQ_I_MSK 0xfffeffff
|
#define UART_MULTI_IRQ_SFT 16
|
#define UART_MULTI_IRQ_HI 16
|
#define UART_MULTI_IRQ_SZ 1
|
#define ID_MNG_INT_2_MSK 0x00020000
|
#define ID_MNG_INT_2_I_MSK 0xfffdffff
|
#define ID_MNG_INT_2_SFT 17
|
#define ID_MNG_INT_2_HI 17
|
#define ID_MNG_INT_2_SZ 1
|
#define DMN_NOHIT_INT_MSK 0x00040000
|
#define DMN_NOHIT_INT_I_MSK 0xfffbffff
|
#define DMN_NOHIT_INT_SFT 18
|
#define DMN_NOHIT_INT_HI 18
|
#define DMN_NOHIT_INT_SZ 1
|
#define ID_THOLD_RX_MSK 0x00080000
|
#define ID_THOLD_RX_I_MSK 0xfff7ffff
|
#define ID_THOLD_RX_SFT 19
|
#define ID_THOLD_RX_HI 19
|
#define ID_THOLD_RX_SZ 1
|
#define ID_THOLD_TX_MSK 0x00100000
|
#define ID_THOLD_TX_I_MSK 0xffefffff
|
#define ID_THOLD_TX_SFT 20
|
#define ID_THOLD_TX_HI 20
|
#define ID_THOLD_TX_SZ 1
|
#define ID_DOUBLE_RLS_MSK 0x00200000
|
#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
|
#define ID_DOUBLE_RLS_SFT 21
|
#define ID_DOUBLE_RLS_HI 21
|
#define ID_DOUBLE_RLS_SZ 1
|
#define RX_ID_LEN_THOLD_MSK 0x00400000
|
#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
|
#define RX_ID_LEN_THOLD_SFT 22
|
#define RX_ID_LEN_THOLD_HI 22
|
#define RX_ID_LEN_THOLD_SZ 1
|
#define TX_ID_LEN_THOLD_MSK 0x00800000
|
#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
|
#define TX_ID_LEN_THOLD_SFT 23
|
#define TX_ID_LEN_THOLD_HI 23
|
#define TX_ID_LEN_THOLD_SZ 1
|
#define ALL_ID_LEN_THOLD_MSK 0x01000000
|
#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
|
#define ALL_ID_LEN_THOLD_SFT 24
|
#define ALL_ID_LEN_THOLD_HI 24
|
#define ALL_ID_LEN_THOLD_SZ 1
|
#define DMN_MCU_INT_MSK 0x02000000
|
#define DMN_MCU_INT_I_MSK 0xfdffffff
|
#define DMN_MCU_INT_SFT 25
|
#define DMN_MCU_INT_HI 25
|
#define DMN_MCU_INT_SZ 1
|
#define IRQ_DAT_UART_TX_MSK 0x04000000
|
#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
|
#define IRQ_DAT_UART_TX_SFT 26
|
#define IRQ_DAT_UART_TX_HI 26
|
#define IRQ_DAT_UART_TX_SZ 1
|
#define IRQ_DAT_UART_RX_MSK 0x08000000
|
#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
|
#define IRQ_DAT_UART_RX_SFT 27
|
#define IRQ_DAT_UART_RX_HI 27
|
#define IRQ_DAT_UART_RX_SZ 1
|
#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
|
#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
|
#define DAT_UART_RX_TIMEOUT_SFT 28
|
#define DAT_UART_RX_TIMEOUT_HI 28
|
#define DAT_UART_RX_TIMEOUT_SZ 1
|
#define DAT_UART_MULTI_IRQ_MSK 0x20000000
|
#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
|
#define DAT_UART_MULTI_IRQ_SFT 29
|
#define DAT_UART_MULTI_IRQ_HI 29
|
#define DAT_UART_MULTI_IRQ_SZ 1
|
#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
|
#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
|
#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
|
#define ALR_ABT_NOCHG_INT_IRQ_HI 30
|
#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
|
#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
|
#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
|
#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
|
#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
|
#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
|
#define INTR_PERI_RAW_MSK 0xffffffff
|
#define INTR_PERI_RAW_I_MSK 0x00000000
|
#define INTR_PERI_RAW_SFT 0
|
#define INTR_PERI_RAW_HI 31
|
#define INTR_PERI_RAW_SZ 32
|
#define INTR_GPI00_CFG_MSK 0x00000003
|
#define INTR_GPI00_CFG_I_MSK 0xfffffffc
|
#define INTR_GPI00_CFG_SFT 0
|
#define INTR_GPI00_CFG_HI 1
|
#define INTR_GPI00_CFG_SZ 2
|
#define INTR_GPI01_CFG_MSK 0x0000000c
|
#define INTR_GPI01_CFG_I_MSK 0xfffffff3
|
#define INTR_GPI01_CFG_SFT 2
|
#define INTR_GPI01_CFG_HI 3
|
#define INTR_GPI01_CFG_SZ 2
|
#define SYS_RST_INT_MSK 0x00000001
|
#define SYS_RST_INT_I_MSK 0xfffffffe
|
#define SYS_RST_INT_SFT 0
|
#define SYS_RST_INT_HI 0
|
#define SYS_RST_INT_SZ 1
|
#define SPI_IPC_ADDR_MSK 0xffffffff
|
#define SPI_IPC_ADDR_I_MSK 0x00000000
|
#define SPI_IPC_ADDR_SFT 0
|
#define SPI_IPC_ADDR_HI 31
|
#define SPI_IPC_ADDR_SZ 32
|
#define SD_MASK_TOP_MSK 0xffffffff
|
#define SD_MASK_TOP_I_MSK 0x00000000
|
#define SD_MASK_TOP_SFT 0
|
#define SD_MASK_TOP_HI 31
|
#define SD_MASK_TOP_SZ 32
|
#define IRQ_PHY_0_SD_MSK 0x00000001
|
#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
|
#define IRQ_PHY_0_SD_SFT 0
|
#define IRQ_PHY_0_SD_HI 0
|
#define IRQ_PHY_0_SD_SZ 1
|
#define IRQ_PHY_1_SD_MSK 0x00000002
|
#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
|
#define IRQ_PHY_1_SD_SFT 1
|
#define IRQ_PHY_1_SD_HI 1
|
#define IRQ_PHY_1_SD_SZ 1
|
#define IRQ_SDIO_SD_MSK 0x00000004
|
#define IRQ_SDIO_SD_I_MSK 0xfffffffb
|
#define IRQ_SDIO_SD_SFT 2
|
#define IRQ_SDIO_SD_HI 2
|
#define IRQ_SDIO_SD_SZ 1
|
#define IRQ_BEACON_DONE_SD_MSK 0x00000008
|
#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
|
#define IRQ_BEACON_DONE_SD_SFT 3
|
#define IRQ_BEACON_DONE_SD_HI 3
|
#define IRQ_BEACON_DONE_SD_SZ 1
|
#define IRQ_BEACON_SD_MSK 0x00000010
|
#define IRQ_BEACON_SD_I_MSK 0xffffffef
|
#define IRQ_BEACON_SD_SFT 4
|
#define IRQ_BEACON_SD_HI 4
|
#define IRQ_BEACON_SD_SZ 1
|
#define IRQ_PRE_BEACON_SD_MSK 0x00000020
|
#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
|
#define IRQ_PRE_BEACON_SD_SFT 5
|
#define IRQ_PRE_BEACON_SD_HI 5
|
#define IRQ_PRE_BEACON_SD_SZ 1
|
#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
|
#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
|
#define IRQ_EDCA0_TX_DONE_SD_SFT 6
|
#define IRQ_EDCA0_TX_DONE_SD_HI 6
|
#define IRQ_EDCA0_TX_DONE_SD_SZ 1
|
#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
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#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
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#define IRQ_EDCA1_TX_DONE_SD_SFT 7
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#define IRQ_EDCA1_TX_DONE_SD_HI 7
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#define IRQ_EDCA1_TX_DONE_SD_SZ 1
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#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
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#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
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#define IRQ_EDCA2_TX_DONE_SD_SFT 8
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#define IRQ_EDCA2_TX_DONE_SD_HI 8
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#define IRQ_EDCA2_TX_DONE_SD_SZ 1
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#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
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#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
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#define IRQ_EDCA3_TX_DONE_SD_SFT 9
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#define IRQ_EDCA3_TX_DONE_SD_HI 9
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#define IRQ_EDCA3_TX_DONE_SD_SZ 1
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#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
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#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
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#define IRQ_EDCA4_TX_DONE_SD_SFT 10
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#define IRQ_EDCA4_TX_DONE_SD_HI 10
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#define IRQ_EDCA4_TX_DONE_SD_SZ 1
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#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
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#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
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#define IRQ_BEACON_DTIM_SD_SFT 12
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#define IRQ_BEACON_DTIM_SD_HI 12
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#define IRQ_BEACON_DTIM_SD_SZ 1
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#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
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#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
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#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
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#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
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#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
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#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
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#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
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#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
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#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
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#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
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#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
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#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
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#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
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#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
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#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
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#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
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#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
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#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
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#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
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#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
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#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
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#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
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#define IRQ_FENCE_HIT_INT_SD_SFT 17
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#define IRQ_FENCE_HIT_INT_SD_HI 17
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#define IRQ_FENCE_HIT_INT_SD_SZ 1
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#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
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#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
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#define IRQ_ILL_ADDR_INT_SD_SFT 18
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#define IRQ_ILL_ADDR_INT_SD_HI 18
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#define IRQ_ILL_ADDR_INT_SD_SZ 1
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#define IRQ_MBOX_SD_MSK 0x00080000
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#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
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#define IRQ_MBOX_SD_SFT 19
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#define IRQ_MBOX_SD_HI 19
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#define IRQ_MBOX_SD_SZ 1
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#define IRQ_US_TIMER0_SD_MSK 0x00100000
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#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
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#define IRQ_US_TIMER0_SD_SFT 20
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#define IRQ_US_TIMER0_SD_HI 20
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#define IRQ_US_TIMER0_SD_SZ 1
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#define IRQ_US_TIMER1_SD_MSK 0x00200000
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#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
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#define IRQ_US_TIMER1_SD_SFT 21
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#define IRQ_US_TIMER1_SD_HI 21
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#define IRQ_US_TIMER1_SD_SZ 1
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#define IRQ_US_TIMER2_SD_MSK 0x00400000
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#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
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#define IRQ_US_TIMER2_SD_SFT 22
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#define IRQ_US_TIMER2_SD_HI 22
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#define IRQ_US_TIMER2_SD_SZ 1
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#define IRQ_US_TIMER3_SD_MSK 0x00800000
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#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
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#define IRQ_US_TIMER3_SD_SFT 23
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#define IRQ_US_TIMER3_SD_HI 23
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#define IRQ_US_TIMER3_SD_SZ 1
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#define IRQ_MS_TIMER0_SD_MSK 0x01000000
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#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
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#define IRQ_MS_TIMER0_SD_SFT 24
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#define IRQ_MS_TIMER0_SD_HI 24
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#define IRQ_MS_TIMER0_SD_SZ 1
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#define IRQ_MS_TIMER1_SD_MSK 0x02000000
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#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
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#define IRQ_MS_TIMER1_SD_SFT 25
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#define IRQ_MS_TIMER1_SD_HI 25
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#define IRQ_MS_TIMER1_SD_SZ 1
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#define IRQ_MS_TIMER2_SD_MSK 0x04000000
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#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
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#define IRQ_MS_TIMER2_SD_SFT 26
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#define IRQ_MS_TIMER2_SD_HI 26
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#define IRQ_MS_TIMER2_SD_SZ 1
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#define IRQ_MS_TIMER3_SD_MSK 0x08000000
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#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
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#define IRQ_MS_TIMER3_SD_SFT 27
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#define IRQ_MS_TIMER3_SD_HI 27
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#define IRQ_MS_TIMER3_SD_SZ 1
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#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
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#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
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#define IRQ_TX_LIMIT_INT_SD_SFT 28
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#define IRQ_TX_LIMIT_INT_SD_HI 28
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#define IRQ_TX_LIMIT_INT_SD_SZ 1
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#define IRQ_DMA0_SD_MSK 0x20000000
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#define IRQ_DMA0_SD_I_MSK 0xdfffffff
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#define IRQ_DMA0_SD_SFT 29
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#define IRQ_DMA0_SD_HI 29
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#define IRQ_DMA0_SD_SZ 1
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#define IRQ_CO_DMA_SD_MSK 0x40000000
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#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
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#define IRQ_CO_DMA_SD_SFT 30
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#define IRQ_CO_DMA_SD_HI 30
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#define IRQ_CO_DMA_SD_SZ 1
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#define IRQ_PERI_GROUP_SD_MSK 0x80000000
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#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
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#define IRQ_PERI_GROUP_SD_SFT 31
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#define IRQ_PERI_GROUP_SD_HI 31
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#define IRQ_PERI_GROUP_SD_SZ 1
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#define INT_PERI_MASK_SD_MSK 0xffffffff
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#define INT_PERI_MASK_SD_I_MSK 0x00000000
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#define INT_PERI_MASK_SD_SFT 0
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#define INT_PERI_MASK_SD_HI 31
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#define INT_PERI_MASK_SD_SZ 32
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#define PERI_RTC_SD_MSK 0x00000001
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#define PERI_RTC_SD_I_MSK 0xfffffffe
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#define PERI_RTC_SD_SFT 0
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#define PERI_RTC_SD_HI 0
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#define PERI_RTC_SD_SZ 1
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#define IRQ_UART0_TX_SD_MSK 0x00000002
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#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
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#define IRQ_UART0_TX_SD_SFT 1
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#define IRQ_UART0_TX_SD_HI 1
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#define IRQ_UART0_TX_SD_SZ 1
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#define IRQ_UART0_RX_SD_MSK 0x00000004
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#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
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#define IRQ_UART0_RX_SD_SFT 2
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#define IRQ_UART0_RX_SD_HI 2
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#define IRQ_UART0_RX_SD_SZ 1
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#define PERI_GPI_SD_2_MSK 0x00000008
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#define PERI_GPI_SD_2_I_MSK 0xfffffff7
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#define PERI_GPI_SD_2_SFT 3
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#define PERI_GPI_SD_2_HI 3
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#define PERI_GPI_SD_2_SZ 1
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#define IRQ_SPI_IPC_SD_MSK 0x00000010
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#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
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#define IRQ_SPI_IPC_SD_SFT 4
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#define IRQ_SPI_IPC_SD_HI 4
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#define IRQ_SPI_IPC_SD_SZ 1
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#define PERI_GPI_SD_1_0_MSK 0x00000060
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#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
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#define PERI_GPI_SD_1_0_SFT 5
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#define PERI_GPI_SD_1_0_HI 6
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#define PERI_GPI_SD_1_0_SZ 2
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#define SCRT_INT_1_SD_MSK 0x00000080
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#define SCRT_INT_1_SD_I_MSK 0xffffff7f
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#define SCRT_INT_1_SD_SFT 7
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#define SCRT_INT_1_SD_HI 7
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#define SCRT_INT_1_SD_SZ 1
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#define MMU_ALC_ERR_SD_MSK 0x00000100
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#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
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#define MMU_ALC_ERR_SD_SFT 8
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#define MMU_ALC_ERR_SD_HI 8
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#define MMU_ALC_ERR_SD_SZ 1
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#define MMU_RLS_ERR_SD_MSK 0x00000200
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#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
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#define MMU_RLS_ERR_SD_SFT 9
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#define MMU_RLS_ERR_SD_HI 9
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#define MMU_RLS_ERR_SD_SZ 1
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#define ID_MNG_INT_1_SD_MSK 0x00000400
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#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
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#define ID_MNG_INT_1_SD_SFT 10
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#define ID_MNG_INT_1_SD_HI 10
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#define ID_MNG_INT_1_SD_SZ 1
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#define MBOX_INT_1_SD_MSK 0x00000800
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#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
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#define MBOX_INT_1_SD_SFT 11
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#define MBOX_INT_1_SD_HI 11
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#define MBOX_INT_1_SD_SZ 1
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#define MBOX_INT_2_SD_MSK 0x00001000
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#define MBOX_INT_2_SD_I_MSK 0xffffefff
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#define MBOX_INT_2_SD_SFT 12
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#define MBOX_INT_2_SD_HI 12
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#define MBOX_INT_2_SD_SZ 1
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#define MBOX_INT_3_SD_MSK 0x00002000
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#define MBOX_INT_3_SD_I_MSK 0xffffdfff
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#define MBOX_INT_3_SD_SFT 13
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#define MBOX_INT_3_SD_HI 13
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#define MBOX_INT_3_SD_SZ 1
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#define HCI_INT_1_SD_MSK 0x00004000
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#define HCI_INT_1_SD_I_MSK 0xffffbfff
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#define HCI_INT_1_SD_SFT 14
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#define HCI_INT_1_SD_HI 14
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#define HCI_INT_1_SD_SZ 1
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#define UART_RX_TIMEOUT_SD_MSK 0x00008000
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#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
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#define UART_RX_TIMEOUT_SD_SFT 15
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#define UART_RX_TIMEOUT_SD_HI 15
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#define UART_RX_TIMEOUT_SD_SZ 1
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#define UART_MULTI_IRQ_SD_MSK 0x00010000
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#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
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#define UART_MULTI_IRQ_SD_SFT 16
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#define UART_MULTI_IRQ_SD_HI 16
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#define UART_MULTI_IRQ_SD_SZ 1
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#define ID_MNG_INT_2_SD_MSK 0x00020000
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#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
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#define ID_MNG_INT_2_SD_SFT 17
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#define ID_MNG_INT_2_SD_HI 17
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#define ID_MNG_INT_2_SD_SZ 1
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#define DMN_NOHIT_INT_SD_MSK 0x00040000
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#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
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#define DMN_NOHIT_INT_SD_SFT 18
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#define DMN_NOHIT_INT_SD_HI 18
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#define DMN_NOHIT_INT_SD_SZ 1
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#define ID_THOLD_RX_SD_MSK 0x00080000
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#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
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#define ID_THOLD_RX_SD_SFT 19
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#define ID_THOLD_RX_SD_HI 19
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#define ID_THOLD_RX_SD_SZ 1
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#define ID_THOLD_TX_SD_MSK 0x00100000
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#define ID_THOLD_TX_SD_I_MSK 0xffefffff
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#define ID_THOLD_TX_SD_SFT 20
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#define ID_THOLD_TX_SD_HI 20
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#define ID_THOLD_TX_SD_SZ 1
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#define ID_DOUBLE_RLS_SD_MSK 0x00200000
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#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
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#define ID_DOUBLE_RLS_SD_SFT 21
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#define ID_DOUBLE_RLS_SD_HI 21
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#define ID_DOUBLE_RLS_SD_SZ 1
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#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
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#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
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#define RX_ID_LEN_THOLD_SD_SFT 22
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#define RX_ID_LEN_THOLD_SD_HI 22
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#define RX_ID_LEN_THOLD_SD_SZ 1
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#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
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#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
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#define TX_ID_LEN_THOLD_SD_SFT 23
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#define TX_ID_LEN_THOLD_SD_HI 23
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#define TX_ID_LEN_THOLD_SD_SZ 1
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#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
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#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
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#define ALL_ID_LEN_THOLD_SD_SFT 24
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#define ALL_ID_LEN_THOLD_SD_HI 24
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#define ALL_ID_LEN_THOLD_SD_SZ 1
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#define DMN_MCU_INT_SD_MSK 0x02000000
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#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
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#define DMN_MCU_INT_SD_SFT 25
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#define DMN_MCU_INT_SD_HI 25
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#define DMN_MCU_INT_SD_SZ 1
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#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
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#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
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#define IRQ_DAT_UART_TX_SD_SFT 26
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#define IRQ_DAT_UART_TX_SD_HI 26
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#define IRQ_DAT_UART_TX_SD_SZ 1
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#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
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#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
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#define IRQ_DAT_UART_RX_SD_SFT 27
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#define IRQ_DAT_UART_RX_SD_HI 27
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#define IRQ_DAT_UART_RX_SD_SZ 1
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#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
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#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
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#define DAT_UART_RX_TIMEOUT_SD_SFT 28
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#define DAT_UART_RX_TIMEOUT_SD_HI 28
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#define DAT_UART_RX_TIMEOUT_SD_SZ 1
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#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
|
#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
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#define DAT_UART_MULTI_IRQ_SD_SFT 29
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#define DAT_UART_MULTI_IRQ_SD_HI 29
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#define DAT_UART_MULTI_IRQ_SD_SZ 1
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#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
|
#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
|
#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
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#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
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#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
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#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
|
#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
|
#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
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#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
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#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
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#define DBG_SPI_MODE_MSK 0xffffffff
|
#define DBG_SPI_MODE_I_MSK 0x00000000
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#define DBG_SPI_MODE_SFT 0
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#define DBG_SPI_MODE_HI 31
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#define DBG_SPI_MODE_SZ 32
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#define DBG_RX_QUOTA_MSK 0x0000ffff
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#define DBG_RX_QUOTA_I_MSK 0xffff0000
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#define DBG_RX_QUOTA_SFT 0
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#define DBG_RX_QUOTA_HI 15
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#define DBG_RX_QUOTA_SZ 16
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#define DBG_CONDI_NUM_MSK 0x000000ff
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#define DBG_CONDI_NUM_I_MSK 0xffffff00
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#define DBG_CONDI_NUM_SFT 0
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#define DBG_CONDI_NUM_HI 7
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#define DBG_CONDI_NUM_SZ 8
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#define DBG_HOST_PATH_MSK 0x00000001
|
#define DBG_HOST_PATH_I_MSK 0xfffffffe
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#define DBG_HOST_PATH_SFT 0
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#define DBG_HOST_PATH_HI 0
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#define DBG_HOST_PATH_SZ 1
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#define DBG_TX_SEG_MSK 0xffffffff
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#define DBG_TX_SEG_I_MSK 0x00000000
|
#define DBG_TX_SEG_SFT 0
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#define DBG_TX_SEG_HI 31
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#define DBG_TX_SEG_SZ 32
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#define DBG_BRST_MODE_MSK 0x00000001
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#define DBG_BRST_MODE_I_MSK 0xfffffffe
|
#define DBG_BRST_MODE_SFT 0
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#define DBG_BRST_MODE_HI 0
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#define DBG_BRST_MODE_SZ 1
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#define DBG_CLK_WIDTH_MSK 0x0000ffff
|
#define DBG_CLK_WIDTH_I_MSK 0xffff0000
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#define DBG_CLK_WIDTH_SFT 0
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#define DBG_CLK_WIDTH_HI 15
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#define DBG_CLK_WIDTH_SZ 16
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#define DBG_CSN_INTER_MSK 0xffff0000
|
#define DBG_CSN_INTER_I_MSK 0x0000ffff
|
#define DBG_CSN_INTER_SFT 16
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#define DBG_CSN_INTER_HI 31
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#define DBG_CSN_INTER_SZ 16
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#define DBG_BACK_DLY_MSK 0x0000ffff
|
#define DBG_BACK_DLY_I_MSK 0xffff0000
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#define DBG_BACK_DLY_SFT 0
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#define DBG_BACK_DLY_HI 15
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#define DBG_BACK_DLY_SZ 16
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#define DBG_FRONT_DLY_MSK 0xffff0000
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#define DBG_FRONT_DLY_I_MSK 0x0000ffff
|
#define DBG_FRONT_DLY_SFT 16
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#define DBG_FRONT_DLY_HI 31
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#define DBG_FRONT_DLY_SZ 16
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#define DBG_RX_FIFO_FAIL_MSK 0x00000002
|
#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
|
#define DBG_RX_FIFO_FAIL_SFT 1
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#define DBG_RX_FIFO_FAIL_HI 1
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#define DBG_RX_FIFO_FAIL_SZ 1
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#define DBG_RX_HOST_FAIL_MSK 0x00000004
|
#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
|
#define DBG_RX_HOST_FAIL_SFT 2
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#define DBG_RX_HOST_FAIL_HI 2
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#define DBG_RX_HOST_FAIL_SZ 1
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#define DBG_TX_FIFO_FAIL_MSK 0x00000008
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#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
|
#define DBG_TX_FIFO_FAIL_SFT 3
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#define DBG_TX_FIFO_FAIL_HI 3
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#define DBG_TX_FIFO_FAIL_SZ 1
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#define DBG_TX_HOST_FAIL_MSK 0x00000010
|
#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
|
#define DBG_TX_HOST_FAIL_SFT 4
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#define DBG_TX_HOST_FAIL_HI 4
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#define DBG_TX_HOST_FAIL_SZ 1
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#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
|
#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
|
#define DBG_SPI_DOUBLE_ALLOC_SFT 5
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#define DBG_SPI_DOUBLE_ALLOC_HI 5
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#define DBG_SPI_DOUBLE_ALLOC_SZ 1
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#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
|
#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
|
#define DBG_SPI_TX_NO_ALLOC_SFT 6
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#define DBG_SPI_TX_NO_ALLOC_HI 6
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#define DBG_SPI_TX_NO_ALLOC_SZ 1
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#define DBG_RDATA_RDY_MSK 0x00000080
|
#define DBG_RDATA_RDY_I_MSK 0xffffff7f
|
#define DBG_RDATA_RDY_SFT 7
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#define DBG_RDATA_RDY_HI 7
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#define DBG_RDATA_RDY_SZ 1
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#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
|
#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
|
#define DBG_SPI_ALLOC_STATUS_SFT 8
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#define DBG_SPI_ALLOC_STATUS_HI 8
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#define DBG_SPI_ALLOC_STATUS_SZ 1
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#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
|
#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
|
#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
|
#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
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#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
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#define DBG_RX_LEN_MSK 0xffff0000
|
#define DBG_RX_LEN_I_MSK 0x0000ffff
|
#define DBG_RX_LEN_SFT 16
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#define DBG_RX_LEN_HI 31
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#define DBG_RX_LEN_SZ 16
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#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
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#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
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#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
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#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
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#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
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#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
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#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
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#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
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#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
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#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
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#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
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#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
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#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
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#define DBG_SPI_TX_ALLOC_SIZE_HI 7
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#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
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#define DBG_RD_DAT_CNT_MSK 0x0000ffff
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#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
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#define DBG_RD_DAT_CNT_SFT 0
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#define DBG_RD_DAT_CNT_HI 15
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#define DBG_RD_DAT_CNT_SZ 16
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#define DBG_RD_STS_CNT_MSK 0xffff0000
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#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
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#define DBG_RD_STS_CNT_SFT 16
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#define DBG_RD_STS_CNT_HI 31
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#define DBG_RD_STS_CNT_SZ 16
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#define DBG_JUDGE_CNT_MSK 0x0000ffff
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#define DBG_JUDGE_CNT_I_MSK 0xffff0000
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#define DBG_JUDGE_CNT_SFT 0
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#define DBG_JUDGE_CNT_HI 15
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#define DBG_JUDGE_CNT_SZ 16
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#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
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#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
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#define DBG_RD_STS_CNT_CLR_SFT 16
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#define DBG_RD_STS_CNT_CLR_HI 16
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#define DBG_RD_STS_CNT_CLR_SZ 1
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#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
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#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
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#define DBG_RD_DAT_CNT_CLR_SFT 17
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#define DBG_RD_DAT_CNT_CLR_HI 17
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#define DBG_RD_DAT_CNT_CLR_SZ 1
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#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
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#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
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#define DBG_JUDGE_CNT_CLR_SFT 18
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#define DBG_JUDGE_CNT_CLR_HI 18
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#define DBG_JUDGE_CNT_CLR_SZ 1
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#define DBG_TX_DONE_CNT_MSK 0x0000ffff
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#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
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#define DBG_TX_DONE_CNT_SFT 0
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#define DBG_TX_DONE_CNT_HI 15
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#define DBG_TX_DONE_CNT_SZ 16
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#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
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#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
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#define DBG_TX_DISCARD_CNT_SFT 16
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#define DBG_TX_DISCARD_CNT_HI 31
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#define DBG_TX_DISCARD_CNT_SZ 16
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#define DBG_TX_SET_CNT_MSK 0x0000ffff
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#define DBG_TX_SET_CNT_I_MSK 0xffff0000
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#define DBG_TX_SET_CNT_SFT 0
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#define DBG_TX_SET_CNT_HI 15
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#define DBG_TX_SET_CNT_SZ 16
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#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
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#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
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#define DBG_TX_DISCARD_CNT_CLR_SFT 16
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#define DBG_TX_DISCARD_CNT_CLR_HI 16
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#define DBG_TX_DISCARD_CNT_CLR_SZ 1
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#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
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#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
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#define DBG_TX_DONE_CNT_CLR_SFT 17
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#define DBG_TX_DONE_CNT_CLR_HI 17
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#define DBG_TX_DONE_CNT_CLR_SZ 1
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#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
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#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
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#define DBG_TX_SET_CNT_CLR_SFT 18
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#define DBG_TX_SET_CNT_CLR_HI 18
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#define DBG_TX_SET_CNT_CLR_SZ 1
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#define DBG_DAT_MODE_OFF_MSK 0x00080000
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#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
|
#define DBG_DAT_MODE_OFF_SFT 19
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#define DBG_DAT_MODE_OFF_HI 19
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#define DBG_DAT_MODE_OFF_SZ 1
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#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
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#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
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#define DBG_TX_FIFO_RESIDUE_SFT 20
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#define DBG_TX_FIFO_RESIDUE_HI 22
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#define DBG_TX_FIFO_RESIDUE_SZ 3
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#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
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#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
|
#define DBG_RX_FIFO_RESIDUE_SFT 24
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#define DBG_RX_FIFO_RESIDUE_HI 26
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#define DBG_RX_FIFO_RESIDUE_SZ 3
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#define DBG_RX_RDY_MSK 0x00000001
|
#define DBG_RX_RDY_I_MSK 0xfffffffe
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#define DBG_RX_RDY_SFT 0
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#define DBG_RX_RDY_HI 0
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#define DBG_RX_RDY_SZ 1
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#define DBG_SDIO_SYS_INT_MSK 0x00000004
|
#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
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#define DBG_SDIO_SYS_INT_SFT 2
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#define DBG_SDIO_SYS_INT_HI 2
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#define DBG_SDIO_SYS_INT_SZ 1
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#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
|
#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
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#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
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#define DBG_EDCA0_LOWTHOLD_INT_HI 3
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#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
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#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
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#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
|
#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
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#define DBG_EDCA1_LOWTHOLD_INT_HI 4
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#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
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#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
|
#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
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#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
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#define DBG_EDCA2_LOWTHOLD_INT_HI 5
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#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
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#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
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#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
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#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
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#define DBG_EDCA3_LOWTHOLD_INT_HI 6
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#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
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#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
|
#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
|
#define DBG_TX_LIMIT_INT_IN_SFT 7
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#define DBG_TX_LIMIT_INT_IN_HI 7
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#define DBG_TX_LIMIT_INT_IN_SZ 1
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#define DBG_SPI_FN1_MSK 0x00007f00
|
#define DBG_SPI_FN1_I_MSK 0xffff80ff
|
#define DBG_SPI_FN1_SFT 8
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#define DBG_SPI_FN1_HI 14
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#define DBG_SPI_FN1_SZ 7
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#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
|
#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
|
#define DBG_SPI_CLK_EN_INT_SFT 15
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#define DBG_SPI_CLK_EN_INT_HI 15
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#define DBG_SPI_CLK_EN_INT_SZ 1
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#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
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#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
|
#define DBG_SPI_HOST_MASK_SFT 16
|
#define DBG_SPI_HOST_MASK_HI 23
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#define DBG_SPI_HOST_MASK_SZ 8
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#define BOOT_ADDR_MSK 0x00ffffff
|
#define BOOT_ADDR_I_MSK 0xff000000
|
#define BOOT_ADDR_SFT 0
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#define BOOT_ADDR_HI 23
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#define BOOT_ADDR_SZ 24
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#define CHECK_SUM_FAIL_MSK 0x80000000
|
#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
|
#define CHECK_SUM_FAIL_SFT 31
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#define CHECK_SUM_FAIL_HI 31
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#define CHECK_SUM_FAIL_SZ 1
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#define VERIFY_DATA_MSK 0xffffffff
|
#define VERIFY_DATA_I_MSK 0x00000000
|
#define VERIFY_DATA_SFT 0
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#define VERIFY_DATA_HI 31
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#define VERIFY_DATA_SZ 32
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#define FLASH_ADDR_MSK 0x00ffffff
|
#define FLASH_ADDR_I_MSK 0xff000000
|
#define FLASH_ADDR_SFT 0
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#define FLASH_ADDR_HI 23
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#define FLASH_ADDR_SZ 24
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#define FLASH_CMD_CLR_MSK 0x10000000
|
#define FLASH_CMD_CLR_I_MSK 0xefffffff
|
#define FLASH_CMD_CLR_SFT 28
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#define FLASH_CMD_CLR_HI 28
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#define FLASH_CMD_CLR_SZ 1
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#define FLASH_DMA_CLR_MSK 0x20000000
|
#define FLASH_DMA_CLR_I_MSK 0xdfffffff
|
#define FLASH_DMA_CLR_SFT 29
|
#define FLASH_DMA_CLR_HI 29
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#define FLASH_DMA_CLR_SZ 1
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#define DMA_EN_MSK 0x40000000
|
#define DMA_EN_I_MSK 0xbfffffff
|
#define DMA_EN_SFT 30
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#define DMA_EN_HI 30
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#define DMA_EN_SZ 1
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#define DMA_BUSY_MSK 0x80000000
|
#define DMA_BUSY_I_MSK 0x7fffffff
|
#define DMA_BUSY_SFT 31
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#define DMA_BUSY_HI 31
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#define DMA_BUSY_SZ 1
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#define SRAM_ADDR_MSK 0xffffffff
|
#define SRAM_ADDR_I_MSK 0x00000000
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#define SRAM_ADDR_SFT 0
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#define SRAM_ADDR_HI 31
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#define SRAM_ADDR_SZ 32
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#define FLASH_DMA_LEN_MSK 0xffffffff
|
#define FLASH_DMA_LEN_I_MSK 0x00000000
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#define FLASH_DMA_LEN_SFT 0
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#define FLASH_DMA_LEN_HI 31
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#define FLASH_DMA_LEN_SZ 32
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#define FLASH_FRONT_DLY_MSK 0x0000ffff
|
#define FLASH_FRONT_DLY_I_MSK 0xffff0000
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#define FLASH_FRONT_DLY_SFT 0
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#define FLASH_FRONT_DLY_HI 15
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#define FLASH_FRONT_DLY_SZ 16
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#define FLASH_BACK_DLY_MSK 0xffff0000
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#define FLASH_BACK_DLY_I_MSK 0x0000ffff
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#define FLASH_BACK_DLY_SFT 16
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#define FLASH_BACK_DLY_HI 31
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#define FLASH_BACK_DLY_SZ 16
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#define FLASH_CLK_WIDTH_MSK 0x0000ffff
|
#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
|
#define FLASH_CLK_WIDTH_SFT 0
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#define FLASH_CLK_WIDTH_HI 15
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#define FLASH_CLK_WIDTH_SZ 16
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#define SPI_BUSY_MSK 0x00010000
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#define SPI_BUSY_I_MSK 0xfffeffff
|
#define SPI_BUSY_SFT 16
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#define SPI_BUSY_HI 16
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#define SPI_BUSY_SZ 1
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#define FLS_REMAP_MSK 0x00020000
|
#define FLS_REMAP_I_MSK 0xfffdffff
|
#define FLS_REMAP_SFT 17
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#define FLS_REMAP_HI 17
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#define FLS_REMAP_SZ 1
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#define PBUS_SWP_MSK 0x00040000
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#define PBUS_SWP_I_MSK 0xfffbffff
|
#define PBUS_SWP_SFT 18
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#define PBUS_SWP_HI 18
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#define PBUS_SWP_SZ 1
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#define BIT_MODE1_MSK 0x00080000
|
#define BIT_MODE1_I_MSK 0xfff7ffff
|
#define BIT_MODE1_SFT 19
|
#define BIT_MODE1_HI 19
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#define BIT_MODE1_SZ 1
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#define BIT_MODE2_MSK 0x00100000
|
#define BIT_MODE2_I_MSK 0xffefffff
|
#define BIT_MODE2_SFT 20
|
#define BIT_MODE2_HI 20
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#define BIT_MODE2_SZ 1
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#define BIT_MODE4_MSK 0x00200000
|
#define BIT_MODE4_I_MSK 0xffdfffff
|
#define BIT_MODE4_SFT 21
|
#define BIT_MODE4_HI 21
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#define BIT_MODE4_SZ 1
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#define BOOT_CHECK_SUM_MSK 0xffffffff
|
#define BOOT_CHECK_SUM_I_MSK 0x00000000
|
#define BOOT_CHECK_SUM_SFT 0
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#define BOOT_CHECK_SUM_HI 31
|
#define BOOT_CHECK_SUM_SZ 32
|
#define CHECK_SUM_TAG_MSK 0xffffffff
|
#define CHECK_SUM_TAG_I_MSK 0x00000000
|
#define CHECK_SUM_TAG_SFT 0
|
#define CHECK_SUM_TAG_HI 31
|
#define CHECK_SUM_TAG_SZ 32
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#define CMD_LEN_MSK 0x0000ffff
|
#define CMD_LEN_I_MSK 0xffff0000
|
#define CMD_LEN_SFT 0
|
#define CMD_LEN_HI 15
|
#define CMD_LEN_SZ 16
|
#define CMD_ADDR_MSK 0xffffffff
|
#define CMD_ADDR_I_MSK 0x00000000
|
#define CMD_ADDR_SFT 0
|
#define CMD_ADDR_HI 31
|
#define CMD_ADDR_SZ 32
|
#define DMA_ADR_SRC_MSK 0xffffffff
|
#define DMA_ADR_SRC_I_MSK 0x00000000
|
#define DMA_ADR_SRC_SFT 0
|
#define DMA_ADR_SRC_HI 31
|
#define DMA_ADR_SRC_SZ 32
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#define DMA_ADR_DST_MSK 0xffffffff
|
#define DMA_ADR_DST_I_MSK 0x00000000
|
#define DMA_ADR_DST_SFT 0
|
#define DMA_ADR_DST_HI 31
|
#define DMA_ADR_DST_SZ 32
|
#define DMA_SRC_SIZE_MSK 0x00000007
|
#define DMA_SRC_SIZE_I_MSK 0xfffffff8
|
#define DMA_SRC_SIZE_SFT 0
|
#define DMA_SRC_SIZE_HI 2
|
#define DMA_SRC_SIZE_SZ 3
|
#define DMA_SRC_INC_MSK 0x00000008
|
#define DMA_SRC_INC_I_MSK 0xfffffff7
|
#define DMA_SRC_INC_SFT 3
|
#define DMA_SRC_INC_HI 3
|
#define DMA_SRC_INC_SZ 1
|
#define DMA_DST_SIZE_MSK 0x00000070
|
#define DMA_DST_SIZE_I_MSK 0xffffff8f
|
#define DMA_DST_SIZE_SFT 4
|
#define DMA_DST_SIZE_HI 6
|
#define DMA_DST_SIZE_SZ 3
|
#define DMA_DST_INC_MSK 0x00000080
|
#define DMA_DST_INC_I_MSK 0xffffff7f
|
#define DMA_DST_INC_SFT 7
|
#define DMA_DST_INC_HI 7
|
#define DMA_DST_INC_SZ 1
|
#define DMA_FAST_FILL_MSK 0x00000100
|
#define DMA_FAST_FILL_I_MSK 0xfffffeff
|
#define DMA_FAST_FILL_SFT 8
|
#define DMA_FAST_FILL_HI 8
|
#define DMA_FAST_FILL_SZ 1
|
#define DMA_SDIO_KICK_MSK 0x00001000
|
#define DMA_SDIO_KICK_I_MSK 0xffffefff
|
#define DMA_SDIO_KICK_SFT 12
|
#define DMA_SDIO_KICK_HI 12
|
#define DMA_SDIO_KICK_SZ 1
|
#define DMA_BADR_EN_MSK 0x00002000
|
#define DMA_BADR_EN_I_MSK 0xffffdfff
|
#define DMA_BADR_EN_SFT 13
|
#define DMA_BADR_EN_HI 13
|
#define DMA_BADR_EN_SZ 1
|
#define DMA_LEN_MSK 0xffff0000
|
#define DMA_LEN_I_MSK 0x0000ffff
|
#define DMA_LEN_SFT 16
|
#define DMA_LEN_HI 31
|
#define DMA_LEN_SZ 16
|
#define DMA_INT_MASK_MSK 0x00000001
|
#define DMA_INT_MASK_I_MSK 0xfffffffe
|
#define DMA_INT_MASK_SFT 0
|
#define DMA_INT_MASK_HI 0
|
#define DMA_INT_MASK_SZ 1
|
#define DMA_STS_MSK 0x00000100
|
#define DMA_STS_I_MSK 0xfffffeff
|
#define DMA_STS_SFT 8
|
#define DMA_STS_HI 8
|
#define DMA_STS_SZ 1
|
#define DMA_FINISH_MSK 0x80000000
|
#define DMA_FINISH_I_MSK 0x7fffffff
|
#define DMA_FINISH_SFT 31
|
#define DMA_FINISH_HI 31
|
#define DMA_FINISH_SZ 1
|
#define DMA_CONST_MSK 0xffffffff
|
#define DMA_CONST_I_MSK 0x00000000
|
#define DMA_CONST_SFT 0
|
#define DMA_CONST_HI 31
|
#define DMA_CONST_SZ 32
|
#define SLEEP_WAKE_CNT_MSK 0x00ffffff
|
#define SLEEP_WAKE_CNT_I_MSK 0xff000000
|
#define SLEEP_WAKE_CNT_SFT 0
|
#define SLEEP_WAKE_CNT_HI 23
|
#define SLEEP_WAKE_CNT_SZ 24
|
#define RG_DLDO_LEVEL_MSK 0x07000000
|
#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
|
#define RG_DLDO_LEVEL_SFT 24
|
#define RG_DLDO_LEVEL_HI 26
|
#define RG_DLDO_LEVEL_SZ 3
|
#define RG_DLDO_BOOST_IQ_MSK 0x08000000
|
#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
|
#define RG_DLDO_BOOST_IQ_SFT 27
|
#define RG_DLDO_BOOST_IQ_HI 27
|
#define RG_DLDO_BOOST_IQ_SZ 1
|
#define RG_BUCK_LEVEL_MSK 0x70000000
|
#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
|
#define RG_BUCK_LEVEL_SFT 28
|
#define RG_BUCK_LEVEL_HI 30
|
#define RG_BUCK_LEVEL_SZ 3
|
#define RG_BUCK_VREF_SEL_MSK 0x80000000
|
#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
|
#define RG_BUCK_VREF_SEL_SFT 31
|
#define RG_BUCK_VREF_SEL_HI 31
|
#define RG_BUCK_VREF_SEL_SZ 1
|
#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
|
#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
|
#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
|
#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
|
#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
|
#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
|
#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
|
#define RG_RTC_OSC_RES_SW_SFT 16
|
#define RG_RTC_OSC_RES_SW_HI 25
|
#define RG_RTC_OSC_RES_SW_SZ 10
|
#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
|
#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
|
#define RTC_OSC_CAL_RES_RDY_SFT 31
|
#define RTC_OSC_CAL_RES_RDY_HI 31
|
#define RTC_OSC_CAL_RES_RDY_SZ 1
|
#define RG_DCDC_MODE_MSK 0x00000001
|
#define RG_DCDC_MODE_I_MSK 0xfffffffe
|
#define RG_DCDC_MODE_SFT 0
|
#define RG_DCDC_MODE_HI 0
|
#define RG_DCDC_MODE_SZ 1
|
#define RG_BUCK_EN_PSM_MSK 0x00000010
|
#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
|
#define RG_BUCK_EN_PSM_SFT 4
|
#define RG_BUCK_EN_PSM_HI 4
|
#define RG_BUCK_EN_PSM_SZ 1
|
#define RG_BUCK_PSM_VTH_MSK 0x00000100
|
#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
|
#define RG_BUCK_PSM_VTH_SFT 8
|
#define RG_BUCK_PSM_VTH_HI 8
|
#define RG_BUCK_PSM_VTH_SZ 1
|
#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
|
#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
|
#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
|
#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
|
#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
|
#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
|
#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
|
#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
|
#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
|
#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
|
#define RTC_CAL_ENA_MSK 0x00010000
|
#define RTC_CAL_ENA_I_MSK 0xfffeffff
|
#define RTC_CAL_ENA_SFT 16
|
#define RTC_CAL_ENA_HI 16
|
#define RTC_CAL_ENA_SZ 1
|
#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
|
#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
|
#define PMU_WAKE_TRIG_EVENT_SFT 0
|
#define PMU_WAKE_TRIG_EVENT_HI 1
|
#define PMU_WAKE_TRIG_EVENT_SZ 2
|
#define DIGI_TOP_POR_MASK_MSK 0x00000010
|
#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
|
#define DIGI_TOP_POR_MASK_SFT 4
|
#define DIGI_TOP_POR_MASK_HI 4
|
#define DIGI_TOP_POR_MASK_SZ 1
|
#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
|
#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
|
#define PMU_ENTER_SLEEP_MODE_SFT 8
|
#define PMU_ENTER_SLEEP_MODE_HI 8
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#define PMU_ENTER_SLEEP_MODE_SZ 1
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#define RG_RTC_DUMMIES_MSK 0xffff0000
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#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
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#define RG_RTC_DUMMIES_SFT 16
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#define RG_RTC_DUMMIES_HI 31
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#define RG_RTC_DUMMIES_SZ 16
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#define RTC_EN_MSK 0x00000001
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#define RTC_EN_I_MSK 0xfffffffe
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#define RTC_EN_SFT 0
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#define RTC_EN_HI 0
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#define RTC_EN_SZ 1
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#define RTC_SRC_MSK 0x00000002
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#define RTC_SRC_I_MSK 0xfffffffd
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#define RTC_SRC_SFT 1
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#define RTC_SRC_HI 1
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#define RTC_SRC_SZ 1
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#define RTC_TICK_CNT_MSK 0x7fff0000
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#define RTC_TICK_CNT_I_MSK 0x8000ffff
|
#define RTC_TICK_CNT_SFT 16
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#define RTC_TICK_CNT_HI 30
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#define RTC_TICK_CNT_SZ 15
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#define RTC_INT_SEC_MASK_MSK 0x00000001
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#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
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#define RTC_INT_SEC_MASK_SFT 0
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#define RTC_INT_SEC_MASK_HI 0
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#define RTC_INT_SEC_MASK_SZ 1
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#define RTC_INT_ALARM_MASK_MSK 0x00000002
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#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
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#define RTC_INT_ALARM_MASK_SFT 1
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#define RTC_INT_ALARM_MASK_HI 1
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#define RTC_INT_ALARM_MASK_SZ 1
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#define RTC_INT_SEC_MSK 0x00010000
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#define RTC_INT_SEC_I_MSK 0xfffeffff
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#define RTC_INT_SEC_SFT 16
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#define RTC_INT_SEC_HI 16
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#define RTC_INT_SEC_SZ 1
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#define RTC_INT_ALARM_MSK 0x00020000
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#define RTC_INT_ALARM_I_MSK 0xfffdffff
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#define RTC_INT_ALARM_SFT 17
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#define RTC_INT_ALARM_HI 17
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#define RTC_INT_ALARM_SZ 1
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#define RTC_SEC_START_CNT_MSK 0xffffffff
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#define RTC_SEC_START_CNT_I_MSK 0x00000000
|
#define RTC_SEC_START_CNT_SFT 0
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#define RTC_SEC_START_CNT_HI 31
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#define RTC_SEC_START_CNT_SZ 32
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#define RTC_SEC_CNT_MSK 0xffffffff
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#define RTC_SEC_CNT_I_MSK 0x00000000
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#define RTC_SEC_CNT_SFT 0
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#define RTC_SEC_CNT_HI 31
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#define RTC_SEC_CNT_SZ 32
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#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
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#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
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#define RTC_SEC_ALARM_VALUE_SFT 0
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#define RTC_SEC_ALARM_VALUE_HI 31
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#define RTC_SEC_ALARM_VALUE_SZ 32
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#define D2_DMA_ADR_SRC_MSK 0xffffffff
|
#define D2_DMA_ADR_SRC_I_MSK 0x00000000
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#define D2_DMA_ADR_SRC_SFT 0
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#define D2_DMA_ADR_SRC_HI 31
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#define D2_DMA_ADR_SRC_SZ 32
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#define D2_DMA_ADR_DST_MSK 0xffffffff
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#define D2_DMA_ADR_DST_I_MSK 0x00000000
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#define D2_DMA_ADR_DST_SFT 0
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#define D2_DMA_ADR_DST_HI 31
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#define D2_DMA_ADR_DST_SZ 32
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#define D2_DMA_SRC_SIZE_MSK 0x00000007
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#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
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#define D2_DMA_SRC_SIZE_SFT 0
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#define D2_DMA_SRC_SIZE_HI 2
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#define D2_DMA_SRC_SIZE_SZ 3
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#define D2_DMA_SRC_INC_MSK 0x00000008
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#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
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#define D2_DMA_SRC_INC_SFT 3
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#define D2_DMA_SRC_INC_HI 3
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#define D2_DMA_SRC_INC_SZ 1
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#define D2_DMA_DST_SIZE_MSK 0x00000070
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#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
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#define D2_DMA_DST_SIZE_SFT 4
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#define D2_DMA_DST_SIZE_HI 6
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#define D2_DMA_DST_SIZE_SZ 3
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#define D2_DMA_DST_INC_MSK 0x00000080
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#define D2_DMA_DST_INC_I_MSK 0xffffff7f
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#define D2_DMA_DST_INC_SFT 7
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#define D2_DMA_DST_INC_HI 7
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#define D2_DMA_DST_INC_SZ 1
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#define D2_DMA_FAST_FILL_MSK 0x00000100
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#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
|
#define D2_DMA_FAST_FILL_SFT 8
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#define D2_DMA_FAST_FILL_HI 8
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#define D2_DMA_FAST_FILL_SZ 1
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#define D2_DMA_SDIO_KICK_MSK 0x00001000
|
#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
|
#define D2_DMA_SDIO_KICK_SFT 12
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#define D2_DMA_SDIO_KICK_HI 12
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#define D2_DMA_SDIO_KICK_SZ 1
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#define D2_DMA_BADR_EN_MSK 0x00002000
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#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
|
#define D2_DMA_BADR_EN_SFT 13
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#define D2_DMA_BADR_EN_HI 13
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#define D2_DMA_BADR_EN_SZ 1
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#define D2_DMA_LEN_MSK 0xffff0000
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#define D2_DMA_LEN_I_MSK 0x0000ffff
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#define D2_DMA_LEN_SFT 16
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#define D2_DMA_LEN_HI 31
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#define D2_DMA_LEN_SZ 16
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#define D2_DMA_INT_MASK_MSK 0x00000001
|
#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
|
#define D2_DMA_INT_MASK_SFT 0
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#define D2_DMA_INT_MASK_HI 0
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#define D2_DMA_INT_MASK_SZ 1
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#define D2_DMA_STS_MSK 0x00000100
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#define D2_DMA_STS_I_MSK 0xfffffeff
|
#define D2_DMA_STS_SFT 8
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#define D2_DMA_STS_HI 8
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#define D2_DMA_STS_SZ 1
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#define D2_DMA_FINISH_MSK 0x80000000
|
#define D2_DMA_FINISH_I_MSK 0x7fffffff
|
#define D2_DMA_FINISH_SFT 31
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#define D2_DMA_FINISH_HI 31
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#define D2_DMA_FINISH_SZ 1
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#define D2_DMA_CONST_MSK 0xffffffff
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#define D2_DMA_CONST_I_MSK 0x00000000
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#define D2_DMA_CONST_SFT 0
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#define D2_DMA_CONST_HI 31
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#define D2_DMA_CONST_SZ 32
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#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
|
#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
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#define TRAP_UNKNOWN_TYPE_SFT 0
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#define TRAP_UNKNOWN_TYPE_HI 0
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#define TRAP_UNKNOWN_TYPE_SZ 1
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#define TX_ON_DEMAND_ENA_MSK 0x00000002
|
#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
|
#define TX_ON_DEMAND_ENA_SFT 1
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#define TX_ON_DEMAND_ENA_HI 1
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#define TX_ON_DEMAND_ENA_SZ 1
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#define RX_2_HOST_MSK 0x00000004
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#define RX_2_HOST_I_MSK 0xfffffffb
|
#define RX_2_HOST_SFT 2
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#define RX_2_HOST_HI 2
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#define RX_2_HOST_SZ 1
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#define AUTO_SEQNO_MSK 0x00000008
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#define AUTO_SEQNO_I_MSK 0xfffffff7
|
#define AUTO_SEQNO_SFT 3
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#define AUTO_SEQNO_HI 3
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#define AUTO_SEQNO_SZ 1
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#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
|
#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
|
#define BYPASSS_TX_PARSER_ENCAP_SFT 4
|
#define BYPASSS_TX_PARSER_ENCAP_HI 4
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#define BYPASSS_TX_PARSER_ENCAP_SZ 1
|
#define HDR_STRIP_MSK 0x00000020
|
#define HDR_STRIP_I_MSK 0xffffffdf
|
#define HDR_STRIP_SFT 5
|
#define HDR_STRIP_HI 5
|
#define HDR_STRIP_SZ 1
|
#define ERP_PROTECT_MSK 0x000000c0
|
#define ERP_PROTECT_I_MSK 0xffffff3f
|
#define ERP_PROTECT_SFT 6
|
#define ERP_PROTECT_HI 7
|
#define ERP_PROTECT_SZ 2
|
#define PRO_VER_MSK 0x00000300
|
#define PRO_VER_I_MSK 0xfffffcff
|
#define PRO_VER_SFT 8
|
#define PRO_VER_HI 9
|
#define PRO_VER_SZ 2
|
#define TXQ_ID0_MSK 0x00007000
|
#define TXQ_ID0_I_MSK 0xffff8fff
|
#define TXQ_ID0_SFT 12
|
#define TXQ_ID0_HI 14
|
#define TXQ_ID0_SZ 3
|
#define TXQ_ID1_MSK 0x00070000
|
#define TXQ_ID1_I_MSK 0xfff8ffff
|
#define TXQ_ID1_SFT 16
|
#define TXQ_ID1_HI 18
|
#define TXQ_ID1_SZ 3
|
#define TX_ETHER_TRAP_EN_MSK 0x00100000
|
#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
|
#define TX_ETHER_TRAP_EN_SFT 20
|
#define TX_ETHER_TRAP_EN_HI 20
|
#define TX_ETHER_TRAP_EN_SZ 1
|
#define RX_ETHER_TRAP_EN_MSK 0x00200000
|
#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
|
#define RX_ETHER_TRAP_EN_SFT 21
|
#define RX_ETHER_TRAP_EN_HI 21
|
#define RX_ETHER_TRAP_EN_SZ 1
|
#define RX_NULL_TRAP_EN_MSK 0x00400000
|
#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
|
#define RX_NULL_TRAP_EN_SFT 22
|
#define RX_NULL_TRAP_EN_HI 22
|
#define RX_NULL_TRAP_EN_SZ 1
|
#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
|
#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
|
#define RX_GET_TX_QUEUE_EN_SFT 25
|
#define RX_GET_TX_QUEUE_EN_HI 25
|
#define RX_GET_TX_QUEUE_EN_SZ 1
|
#define HCI_INQ_SEL_MSK 0x04000000
|
#define HCI_INQ_SEL_I_MSK 0xfbffffff
|
#define HCI_INQ_SEL_SFT 26
|
#define HCI_INQ_SEL_HI 26
|
#define HCI_INQ_SEL_SZ 1
|
#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
|
#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
|
#define TRX_DEBUG_CNT_ENA_SFT 28
|
#define TRX_DEBUG_CNT_ENA_HI 28
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#define TRX_DEBUG_CNT_ENA_SZ 1
|
#define WAKE_SOON_WITH_SCK_MSK 0x00000001
|
#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
|
#define WAKE_SOON_WITH_SCK_SFT 0
|
#define WAKE_SOON_WITH_SCK_HI 0
|
#define WAKE_SOON_WITH_SCK_SZ 1
|
#define TX_FLOW_CTRL_MSK 0x0000ffff
|
#define TX_FLOW_CTRL_I_MSK 0xffff0000
|
#define TX_FLOW_CTRL_SFT 0
|
#define TX_FLOW_CTRL_HI 15
|
#define TX_FLOW_CTRL_SZ 16
|
#define TX_FLOW_MGMT_MSK 0xffff0000
|
#define TX_FLOW_MGMT_I_MSK 0x0000ffff
|
#define TX_FLOW_MGMT_SFT 16
|
#define TX_FLOW_MGMT_HI 31
|
#define TX_FLOW_MGMT_SZ 16
|
#define TX_FLOW_DATA_MSK 0xffffffff
|
#define TX_FLOW_DATA_I_MSK 0x00000000
|
#define TX_FLOW_DATA_SFT 0
|
#define TX_FLOW_DATA_HI 31
|
#define TX_FLOW_DATA_SZ 32
|
#define DOT11RTSTHRESHOLD_MSK 0xffff0000
|
#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
|
#define DOT11RTSTHRESHOLD_SFT 16
|
#define DOT11RTSTHRESHOLD_HI 31
|
#define DOT11RTSTHRESHOLD_SZ 16
|
#define TXF_ID_MSK 0x0000003f
|
#define TXF_ID_I_MSK 0xffffffc0
|
#define TXF_ID_SFT 0
|
#define TXF_ID_HI 5
|
#define TXF_ID_SZ 6
|
#define SEQ_CTRL_MSK 0x0000ffff
|
#define SEQ_CTRL_I_MSK 0xffff0000
|
#define SEQ_CTRL_SFT 0
|
#define SEQ_CTRL_HI 15
|
#define SEQ_CTRL_SZ 16
|
#define TX_PBOFFSET_MSK 0x000000ff
|
#define TX_PBOFFSET_I_MSK 0xffffff00
|
#define TX_PBOFFSET_SFT 0
|
#define TX_PBOFFSET_HI 7
|
#define TX_PBOFFSET_SZ 8
|
#define TX_INFO_SIZE_MSK 0x0000ff00
|
#define TX_INFO_SIZE_I_MSK 0xffff00ff
|
#define TX_INFO_SIZE_SFT 8
|
#define TX_INFO_SIZE_HI 15
|
#define TX_INFO_SIZE_SZ 8
|
#define RX_INFO_SIZE_MSK 0x00ff0000
|
#define RX_INFO_SIZE_I_MSK 0xff00ffff
|
#define RX_INFO_SIZE_SFT 16
|
#define RX_INFO_SIZE_HI 23
|
#define RX_INFO_SIZE_SZ 8
|
#define RX_LAST_PHY_SIZE_MSK 0xff000000
|
#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
|
#define RX_LAST_PHY_SIZE_SFT 24
|
#define RX_LAST_PHY_SIZE_HI 31
|
#define RX_LAST_PHY_SIZE_SZ 8
|
#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
|
#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
|
#define TX_INFO_CLEAR_SIZE_SFT 0
|
#define TX_INFO_CLEAR_SIZE_HI 5
|
#define TX_INFO_CLEAR_SIZE_SZ 6
|
#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
|
#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
|
#define TX_INFO_CLEAR_ENABLE_SFT 8
|
#define TX_INFO_CLEAR_ENABLE_HI 8
|
#define TX_INFO_CLEAR_ENABLE_SZ 1
|
#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
|
#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
|
#define TXTRAP_ETHTYPE1_SFT 0
|
#define TXTRAP_ETHTYPE1_HI 15
|
#define TXTRAP_ETHTYPE1_SZ 16
|
#define TXTRAP_ETHTYPE0_MSK 0xffff0000
|
#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
|
#define TXTRAP_ETHTYPE0_SFT 16
|
#define TXTRAP_ETHTYPE0_HI 31
|
#define TXTRAP_ETHTYPE0_SZ 16
|
#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
|
#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
|
#define RXTRAP_ETHTYPE1_SFT 0
|
#define RXTRAP_ETHTYPE1_HI 15
|
#define RXTRAP_ETHTYPE1_SZ 16
|
#define RXTRAP_ETHTYPE0_MSK 0xffff0000
|
#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
|
#define RXTRAP_ETHTYPE0_SFT 16
|
#define RXTRAP_ETHTYPE0_HI 31
|
#define RXTRAP_ETHTYPE0_SZ 16
|
#define TX_PKT_COUNTER_MSK 0xffffffff
|
#define TX_PKT_COUNTER_I_MSK 0x00000000
|
#define TX_PKT_COUNTER_SFT 0
|
#define TX_PKT_COUNTER_HI 31
|
#define TX_PKT_COUNTER_SZ 32
|
#define RX_PKT_COUNTER_MSK 0xffffffff
|
#define RX_PKT_COUNTER_I_MSK 0x00000000
|
#define RX_PKT_COUNTER_SFT 0
|
#define RX_PKT_COUNTER_HI 31
|
#define RX_PKT_COUNTER_SZ 32
|
#define HOST_CMD_COUNTER_MSK 0x000000ff
|
#define HOST_CMD_COUNTER_I_MSK 0xffffff00
|
#define HOST_CMD_COUNTER_SFT 0
|
#define HOST_CMD_COUNTER_HI 7
|
#define HOST_CMD_COUNTER_SZ 8
|
#define HOST_EVENT_COUNTER_MSK 0x000000ff
|
#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
|
#define HOST_EVENT_COUNTER_SFT 0
|
#define HOST_EVENT_COUNTER_HI 7
|
#define HOST_EVENT_COUNTER_SZ 8
|
#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
|
#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
|
#define TX_PKT_DROP_COUNTER_SFT 0
|
#define TX_PKT_DROP_COUNTER_HI 7
|
#define TX_PKT_DROP_COUNTER_SZ 8
|
#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
|
#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
|
#define RX_PKT_DROP_COUNTER_SFT 0
|
#define RX_PKT_DROP_COUNTER_HI 7
|
#define RX_PKT_DROP_COUNTER_SZ 8
|
#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
|
#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
|
#define TX_PKT_TRAP_COUNTER_SFT 0
|
#define TX_PKT_TRAP_COUNTER_HI 7
|
#define TX_PKT_TRAP_COUNTER_SZ 8
|
#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
|
#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
|
#define RX_PKT_TRAP_COUNTER_SFT 0
|
#define RX_PKT_TRAP_COUNTER_HI 7
|
#define RX_PKT_TRAP_COUNTER_SZ 8
|
#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
|
#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
|
#define HOST_TX_FAIL_COUNTER_SFT 0
|
#define HOST_TX_FAIL_COUNTER_HI 7
|
#define HOST_TX_FAIL_COUNTER_SZ 8
|
#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
|
#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
|
#define HOST_RX_FAIL_COUNTER_SFT 0
|
#define HOST_RX_FAIL_COUNTER_HI 7
|
#define HOST_RX_FAIL_COUNTER_SZ 8
|
#define HCI_STATE_MONITOR_MSK 0xffffffff
|
#define HCI_STATE_MONITOR_I_MSK 0x00000000
|
#define HCI_STATE_MONITOR_SFT 0
|
#define HCI_STATE_MONITOR_HI 31
|
#define HCI_STATE_MONITOR_SZ 32
|
#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
|
#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
|
#define HCI_ST_TIMEOUT_MONITOR_SFT 0
|
#define HCI_ST_TIMEOUT_MONITOR_HI 31
|
#define HCI_ST_TIMEOUT_MONITOR_SZ 32
|
#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
|
#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
|
#define TX_ON_DEMAND_LENGTH_SFT 0
|
#define TX_ON_DEMAND_LENGTH_HI 31
|
#define TX_ON_DEMAND_LENGTH_SZ 32
|
#define HCI_MONITOR_REG1_MSK 0xffffffff
|
#define HCI_MONITOR_REG1_I_MSK 0x00000000
|
#define HCI_MONITOR_REG1_SFT 0
|
#define HCI_MONITOR_REG1_HI 31
|
#define HCI_MONITOR_REG1_SZ 32
|
#define HCI_MONITOR_REG2_MSK 0xffffffff
|
#define HCI_MONITOR_REG2_I_MSK 0x00000000
|
#define HCI_MONITOR_REG2_SFT 0
|
#define HCI_MONITOR_REG2_HI 31
|
#define HCI_MONITOR_REG2_SZ 32
|
#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
|
#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
|
#define HCI_TX_ALLOC_TIME_31_0_SFT 0
|
#define HCI_TX_ALLOC_TIME_31_0_HI 31
|
#define HCI_TX_ALLOC_TIME_31_0_SZ 32
|
#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
|
#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
|
#define HCI_TX_ALLOC_TIME_47_32_SFT 0
|
#define HCI_TX_ALLOC_TIME_47_32_HI 15
|
#define HCI_TX_ALLOC_TIME_47_32_SZ 16
|
#define HCI_MB_MAX_CNT_MSK 0x00ff0000
|
#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
|
#define HCI_MB_MAX_CNT_SFT 16
|
#define HCI_MB_MAX_CNT_HI 23
|
#define HCI_MB_MAX_CNT_SZ 8
|
#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
|
#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
|
#define HCI_TX_ALLOC_CNT_31_0_SFT 0
|
#define HCI_TX_ALLOC_CNT_31_0_HI 31
|
#define HCI_TX_ALLOC_CNT_31_0_SZ 32
|
#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
|
#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
|
#define HCI_TX_ALLOC_CNT_47_32_SFT 0
|
#define HCI_TX_ALLOC_CNT_47_32_HI 15
|
#define HCI_TX_ALLOC_CNT_47_32_SZ 16
|
#define HCI_PROC_CNT_MSK 0x00ff0000
|
#define HCI_PROC_CNT_I_MSK 0xff00ffff
|
#define HCI_PROC_CNT_SFT 16
|
#define HCI_PROC_CNT_HI 23
|
#define HCI_PROC_CNT_SZ 8
|
#define SDIO_TRANS_CNT_MSK 0xff000000
|
#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
|
#define SDIO_TRANS_CNT_SFT 24
|
#define SDIO_TRANS_CNT_HI 31
|
#define SDIO_TRANS_CNT_SZ 8
|
#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
|
#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
|
#define SDIO_TX_INVALID_CNT_31_0_SFT 0
|
#define SDIO_TX_INVALID_CNT_31_0_HI 31
|
#define SDIO_TX_INVALID_CNT_31_0_SZ 32
|
#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
|
#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
|
#define SDIO_TX_INVALID_CNT_47_32_SFT 0
|
#define SDIO_TX_INVALID_CNT_47_32_HI 15
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#define SDIO_TX_INVALID_CNT_47_32_SZ 16
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#define CS_START_ADDR_MSK 0x0000ffff
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#define CS_START_ADDR_I_MSK 0xffff0000
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#define CS_START_ADDR_SFT 0
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#define CS_START_ADDR_HI 15
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#define CS_START_ADDR_SZ 16
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#define CS_PKT_ID_MSK 0x007f0000
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#define CS_PKT_ID_I_MSK 0xff80ffff
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#define CS_PKT_ID_SFT 16
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#define CS_PKT_ID_HI 22
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#define CS_PKT_ID_SZ 7
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#define ADD_LEN_MSK 0x0000ffff
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#define ADD_LEN_I_MSK 0xffff0000
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#define ADD_LEN_SFT 0
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#define ADD_LEN_HI 15
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#define ADD_LEN_SZ 16
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#define CS_ADDER_EN_MSK 0x00000001
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#define CS_ADDER_EN_I_MSK 0xfffffffe
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#define CS_ADDER_EN_SFT 0
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#define CS_ADDER_EN_HI 0
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#define CS_ADDER_EN_SZ 1
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#define PSEUDO_MSK 0x00000002
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#define PSEUDO_I_MSK 0xfffffffd
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#define PSEUDO_SFT 1
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#define PSEUDO_HI 1
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#define PSEUDO_SZ 1
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#define CALCULATE_MSK 0xffffffff
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#define CALCULATE_I_MSK 0x00000000
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#define CALCULATE_SFT 0
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#define CALCULATE_HI 31
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#define CALCULATE_SZ 32
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#define L4_LEN_MSK 0x0000ffff
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#define L4_LEN_I_MSK 0xffff0000
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#define L4_LEN_SFT 0
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#define L4_LEN_HI 15
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#define L4_LEN_SZ 16
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#define L4_PROTOL_MSK 0x00ff0000
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#define L4_PROTOL_I_MSK 0xff00ffff
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#define L4_PROTOL_SFT 16
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#define L4_PROTOL_HI 23
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#define L4_PROTOL_SZ 8
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#define CHECK_SUM_MSK 0x0000ffff
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#define CHECK_SUM_I_MSK 0xffff0000
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#define CHECK_SUM_SFT 0
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#define CHECK_SUM_HI 15
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#define CHECK_SUM_SZ 16
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#define RAND_EN_MSK 0x00000001
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#define RAND_EN_I_MSK 0xfffffffe
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#define RAND_EN_SFT 0
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#define RAND_EN_HI 0
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#define RAND_EN_SZ 1
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#define RAND_NUM_MSK 0xffffffff
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#define RAND_NUM_I_MSK 0x00000000
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#define RAND_NUM_SFT 0
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#define RAND_NUM_HI 31
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#define RAND_NUM_SZ 32
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#define MUL_OP1_MSK 0xffffffff
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#define MUL_OP1_I_MSK 0x00000000
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#define MUL_OP1_SFT 0
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#define MUL_OP1_HI 31
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#define MUL_OP1_SZ 32
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#define MUL_OP2_MSK 0xffffffff
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#define MUL_OP2_I_MSK 0x00000000
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#define MUL_OP2_SFT 0
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#define MUL_OP2_HI 31
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#define MUL_OP2_SZ 32
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#define MUL_ANS0_MSK 0xffffffff
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#define MUL_ANS0_I_MSK 0x00000000
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#define MUL_ANS0_SFT 0
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#define MUL_ANS0_HI 31
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#define MUL_ANS0_SZ 32
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#define MUL_ANS1_MSK 0xffffffff
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#define MUL_ANS1_I_MSK 0x00000000
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#define MUL_ANS1_SFT 0
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#define MUL_ANS1_HI 31
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#define MUL_ANS1_SZ 32
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#define RD_ADDR_MSK 0x0000ffff
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#define RD_ADDR_I_MSK 0xffff0000
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#define RD_ADDR_SFT 0
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#define RD_ADDR_HI 15
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#define RD_ADDR_SZ 16
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#define RD_ID_MSK 0x007f0000
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#define RD_ID_I_MSK 0xff80ffff
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#define RD_ID_SFT 16
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#define RD_ID_HI 22
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#define RD_ID_SZ 7
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#define WR_ADDR_MSK 0x0000ffff
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#define WR_ADDR_I_MSK 0xffff0000
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#define WR_ADDR_SFT 0
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#define WR_ADDR_HI 15
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#define WR_ADDR_SZ 16
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#define WR_ID_MSK 0x007f0000
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#define WR_ID_I_MSK 0xff80ffff
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#define WR_ID_SFT 16
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#define WR_ID_HI 22
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#define WR_ID_SZ 7
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#define LEN_MSK 0x0000ffff
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#define LEN_I_MSK 0xffff0000
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#define LEN_SFT 0
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#define LEN_HI 15
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#define LEN_SZ 16
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#define CLR_MSK 0x00000001
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#define CLR_I_MSK 0xfffffffe
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#define CLR_SFT 0
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#define CLR_HI 0
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#define CLR_SZ 1
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#define PHY_MODE_MSK 0x00000003
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#define PHY_MODE_I_MSK 0xfffffffc
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#define PHY_MODE_SFT 0
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#define PHY_MODE_HI 1
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#define PHY_MODE_SZ 2
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#define SHRT_PREAM_MSK 0x00000004
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#define SHRT_PREAM_I_MSK 0xfffffffb
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#define SHRT_PREAM_SFT 2
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#define SHRT_PREAM_HI 2
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#define SHRT_PREAM_SZ 1
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#define SHRT_GI_MSK 0x00000008
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#define SHRT_GI_I_MSK 0xfffffff7
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#define SHRT_GI_SFT 3
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#define SHRT_GI_HI 3
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#define SHRT_GI_SZ 1
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#define DATA_RATE_MSK 0x000007f0
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#define DATA_RATE_I_MSK 0xfffff80f
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#define DATA_RATE_SFT 4
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#define DATA_RATE_HI 10
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#define DATA_RATE_SZ 7
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#define MCS_MSK 0x00007000
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#define MCS_I_MSK 0xffff8fff
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#define MCS_SFT 12
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#define MCS_HI 14
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#define MCS_SZ 3
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#define FRAME_LEN_MSK 0xffff0000
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#define FRAME_LEN_I_MSK 0x0000ffff
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#define FRAME_LEN_SFT 16
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#define FRAME_LEN_HI 31
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#define FRAME_LEN_SZ 16
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#define DURATION_MSK 0x0000ffff
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#define DURATION_I_MSK 0xffff0000
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#define DURATION_SFT 0
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#define DURATION_HI 15
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#define DURATION_SZ 16
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#define SHA_DST_ADDR_MSK 0xffffffff
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#define SHA_DST_ADDR_I_MSK 0x00000000
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#define SHA_DST_ADDR_SFT 0
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#define SHA_DST_ADDR_HI 31
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#define SHA_DST_ADDR_SZ 32
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#define SHA_SRC_ADDR_MSK 0xffffffff
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#define SHA_SRC_ADDR_I_MSK 0x00000000
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#define SHA_SRC_ADDR_SFT 0
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#define SHA_SRC_ADDR_HI 31
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#define SHA_SRC_ADDR_SZ 32
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#define SHA_BUSY_MSK 0x00000001
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#define SHA_BUSY_I_MSK 0xfffffffe
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#define SHA_BUSY_SFT 0
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#define SHA_BUSY_HI 0
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#define SHA_BUSY_SZ 1
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#define SHA_ENDIAN_MSK 0x00000002
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#define SHA_ENDIAN_I_MSK 0xfffffffd
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#define SHA_ENDIAN_SFT 1
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#define SHA_ENDIAN_HI 1
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#define SHA_ENDIAN_SZ 1
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#define EFS_CLKFREQ_MSK 0x00000fff
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#define EFS_CLKFREQ_I_MSK 0xfffff000
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#define EFS_CLKFREQ_SFT 0
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#define EFS_CLKFREQ_HI 11
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#define EFS_CLKFREQ_SZ 12
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#define LOW_ACTIVE_MSK 0x00010000
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#define LOW_ACTIVE_I_MSK 0xfffeffff
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#define LOW_ACTIVE_SFT 16
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#define LOW_ACTIVE_HI 16
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#define LOW_ACTIVE_SZ 1
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#define EFS_CLKFREQ_RD_MSK 0x0ff00000
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#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
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#define EFS_CLKFREQ_RD_SFT 20
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#define EFS_CLKFREQ_RD_HI 27
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#define EFS_CLKFREQ_RD_SZ 8
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#define EFS_PRE_RD_MSK 0xf0000000
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#define EFS_PRE_RD_I_MSK 0x0fffffff
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#define EFS_PRE_RD_SFT 28
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#define EFS_PRE_RD_HI 31
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#define EFS_PRE_RD_SZ 4
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#define EFS_LDO_ON_MSK 0x0000ffff
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#define EFS_LDO_ON_I_MSK 0xffff0000
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#define EFS_LDO_ON_SFT 0
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#define EFS_LDO_ON_HI 15
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#define EFS_LDO_ON_SZ 16
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#define EFS_LDO_OFF_MSK 0xffff0000
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#define EFS_LDO_OFF_I_MSK 0x0000ffff
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#define EFS_LDO_OFF_SFT 16
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#define EFS_LDO_OFF_HI 31
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#define EFS_LDO_OFF_SZ 16
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#define EFS_RDATA_0_MSK 0xffffffff
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#define EFS_RDATA_0_I_MSK 0x00000000
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#define EFS_RDATA_0_SFT 0
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#define EFS_RDATA_0_HI 31
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#define EFS_RDATA_0_SZ 32
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#define EFS_WDATA_0_MSK 0xffffffff
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#define EFS_WDATA_0_I_MSK 0x00000000
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#define EFS_WDATA_0_SFT 0
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#define EFS_WDATA_0_HI 31
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#define EFS_WDATA_0_SZ 32
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#define EFS_RDATA_1_MSK 0xffffffff
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#define EFS_RDATA_1_I_MSK 0x00000000
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#define EFS_RDATA_1_SFT 0
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#define EFS_RDATA_1_HI 31
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#define EFS_RDATA_1_SZ 32
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#define EFS_WDATA_1_MSK 0xffffffff
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#define EFS_WDATA_1_I_MSK 0x00000000
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#define EFS_WDATA_1_SFT 0
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#define EFS_WDATA_1_HI 31
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#define EFS_WDATA_1_SZ 32
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#define EFS_RDATA_2_MSK 0xffffffff
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#define EFS_RDATA_2_I_MSK 0x00000000
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#define EFS_RDATA_2_SFT 0
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#define EFS_RDATA_2_HI 31
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#define EFS_RDATA_2_SZ 32
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#define EFS_WDATA_2_MSK 0xffffffff
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#define EFS_WDATA_2_I_MSK 0x00000000
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#define EFS_WDATA_2_SFT 0
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#define EFS_WDATA_2_HI 31
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#define EFS_WDATA_2_SZ 32
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#define EFS_RDATA_3_MSK 0xffffffff
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#define EFS_RDATA_3_I_MSK 0x00000000
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#define EFS_RDATA_3_SFT 0
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#define EFS_RDATA_3_HI 31
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#define EFS_RDATA_3_SZ 32
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#define EFS_WDATA_3_MSK 0xffffffff
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#define EFS_WDATA_3_I_MSK 0x00000000
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#define EFS_WDATA_3_SFT 0
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#define EFS_WDATA_3_HI 31
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#define EFS_WDATA_3_SZ 32
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#define EFS_RDATA_4_MSK 0xffffffff
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#define EFS_RDATA_4_I_MSK 0x00000000
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#define EFS_RDATA_4_SFT 0
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#define EFS_RDATA_4_HI 31
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#define EFS_RDATA_4_SZ 32
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#define EFS_WDATA_4_MSK 0xffffffff
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#define EFS_WDATA_4_I_MSK 0x00000000
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#define EFS_WDATA_4_SFT 0
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#define EFS_WDATA_4_HI 31
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#define EFS_WDATA_4_SZ 32
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#define EFS_RDATA_5_MSK 0xffffffff
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#define EFS_RDATA_5_I_MSK 0x00000000
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#define EFS_RDATA_5_SFT 0
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#define EFS_RDATA_5_HI 31
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#define EFS_RDATA_5_SZ 32
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#define EFS_WDATA_5_MSK 0xffffffff
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#define EFS_WDATA_5_I_MSK 0x00000000
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#define EFS_WDATA_5_SFT 0
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#define EFS_WDATA_5_HI 31
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#define EFS_WDATA_5_SZ 32
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#define EFS_RDATA_6_MSK 0xffffffff
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#define EFS_RDATA_6_I_MSK 0x00000000
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#define EFS_RDATA_6_SFT 0
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#define EFS_RDATA_6_HI 31
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#define EFS_RDATA_6_SZ 32
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#define EFS_WDATA_6_MSK 0xffffffff
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#define EFS_WDATA_6_I_MSK 0x00000000
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#define EFS_WDATA_6_SFT 0
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#define EFS_WDATA_6_HI 31
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#define EFS_WDATA_6_SZ 32
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#define EFS_RDATA_7_MSK 0xffffffff
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#define EFS_RDATA_7_I_MSK 0x00000000
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#define EFS_RDATA_7_SFT 0
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#define EFS_RDATA_7_HI 31
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#define EFS_RDATA_7_SZ 32
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#define EFS_WDATA_7_MSK 0xffffffff
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#define EFS_WDATA_7_I_MSK 0x00000000
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#define EFS_WDATA_7_SFT 0
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#define EFS_WDATA_7_HI 31
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#define EFS_WDATA_7_SZ 32
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#define EFS_SPI_RD0_EN_MSK 0x00000001
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#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD0_EN_SFT 0
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#define EFS_SPI_RD0_EN_HI 0
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#define EFS_SPI_RD0_EN_SZ 1
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#define EFS_SPI_RD1_EN_MSK 0x00000001
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#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD1_EN_SFT 0
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#define EFS_SPI_RD1_EN_HI 0
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#define EFS_SPI_RD1_EN_SZ 1
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#define EFS_SPI_RD2_EN_MSK 0x00000001
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#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD2_EN_SFT 0
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#define EFS_SPI_RD2_EN_HI 0
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#define EFS_SPI_RD2_EN_SZ 1
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#define EFS_SPI_RD3_EN_MSK 0x00000001
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#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD3_EN_SFT 0
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#define EFS_SPI_RD3_EN_HI 0
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#define EFS_SPI_RD3_EN_SZ 1
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#define EFS_SPI_RD4_EN_MSK 0x00000001
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#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD4_EN_SFT 0
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#define EFS_SPI_RD4_EN_HI 0
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#define EFS_SPI_RD4_EN_SZ 1
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#define EFS_SPI_RD5_EN_MSK 0x00000001
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#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD5_EN_SFT 0
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#define EFS_SPI_RD5_EN_HI 0
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#define EFS_SPI_RD5_EN_SZ 1
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#define EFS_SPI_RD6_EN_MSK 0x00000001
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#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD6_EN_SFT 0
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#define EFS_SPI_RD6_EN_HI 0
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#define EFS_SPI_RD6_EN_SZ 1
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#define EFS_SPI_RD7_EN_MSK 0x00000001
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#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
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#define EFS_SPI_RD7_EN_SFT 0
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#define EFS_SPI_RD7_EN_HI 0
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#define EFS_SPI_RD7_EN_SZ 1
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#define EFS_SPI_RBUSY_MSK 0x00000001
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#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
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#define EFS_SPI_RBUSY_SFT 0
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#define EFS_SPI_RBUSY_HI 0
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#define EFS_SPI_RBUSY_SZ 1
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#define EFS_SPI_RDATA_0_MSK 0xffffffff
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#define EFS_SPI_RDATA_0_I_MSK 0x00000000
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#define EFS_SPI_RDATA_0_SFT 0
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#define EFS_SPI_RDATA_0_HI 31
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#define EFS_SPI_RDATA_0_SZ 32
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#define EFS_SPI_RDATA_1_MSK 0xffffffff
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#define EFS_SPI_RDATA_1_I_MSK 0x00000000
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#define EFS_SPI_RDATA_1_SFT 0
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#define EFS_SPI_RDATA_1_HI 31
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#define EFS_SPI_RDATA_1_SZ 32
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#define EFS_SPI_RDATA_2_MSK 0xffffffff
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#define EFS_SPI_RDATA_2_I_MSK 0x00000000
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#define EFS_SPI_RDATA_2_SFT 0
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#define EFS_SPI_RDATA_2_HI 31
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#define EFS_SPI_RDATA_2_SZ 32
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#define EFS_SPI_RDATA_3_MSK 0xffffffff
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#define EFS_SPI_RDATA_3_I_MSK 0x00000000
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#define EFS_SPI_RDATA_3_SFT 0
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#define EFS_SPI_RDATA_3_HI 31
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#define EFS_SPI_RDATA_3_SZ 32
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#define EFS_SPI_RDATA_4_MSK 0xffffffff
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#define EFS_SPI_RDATA_4_I_MSK 0x00000000
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#define EFS_SPI_RDATA_4_SFT 0
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#define EFS_SPI_RDATA_4_HI 31
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#define EFS_SPI_RDATA_4_SZ 32
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#define EFS_SPI_RDATA_5_MSK 0xffffffff
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#define EFS_SPI_RDATA_5_I_MSK 0x00000000
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#define EFS_SPI_RDATA_5_SFT 0
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#define EFS_SPI_RDATA_5_HI 31
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#define EFS_SPI_RDATA_5_SZ 32
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#define EFS_SPI_RDATA_6_MSK 0xffffffff
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#define EFS_SPI_RDATA_6_I_MSK 0x00000000
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#define EFS_SPI_RDATA_6_SFT 0
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#define EFS_SPI_RDATA_6_HI 31
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#define EFS_SPI_RDATA_6_SZ 32
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#define EFS_SPI_RDATA_7_MSK 0xffffffff
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#define EFS_SPI_RDATA_7_I_MSK 0x00000000
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#define EFS_SPI_RDATA_7_SFT 0
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#define EFS_SPI_RDATA_7_HI 31
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#define EFS_SPI_RDATA_7_SZ 32
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#define GET_RK_MSK 0x00000001
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#define GET_RK_I_MSK 0xfffffffe
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#define GET_RK_SFT 0
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#define GET_RK_HI 0
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#define GET_RK_SZ 1
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#define FORCE_GET_RK_MSK 0x00000002
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#define FORCE_GET_RK_I_MSK 0xfffffffd
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#define FORCE_GET_RK_SFT 1
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#define FORCE_GET_RK_HI 1
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#define FORCE_GET_RK_SZ 1
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#define SMS4_DESCRY_EN_MSK 0x00000010
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#define SMS4_DESCRY_EN_I_MSK 0xffffffef
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#define SMS4_DESCRY_EN_SFT 4
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#define SMS4_DESCRY_EN_HI 4
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#define SMS4_DESCRY_EN_SZ 1
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#define DEC_DOUT_MSB_MSK 0x00000001
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#define DEC_DOUT_MSB_I_MSK 0xfffffffe
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#define DEC_DOUT_MSB_SFT 0
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#define DEC_DOUT_MSB_HI 0
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#define DEC_DOUT_MSB_SZ 1
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#define DEC_DIN_MSB_MSK 0x00000002
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#define DEC_DIN_MSB_I_MSK 0xfffffffd
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#define DEC_DIN_MSB_SFT 1
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#define DEC_DIN_MSB_HI 1
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#define DEC_DIN_MSB_SZ 1
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#define ENC_DOUT_MSB_MSK 0x00000004
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#define ENC_DOUT_MSB_I_MSK 0xfffffffb
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#define ENC_DOUT_MSB_SFT 2
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#define ENC_DOUT_MSB_HI 2
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#define ENC_DOUT_MSB_SZ 1
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#define ENC_DIN_MSB_MSK 0x00000008
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#define ENC_DIN_MSB_I_MSK 0xfffffff7
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#define ENC_DIN_MSB_SFT 3
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#define ENC_DIN_MSB_HI 3
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#define ENC_DIN_MSB_SZ 1
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#define KEY_DIN_MSB_MSK 0x00000010
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#define KEY_DIN_MSB_I_MSK 0xffffffef
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#define KEY_DIN_MSB_SFT 4
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#define KEY_DIN_MSB_HI 4
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#define KEY_DIN_MSB_SZ 1
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#define SMS4_CBC_EN_MSK 0x00000001
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#define SMS4_CBC_EN_I_MSK 0xfffffffe
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#define SMS4_CBC_EN_SFT 0
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#define SMS4_CBC_EN_HI 0
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#define SMS4_CBC_EN_SZ 1
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#define SMS4_CFB_EN_MSK 0x00000002
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#define SMS4_CFB_EN_I_MSK 0xfffffffd
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#define SMS4_CFB_EN_SFT 1
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#define SMS4_CFB_EN_HI 1
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#define SMS4_CFB_EN_SZ 1
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#define SMS4_OFB_EN_MSK 0x00000004
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#define SMS4_OFB_EN_I_MSK 0xfffffffb
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#define SMS4_OFB_EN_SFT 2
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#define SMS4_OFB_EN_HI 2
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#define SMS4_OFB_EN_SZ 1
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#define SMS4_START_TRIG_MSK 0x00000001
|
#define SMS4_START_TRIG_I_MSK 0xfffffffe
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#define SMS4_START_TRIG_SFT 0
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#define SMS4_START_TRIG_HI 0
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#define SMS4_START_TRIG_SZ 1
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#define SMS4_BUSY_MSK 0x00000001
|
#define SMS4_BUSY_I_MSK 0xfffffffe
|
#define SMS4_BUSY_SFT 0
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#define SMS4_BUSY_HI 0
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#define SMS4_BUSY_SZ 1
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#define SMS4_DONE_MSK 0x00000001
|
#define SMS4_DONE_I_MSK 0xfffffffe
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#define SMS4_DONE_SFT 0
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#define SMS4_DONE_HI 0
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#define SMS4_DONE_SZ 1
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#define SMS4_DATAIN_0_MSK 0xffffffff
|
#define SMS4_DATAIN_0_I_MSK 0x00000000
|
#define SMS4_DATAIN_0_SFT 0
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#define SMS4_DATAIN_0_HI 31
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#define SMS4_DATAIN_0_SZ 32
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#define SMS4_DATAIN_1_MSK 0xffffffff
|
#define SMS4_DATAIN_1_I_MSK 0x00000000
|
#define SMS4_DATAIN_1_SFT 0
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#define SMS4_DATAIN_1_HI 31
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#define SMS4_DATAIN_1_SZ 32
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#define SMS4_DATAIN_2_MSK 0xffffffff
|
#define SMS4_DATAIN_2_I_MSK 0x00000000
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#define SMS4_DATAIN_2_SFT 0
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#define SMS4_DATAIN_2_HI 31
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#define SMS4_DATAIN_2_SZ 32
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#define SMS4_DATAIN_3_MSK 0xffffffff
|
#define SMS4_DATAIN_3_I_MSK 0x00000000
|
#define SMS4_DATAIN_3_SFT 0
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#define SMS4_DATAIN_3_HI 31
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#define SMS4_DATAIN_3_SZ 32
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#define SMS4_DATAOUT_0_MSK 0xffffffff
|
#define SMS4_DATAOUT_0_I_MSK 0x00000000
|
#define SMS4_DATAOUT_0_SFT 0
|
#define SMS4_DATAOUT_0_HI 31
|
#define SMS4_DATAOUT_0_SZ 32
|
#define SMS4_DATAOUT_1_MSK 0xffffffff
|
#define SMS4_DATAOUT_1_I_MSK 0x00000000
|
#define SMS4_DATAOUT_1_SFT 0
|
#define SMS4_DATAOUT_1_HI 31
|
#define SMS4_DATAOUT_1_SZ 32
|
#define SMS4_DATAOUT_2_MSK 0xffffffff
|
#define SMS4_DATAOUT_2_I_MSK 0x00000000
|
#define SMS4_DATAOUT_2_SFT 0
|
#define SMS4_DATAOUT_2_HI 31
|
#define SMS4_DATAOUT_2_SZ 32
|
#define SMS4_DATAOUT_3_MSK 0xffffffff
|
#define SMS4_DATAOUT_3_I_MSK 0x00000000
|
#define SMS4_DATAOUT_3_SFT 0
|
#define SMS4_DATAOUT_3_HI 31
|
#define SMS4_DATAOUT_3_SZ 32
|
#define SMS4_KEY_0_MSK 0xffffffff
|
#define SMS4_KEY_0_I_MSK 0x00000000
|
#define SMS4_KEY_0_SFT 0
|
#define SMS4_KEY_0_HI 31
|
#define SMS4_KEY_0_SZ 32
|
#define SMS4_KEY_1_MSK 0xffffffff
|
#define SMS4_KEY_1_I_MSK 0x00000000
|
#define SMS4_KEY_1_SFT 0
|
#define SMS4_KEY_1_HI 31
|
#define SMS4_KEY_1_SZ 32
|
#define SMS4_KEY_2_MSK 0xffffffff
|
#define SMS4_KEY_2_I_MSK 0x00000000
|
#define SMS4_KEY_2_SFT 0
|
#define SMS4_KEY_2_HI 31
|
#define SMS4_KEY_2_SZ 32
|
#define SMS4_KEY_3_MSK 0xffffffff
|
#define SMS4_KEY_3_I_MSK 0x00000000
|
#define SMS4_KEY_3_SFT 0
|
#define SMS4_KEY_3_HI 31
|
#define SMS4_KEY_3_SZ 32
|
#define SMS4_MODE_IV0_MSK 0xffffffff
|
#define SMS4_MODE_IV0_I_MSK 0x00000000
|
#define SMS4_MODE_IV0_SFT 0
|
#define SMS4_MODE_IV0_HI 31
|
#define SMS4_MODE_IV0_SZ 32
|
#define SMS4_MODE_IV1_MSK 0xffffffff
|
#define SMS4_MODE_IV1_I_MSK 0x00000000
|
#define SMS4_MODE_IV1_SFT 0
|
#define SMS4_MODE_IV1_HI 31
|
#define SMS4_MODE_IV1_SZ 32
|
#define SMS4_MODE_IV2_MSK 0xffffffff
|
#define SMS4_MODE_IV2_I_MSK 0x00000000
|
#define SMS4_MODE_IV2_SFT 0
|
#define SMS4_MODE_IV2_HI 31
|
#define SMS4_MODE_IV2_SZ 32
|
#define SMS4_MODE_IV3_MSK 0xffffffff
|
#define SMS4_MODE_IV3_I_MSK 0x00000000
|
#define SMS4_MODE_IV3_SFT 0
|
#define SMS4_MODE_IV3_HI 31
|
#define SMS4_MODE_IV3_SZ 32
|
#define SMS4_OFB_ENC0_MSK 0xffffffff
|
#define SMS4_OFB_ENC0_I_MSK 0x00000000
|
#define SMS4_OFB_ENC0_SFT 0
|
#define SMS4_OFB_ENC0_HI 31
|
#define SMS4_OFB_ENC0_SZ 32
|
#define SMS4_OFB_ENC1_MSK 0xffffffff
|
#define SMS4_OFB_ENC1_I_MSK 0x00000000
|
#define SMS4_OFB_ENC1_SFT 0
|
#define SMS4_OFB_ENC1_HI 31
|
#define SMS4_OFB_ENC1_SZ 32
|
#define SMS4_OFB_ENC2_MSK 0xffffffff
|
#define SMS4_OFB_ENC2_I_MSK 0x00000000
|
#define SMS4_OFB_ENC2_SFT 0
|
#define SMS4_OFB_ENC2_HI 31
|
#define SMS4_OFB_ENC2_SZ 32
|
#define SMS4_OFB_ENC3_MSK 0xffffffff
|
#define SMS4_OFB_ENC3_I_MSK 0x00000000
|
#define SMS4_OFB_ENC3_SFT 0
|
#define SMS4_OFB_ENC3_HI 31
|
#define SMS4_OFB_ENC3_SZ 32
|
#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
|
#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_TB0_31_0_SFT 0
|
#define MRX_MCAST_TB0_31_0_HI 31
|
#define MRX_MCAST_TB0_31_0_SZ 32
|
#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_TB0_47_32_SFT 0
|
#define MRX_MCAST_TB0_47_32_HI 15
|
#define MRX_MCAST_TB0_47_32_SZ 16
|
#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
|
#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_MASK0_31_0_SFT 0
|
#define MRX_MCAST_MASK0_31_0_HI 31
|
#define MRX_MCAST_MASK0_31_0_SZ 32
|
#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_MASK0_47_32_SFT 0
|
#define MRX_MCAST_MASK0_47_32_HI 15
|
#define MRX_MCAST_MASK0_47_32_SZ 16
|
#define MRX_MCAST_CTRL_0_MSK 0x00000003
|
#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
|
#define MRX_MCAST_CTRL_0_SFT 0
|
#define MRX_MCAST_CTRL_0_HI 1
|
#define MRX_MCAST_CTRL_0_SZ 2
|
#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
|
#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_TB1_31_0_SFT 0
|
#define MRX_MCAST_TB1_31_0_HI 31
|
#define MRX_MCAST_TB1_31_0_SZ 32
|
#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_TB1_47_32_SFT 0
|
#define MRX_MCAST_TB1_47_32_HI 15
|
#define MRX_MCAST_TB1_47_32_SZ 16
|
#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
|
#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_MASK1_31_0_SFT 0
|
#define MRX_MCAST_MASK1_31_0_HI 31
|
#define MRX_MCAST_MASK1_31_0_SZ 32
|
#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_MASK1_47_32_SFT 0
|
#define MRX_MCAST_MASK1_47_32_HI 15
|
#define MRX_MCAST_MASK1_47_32_SZ 16
|
#define MRX_MCAST_CTRL_1_MSK 0x00000003
|
#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
|
#define MRX_MCAST_CTRL_1_SFT 0
|
#define MRX_MCAST_CTRL_1_HI 1
|
#define MRX_MCAST_CTRL_1_SZ 2
|
#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
|
#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_TB2_31_0_SFT 0
|
#define MRX_MCAST_TB2_31_0_HI 31
|
#define MRX_MCAST_TB2_31_0_SZ 32
|
#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_TB2_47_32_SFT 0
|
#define MRX_MCAST_TB2_47_32_HI 15
|
#define MRX_MCAST_TB2_47_32_SZ 16
|
#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
|
#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_MASK2_31_0_SFT 0
|
#define MRX_MCAST_MASK2_31_0_HI 31
|
#define MRX_MCAST_MASK2_31_0_SZ 32
|
#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_MASK2_47_32_SFT 0
|
#define MRX_MCAST_MASK2_47_32_HI 15
|
#define MRX_MCAST_MASK2_47_32_SZ 16
|
#define MRX_MCAST_CTRL_2_MSK 0x00000003
|
#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
|
#define MRX_MCAST_CTRL_2_SFT 0
|
#define MRX_MCAST_CTRL_2_HI 1
|
#define MRX_MCAST_CTRL_2_SZ 2
|
#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
|
#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_TB3_31_0_SFT 0
|
#define MRX_MCAST_TB3_31_0_HI 31
|
#define MRX_MCAST_TB3_31_0_SZ 32
|
#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_TB3_47_32_SFT 0
|
#define MRX_MCAST_TB3_47_32_HI 15
|
#define MRX_MCAST_TB3_47_32_SZ 16
|
#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
|
#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
|
#define MRX_MCAST_MASK3_31_0_SFT 0
|
#define MRX_MCAST_MASK3_31_0_HI 31
|
#define MRX_MCAST_MASK3_31_0_SZ 32
|
#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
|
#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
|
#define MRX_MCAST_MASK3_47_32_SFT 0
|
#define MRX_MCAST_MASK3_47_32_HI 15
|
#define MRX_MCAST_MASK3_47_32_SZ 16
|
#define MRX_MCAST_CTRL_3_MSK 0x00000003
|
#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
|
#define MRX_MCAST_CTRL_3_SFT 0
|
#define MRX_MCAST_CTRL_3_HI 1
|
#define MRX_MCAST_CTRL_3_SZ 2
|
#define MRX_PHY_INFO_MSK 0xffffffff
|
#define MRX_PHY_INFO_I_MSK 0x00000000
|
#define MRX_PHY_INFO_SFT 0
|
#define MRX_PHY_INFO_HI 31
|
#define MRX_PHY_INFO_SZ 32
|
#define DBG_BA_TYPE_MSK 0x0000003f
|
#define DBG_BA_TYPE_I_MSK 0xffffffc0
|
#define DBG_BA_TYPE_SFT 0
|
#define DBG_BA_TYPE_HI 5
|
#define DBG_BA_TYPE_SZ 6
|
#define DBG_BA_SEQ_MSK 0x000fff00
|
#define DBG_BA_SEQ_I_MSK 0xfff000ff
|
#define DBG_BA_SEQ_SFT 8
|
#define DBG_BA_SEQ_HI 19
|
#define DBG_BA_SEQ_SZ 12
|
#define MRX_FLT_TB0_MSK 0x00007fff
|
#define MRX_FLT_TB0_I_MSK 0xffff8000
|
#define MRX_FLT_TB0_SFT 0
|
#define MRX_FLT_TB0_HI 14
|
#define MRX_FLT_TB0_SZ 15
|
#define MRX_FLT_TB1_MSK 0x00007fff
|
#define MRX_FLT_TB1_I_MSK 0xffff8000
|
#define MRX_FLT_TB1_SFT 0
|
#define MRX_FLT_TB1_HI 14
|
#define MRX_FLT_TB1_SZ 15
|
#define MRX_FLT_TB2_MSK 0x00007fff
|
#define MRX_FLT_TB2_I_MSK 0xffff8000
|
#define MRX_FLT_TB2_SFT 0
|
#define MRX_FLT_TB2_HI 14
|
#define MRX_FLT_TB2_SZ 15
|
#define MRX_FLT_TB3_MSK 0x00007fff
|
#define MRX_FLT_TB3_I_MSK 0xffff8000
|
#define MRX_FLT_TB3_SFT 0
|
#define MRX_FLT_TB3_HI 14
|
#define MRX_FLT_TB3_SZ 15
|
#define MRX_FLT_TB4_MSK 0x00007fff
|
#define MRX_FLT_TB4_I_MSK 0xffff8000
|
#define MRX_FLT_TB4_SFT 0
|
#define MRX_FLT_TB4_HI 14
|
#define MRX_FLT_TB4_SZ 15
|
#define MRX_FLT_TB5_MSK 0x00007fff
|
#define MRX_FLT_TB5_I_MSK 0xffff8000
|
#define MRX_FLT_TB5_SFT 0
|
#define MRX_FLT_TB5_HI 14
|
#define MRX_FLT_TB5_SZ 15
|
#define MRX_FLT_TB6_MSK 0x00007fff
|
#define MRX_FLT_TB6_I_MSK 0xffff8000
|
#define MRX_FLT_TB6_SFT 0
|
#define MRX_FLT_TB6_HI 14
|
#define MRX_FLT_TB6_SZ 15
|
#define MRX_FLT_TB7_MSK 0x00007fff
|
#define MRX_FLT_TB7_I_MSK 0xffff8000
|
#define MRX_FLT_TB7_SFT 0
|
#define MRX_FLT_TB7_HI 14
|
#define MRX_FLT_TB7_SZ 15
|
#define MRX_FLT_TB8_MSK 0x00007fff
|
#define MRX_FLT_TB8_I_MSK 0xffff8000
|
#define MRX_FLT_TB8_SFT 0
|
#define MRX_FLT_TB8_HI 14
|
#define MRX_FLT_TB8_SZ 15
|
#define MRX_FLT_TB9_MSK 0x00007fff
|
#define MRX_FLT_TB9_I_MSK 0xffff8000
|
#define MRX_FLT_TB9_SFT 0
|
#define MRX_FLT_TB9_HI 14
|
#define MRX_FLT_TB9_SZ 15
|
#define MRX_FLT_TB10_MSK 0x00007fff
|
#define MRX_FLT_TB10_I_MSK 0xffff8000
|
#define MRX_FLT_TB10_SFT 0
|
#define MRX_FLT_TB10_HI 14
|
#define MRX_FLT_TB10_SZ 15
|
#define MRX_FLT_TB11_MSK 0x00007fff
|
#define MRX_FLT_TB11_I_MSK 0xffff8000
|
#define MRX_FLT_TB11_SFT 0
|
#define MRX_FLT_TB11_HI 14
|
#define MRX_FLT_TB11_SZ 15
|
#define MRX_FLT_TB12_MSK 0x00007fff
|
#define MRX_FLT_TB12_I_MSK 0xffff8000
|
#define MRX_FLT_TB12_SFT 0
|
#define MRX_FLT_TB12_HI 14
|
#define MRX_FLT_TB12_SZ 15
|
#define MRX_FLT_TB13_MSK 0x00007fff
|
#define MRX_FLT_TB13_I_MSK 0xffff8000
|
#define MRX_FLT_TB13_SFT 0
|
#define MRX_FLT_TB13_HI 14
|
#define MRX_FLT_TB13_SZ 15
|
#define MRX_FLT_TB14_MSK 0x00007fff
|
#define MRX_FLT_TB14_I_MSK 0xffff8000
|
#define MRX_FLT_TB14_SFT 0
|
#define MRX_FLT_TB14_HI 14
|
#define MRX_FLT_TB14_SZ 15
|
#define MRX_FLT_TB15_MSK 0x00007fff
|
#define MRX_FLT_TB15_I_MSK 0xffff8000
|
#define MRX_FLT_TB15_SFT 0
|
#define MRX_FLT_TB15_HI 14
|
#define MRX_FLT_TB15_SZ 15
|
#define MRX_FLT_EN0_MSK 0x0000ffff
|
#define MRX_FLT_EN0_I_MSK 0xffff0000
|
#define MRX_FLT_EN0_SFT 0
|
#define MRX_FLT_EN0_HI 15
|
#define MRX_FLT_EN0_SZ 16
|
#define MRX_FLT_EN1_MSK 0x0000ffff
|
#define MRX_FLT_EN1_I_MSK 0xffff0000
|
#define MRX_FLT_EN1_SFT 0
|
#define MRX_FLT_EN1_HI 15
|
#define MRX_FLT_EN1_SZ 16
|
#define MRX_FLT_EN2_MSK 0x0000ffff
|
#define MRX_FLT_EN2_I_MSK 0xffff0000
|
#define MRX_FLT_EN2_SFT 0
|
#define MRX_FLT_EN2_HI 15
|
#define MRX_FLT_EN2_SZ 16
|
#define MRX_FLT_EN3_MSK 0x0000ffff
|
#define MRX_FLT_EN3_I_MSK 0xffff0000
|
#define MRX_FLT_EN3_SFT 0
|
#define MRX_FLT_EN3_HI 15
|
#define MRX_FLT_EN3_SZ 16
|
#define MRX_FLT_EN4_MSK 0x0000ffff
|
#define MRX_FLT_EN4_I_MSK 0xffff0000
|
#define MRX_FLT_EN4_SFT 0
|
#define MRX_FLT_EN4_HI 15
|
#define MRX_FLT_EN4_SZ 16
|
#define MRX_FLT_EN5_MSK 0x0000ffff
|
#define MRX_FLT_EN5_I_MSK 0xffff0000
|
#define MRX_FLT_EN5_SFT 0
|
#define MRX_FLT_EN5_HI 15
|
#define MRX_FLT_EN5_SZ 16
|
#define MRX_FLT_EN6_MSK 0x0000ffff
|
#define MRX_FLT_EN6_I_MSK 0xffff0000
|
#define MRX_FLT_EN6_SFT 0
|
#define MRX_FLT_EN6_HI 15
|
#define MRX_FLT_EN6_SZ 16
|
#define MRX_FLT_EN7_MSK 0x0000ffff
|
#define MRX_FLT_EN7_I_MSK 0xffff0000
|
#define MRX_FLT_EN7_SFT 0
|
#define MRX_FLT_EN7_HI 15
|
#define MRX_FLT_EN7_SZ 16
|
#define MRX_FLT_EN8_MSK 0x0000ffff
|
#define MRX_FLT_EN8_I_MSK 0xffff0000
|
#define MRX_FLT_EN8_SFT 0
|
#define MRX_FLT_EN8_HI 15
|
#define MRX_FLT_EN8_SZ 16
|
#define MRX_LEN_FLT_MSK 0x0000ffff
|
#define MRX_LEN_FLT_I_MSK 0xffff0000
|
#define MRX_LEN_FLT_SFT 0
|
#define MRX_LEN_FLT_HI 15
|
#define MRX_LEN_FLT_SZ 16
|
#define RX_FLOW_DATA_MSK 0xffffffff
|
#define RX_FLOW_DATA_I_MSK 0x00000000
|
#define RX_FLOW_DATA_SFT 0
|
#define RX_FLOW_DATA_HI 31
|
#define RX_FLOW_DATA_SZ 32
|
#define RX_FLOW_MNG_MSK 0x0000ffff
|
#define RX_FLOW_MNG_I_MSK 0xffff0000
|
#define RX_FLOW_MNG_SFT 0
|
#define RX_FLOW_MNG_HI 15
|
#define RX_FLOW_MNG_SZ 16
|
#define RX_FLOW_CTRL_MSK 0x0000ffff
|
#define RX_FLOW_CTRL_I_MSK 0xffff0000
|
#define RX_FLOW_CTRL_SFT 0
|
#define RX_FLOW_CTRL_HI 15
|
#define RX_FLOW_CTRL_SZ 16
|
#define MRX_STP_EN_MSK 0x00000001
|
#define MRX_STP_EN_I_MSK 0xfffffffe
|
#define MRX_STP_EN_SFT 0
|
#define MRX_STP_EN_HI 0
|
#define MRX_STP_EN_SZ 1
|
#define MRX_STP_OFST_MSK 0x0000ff00
|
#define MRX_STP_OFST_I_MSK 0xffff00ff
|
#define MRX_STP_OFST_SFT 8
|
#define MRX_STP_OFST_HI 15
|
#define MRX_STP_OFST_SZ 8
|
#define DBG_FF_FULL_MSK 0x0000ffff
|
#define DBG_FF_FULL_I_MSK 0xffff0000
|
#define DBG_FF_FULL_SFT 0
|
#define DBG_FF_FULL_HI 15
|
#define DBG_FF_FULL_SZ 16
|
#define DBG_FF_FULL_CLR_MSK 0x80000000
|
#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
|
#define DBG_FF_FULL_CLR_SFT 31
|
#define DBG_FF_FULL_CLR_HI 31
|
#define DBG_FF_FULL_CLR_SZ 1
|
#define DBG_WFF_FULL_MSK 0x0000ffff
|
#define DBG_WFF_FULL_I_MSK 0xffff0000
|
#define DBG_WFF_FULL_SFT 0
|
#define DBG_WFF_FULL_HI 15
|
#define DBG_WFF_FULL_SZ 16
|
#define DBG_WFF_FULL_CLR_MSK 0x80000000
|
#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
|
#define DBG_WFF_FULL_CLR_SFT 31
|
#define DBG_WFF_FULL_CLR_HI 31
|
#define DBG_WFF_FULL_CLR_SZ 1
|
#define DBG_MB_FULL_MSK 0x0000ffff
|
#define DBG_MB_FULL_I_MSK 0xffff0000
|
#define DBG_MB_FULL_SFT 0
|
#define DBG_MB_FULL_HI 15
|
#define DBG_MB_FULL_SZ 16
|
#define DBG_MB_FULL_CLR_MSK 0x80000000
|
#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
|
#define DBG_MB_FULL_CLR_SFT 31
|
#define DBG_MB_FULL_CLR_HI 31
|
#define DBG_MB_FULL_CLR_SZ 1
|
#define BA_CTRL_MSK 0x00000003
|
#define BA_CTRL_I_MSK 0xfffffffc
|
#define BA_CTRL_SFT 0
|
#define BA_CTRL_HI 1
|
#define BA_CTRL_SZ 2
|
#define BA_DBG_EN_MSK 0x00000004
|
#define BA_DBG_EN_I_MSK 0xfffffffb
|
#define BA_DBG_EN_SFT 2
|
#define BA_DBG_EN_HI 2
|
#define BA_DBG_EN_SZ 1
|
#define BA_AGRE_EN_MSK 0x00000008
|
#define BA_AGRE_EN_I_MSK 0xfffffff7
|
#define BA_AGRE_EN_SFT 3
|
#define BA_AGRE_EN_HI 3
|
#define BA_AGRE_EN_SZ 1
|
#define BA_TA_31_0_MSK 0xffffffff
|
#define BA_TA_31_0_I_MSK 0x00000000
|
#define BA_TA_31_0_SFT 0
|
#define BA_TA_31_0_HI 31
|
#define BA_TA_31_0_SZ 32
|
#define BA_TA_47_32_MSK 0x0000ffff
|
#define BA_TA_47_32_I_MSK 0xffff0000
|
#define BA_TA_47_32_SFT 0
|
#define BA_TA_47_32_HI 15
|
#define BA_TA_47_32_SZ 16
|
#define BA_TID_MSK 0x0000000f
|
#define BA_TID_I_MSK 0xfffffff0
|
#define BA_TID_SFT 0
|
#define BA_TID_HI 3
|
#define BA_TID_SZ 4
|
#define BA_ST_SEQ_MSK 0x00000fff
|
#define BA_ST_SEQ_I_MSK 0xfffff000
|
#define BA_ST_SEQ_SFT 0
|
#define BA_ST_SEQ_HI 11
|
#define BA_ST_SEQ_SZ 12
|
#define BA_SB0_MSK 0xffffffff
|
#define BA_SB0_I_MSK 0x00000000
|
#define BA_SB0_SFT 0
|
#define BA_SB0_HI 31
|
#define BA_SB0_SZ 32
|
#define BA_SB1_MSK 0xffffffff
|
#define BA_SB1_I_MSK 0x00000000
|
#define BA_SB1_SFT 0
|
#define BA_SB1_HI 31
|
#define BA_SB1_SZ 32
|
#define MRX_WD_MSK 0x0001ffff
|
#define MRX_WD_I_MSK 0xfffe0000
|
#define MRX_WD_SFT 0
|
#define MRX_WD_HI 16
|
#define MRX_WD_SZ 17
|
#define ACK_GEN_EN_MSK 0x00000001
|
#define ACK_GEN_EN_I_MSK 0xfffffffe
|
#define ACK_GEN_EN_SFT 0
|
#define ACK_GEN_EN_HI 0
|
#define ACK_GEN_EN_SZ 1
|
#define BA_GEN_EN_MSK 0x00000002
|
#define BA_GEN_EN_I_MSK 0xfffffffd
|
#define BA_GEN_EN_SFT 1
|
#define BA_GEN_EN_HI 1
|
#define BA_GEN_EN_SZ 1
|
#define ACK_GEN_DUR_MSK 0x0000ffff
|
#define ACK_GEN_DUR_I_MSK 0xffff0000
|
#define ACK_GEN_DUR_SFT 0
|
#define ACK_GEN_DUR_HI 15
|
#define ACK_GEN_DUR_SZ 16
|
#define ACK_GEN_INFO_MSK 0x003f0000
|
#define ACK_GEN_INFO_I_MSK 0xffc0ffff
|
#define ACK_GEN_INFO_SFT 16
|
#define ACK_GEN_INFO_HI 21
|
#define ACK_GEN_INFO_SZ 6
|
#define ACK_GEN_RA_31_0_MSK 0xffffffff
|
#define ACK_GEN_RA_31_0_I_MSK 0x00000000
|
#define ACK_GEN_RA_31_0_SFT 0
|
#define ACK_GEN_RA_31_0_HI 31
|
#define ACK_GEN_RA_31_0_SZ 32
|
#define ACK_GEN_RA_47_32_MSK 0x0000ffff
|
#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
|
#define ACK_GEN_RA_47_32_SFT 0
|
#define ACK_GEN_RA_47_32_HI 15
|
#define ACK_GEN_RA_47_32_SZ 16
|
#define MIB_LEN_FAIL_MSK 0x0000ffff
|
#define MIB_LEN_FAIL_I_MSK 0xffff0000
|
#define MIB_LEN_FAIL_SFT 0
|
#define MIB_LEN_FAIL_HI 15
|
#define MIB_LEN_FAIL_SZ 16
|
#define TRAP_HW_ID_MSK 0x0000000f
|
#define TRAP_HW_ID_I_MSK 0xfffffff0
|
#define TRAP_HW_ID_SFT 0
|
#define TRAP_HW_ID_HI 3
|
#define TRAP_HW_ID_SZ 4
|
#define ID_IN_USE_MSK 0x000000ff
|
#define ID_IN_USE_I_MSK 0xffffff00
|
#define ID_IN_USE_SFT 0
|
#define ID_IN_USE_HI 7
|
#define ID_IN_USE_SZ 8
|
#define MRX_ERR_MSK 0xffffffff
|
#define MRX_ERR_I_MSK 0x00000000
|
#define MRX_ERR_SFT 0
|
#define MRX_ERR_HI 31
|
#define MRX_ERR_SZ 32
|
#define W0_T0_SEQ_MSK 0x0000ffff
|
#define W0_T0_SEQ_I_MSK 0xffff0000
|
#define W0_T0_SEQ_SFT 0
|
#define W0_T0_SEQ_HI 15
|
#define W0_T0_SEQ_SZ 16
|
#define W0_T1_SEQ_MSK 0x0000ffff
|
#define W0_T1_SEQ_I_MSK 0xffff0000
|
#define W0_T1_SEQ_SFT 0
|
#define W0_T1_SEQ_HI 15
|
#define W0_T1_SEQ_SZ 16
|
#define W0_T2_SEQ_MSK 0x0000ffff
|
#define W0_T2_SEQ_I_MSK 0xffff0000
|
#define W0_T2_SEQ_SFT 0
|
#define W0_T2_SEQ_HI 15
|
#define W0_T2_SEQ_SZ 16
|
#define W0_T3_SEQ_MSK 0x0000ffff
|
#define W0_T3_SEQ_I_MSK 0xffff0000
|
#define W0_T3_SEQ_SFT 0
|
#define W0_T3_SEQ_HI 15
|
#define W0_T3_SEQ_SZ 16
|
#define W0_T4_SEQ_MSK 0x0000ffff
|
#define W0_T4_SEQ_I_MSK 0xffff0000
|
#define W0_T4_SEQ_SFT 0
|
#define W0_T4_SEQ_HI 15
|
#define W0_T4_SEQ_SZ 16
|
#define W0_T5_SEQ_MSK 0x0000ffff
|
#define W0_T5_SEQ_I_MSK 0xffff0000
|
#define W0_T5_SEQ_SFT 0
|
#define W0_T5_SEQ_HI 15
|
#define W0_T5_SEQ_SZ 16
|
#define W0_T6_SEQ_MSK 0x0000ffff
|
#define W0_T6_SEQ_I_MSK 0xffff0000
|
#define W0_T6_SEQ_SFT 0
|
#define W0_T6_SEQ_HI 15
|
#define W0_T6_SEQ_SZ 16
|
#define W0_T7_SEQ_MSK 0x0000ffff
|
#define W0_T7_SEQ_I_MSK 0xffff0000
|
#define W0_T7_SEQ_SFT 0
|
#define W0_T7_SEQ_HI 15
|
#define W0_T7_SEQ_SZ 16
|
#define W1_T0_SEQ_MSK 0x0000ffff
|
#define W1_T0_SEQ_I_MSK 0xffff0000
|
#define W1_T0_SEQ_SFT 0
|
#define W1_T0_SEQ_HI 15
|
#define W1_T0_SEQ_SZ 16
|
#define W1_T1_SEQ_MSK 0x0000ffff
|
#define W1_T1_SEQ_I_MSK 0xffff0000
|
#define W1_T1_SEQ_SFT 0
|
#define W1_T1_SEQ_HI 15
|
#define W1_T1_SEQ_SZ 16
|
#define W1_T2_SEQ_MSK 0x0000ffff
|
#define W1_T2_SEQ_I_MSK 0xffff0000
|
#define W1_T2_SEQ_SFT 0
|
#define W1_T2_SEQ_HI 15
|
#define W1_T2_SEQ_SZ 16
|
#define W1_T3_SEQ_MSK 0x0000ffff
|
#define W1_T3_SEQ_I_MSK 0xffff0000
|
#define W1_T3_SEQ_SFT 0
|
#define W1_T3_SEQ_HI 15
|
#define W1_T3_SEQ_SZ 16
|
#define W1_T4_SEQ_MSK 0x0000ffff
|
#define W1_T4_SEQ_I_MSK 0xffff0000
|
#define W1_T4_SEQ_SFT 0
|
#define W1_T4_SEQ_HI 15
|
#define W1_T4_SEQ_SZ 16
|
#define W1_T5_SEQ_MSK 0x0000ffff
|
#define W1_T5_SEQ_I_MSK 0xffff0000
|
#define W1_T5_SEQ_SFT 0
|
#define W1_T5_SEQ_HI 15
|
#define W1_T5_SEQ_SZ 16
|
#define W1_T6_SEQ_MSK 0x0000ffff
|
#define W1_T6_SEQ_I_MSK 0xffff0000
|
#define W1_T6_SEQ_SFT 0
|
#define W1_T6_SEQ_HI 15
|
#define W1_T6_SEQ_SZ 16
|
#define W1_T7_SEQ_MSK 0x0000ffff
|
#define W1_T7_SEQ_I_MSK 0xffff0000
|
#define W1_T7_SEQ_SFT 0
|
#define W1_T7_SEQ_HI 15
|
#define W1_T7_SEQ_SZ 16
|
#define ADDR1A_SEL_MSK 0x00000003
|
#define ADDR1A_SEL_I_MSK 0xfffffffc
|
#define ADDR1A_SEL_SFT 0
|
#define ADDR1A_SEL_HI 1
|
#define ADDR1A_SEL_SZ 2
|
#define ADDR2A_SEL_MSK 0x0000000c
|
#define ADDR2A_SEL_I_MSK 0xfffffff3
|
#define ADDR2A_SEL_SFT 2
|
#define ADDR2A_SEL_HI 3
|
#define ADDR2A_SEL_SZ 2
|
#define ADDR3A_SEL_MSK 0x00000030
|
#define ADDR3A_SEL_I_MSK 0xffffffcf
|
#define ADDR3A_SEL_SFT 4
|
#define ADDR3A_SEL_HI 5
|
#define ADDR3A_SEL_SZ 2
|
#define ADDR1B_SEL_MSK 0x000000c0
|
#define ADDR1B_SEL_I_MSK 0xffffff3f
|
#define ADDR1B_SEL_SFT 6
|
#define ADDR1B_SEL_HI 7
|
#define ADDR1B_SEL_SZ 2
|
#define ADDR2B_SEL_MSK 0x00000300
|
#define ADDR2B_SEL_I_MSK 0xfffffcff
|
#define ADDR2B_SEL_SFT 8
|
#define ADDR2B_SEL_HI 9
|
#define ADDR2B_SEL_SZ 2
|
#define ADDR3B_SEL_MSK 0x00000c00
|
#define ADDR3B_SEL_I_MSK 0xfffff3ff
|
#define ADDR3B_SEL_SFT 10
|
#define ADDR3B_SEL_HI 11
|
#define ADDR3B_SEL_SZ 2
|
#define ADDR3C_SEL_MSK 0x00003000
|
#define ADDR3C_SEL_I_MSK 0xffffcfff
|
#define ADDR3C_SEL_SFT 12
|
#define ADDR3C_SEL_HI 13
|
#define ADDR3C_SEL_SZ 2
|
#define FRM_CTRL_MSK 0x0000003f
|
#define FRM_CTRL_I_MSK 0xffffffc0
|
#define FRM_CTRL_SFT 0
|
#define FRM_CTRL_HI 5
|
#define FRM_CTRL_SZ 6
|
#define CSR_PHY_INFO_MSK 0x00007fff
|
#define CSR_PHY_INFO_I_MSK 0xffff8000
|
#define CSR_PHY_INFO_SFT 0
|
#define CSR_PHY_INFO_HI 14
|
#define CSR_PHY_INFO_SZ 15
|
#define AMPDU_SIG_MSK 0x000000ff
|
#define AMPDU_SIG_I_MSK 0xffffff00
|
#define AMPDU_SIG_SFT 0
|
#define AMPDU_SIG_HI 7
|
#define AMPDU_SIG_SZ 8
|
#define MIB_AMPDU_MSK 0xffffffff
|
#define MIB_AMPDU_I_MSK 0x00000000
|
#define MIB_AMPDU_SFT 0
|
#define MIB_AMPDU_HI 31
|
#define MIB_AMPDU_SZ 32
|
#define LEN_FLT_MSK 0x0000ffff
|
#define LEN_FLT_I_MSK 0xffff0000
|
#define LEN_FLT_SFT 0
|
#define LEN_FLT_HI 15
|
#define LEN_FLT_SZ 16
|
#define MIB_DELIMITER_MSK 0x0000ffff
|
#define MIB_DELIMITER_I_MSK 0xffff0000
|
#define MIB_DELIMITER_SFT 0
|
#define MIB_DELIMITER_HI 15
|
#define MIB_DELIMITER_SZ 16
|
#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
|
#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
|
#define MTX_INT_Q0_Q_EMPTY_SFT 16
|
#define MTX_INT_Q0_Q_EMPTY_HI 16
|
#define MTX_INT_Q0_Q_EMPTY_SZ 1
|
#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
|
#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
|
#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
|
#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
|
#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
|
#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
|
#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
|
#define MTX_INT_Q1_Q_EMPTY_SFT 18
|
#define MTX_INT_Q1_Q_EMPTY_HI 18
|
#define MTX_INT_Q1_Q_EMPTY_SZ 1
|
#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
|
#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
|
#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
|
#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
|
#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
|
#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
|
#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
|
#define MTX_INT_Q2_Q_EMPTY_SFT 20
|
#define MTX_INT_Q2_Q_EMPTY_HI 20
|
#define MTX_INT_Q2_Q_EMPTY_SZ 1
|
#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
|
#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
|
#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
|
#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
|
#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
|
#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
|
#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
|
#define MTX_INT_Q3_Q_EMPTY_SFT 22
|
#define MTX_INT_Q3_Q_EMPTY_HI 22
|
#define MTX_INT_Q3_Q_EMPTY_SZ 1
|
#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
|
#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
|
#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
|
#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
|
#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
|
#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
|
#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
|
#define MTX_INT_Q4_Q_EMPTY_SFT 24
|
#define MTX_INT_Q4_Q_EMPTY_HI 24
|
#define MTX_INT_Q4_Q_EMPTY_SZ 1
|
#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
|
#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
|
#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
|
#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
|
#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
|
#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
|
#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
|
#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
|
#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
|
#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
|
#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
|
#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
|
#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
|
#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
|
#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
|
#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
|
#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
|
#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
|
#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
|
#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
|
#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
|
#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
|
#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
|
#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
|
#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
|
#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
|
#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
|
#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
|
#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
|
#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
|
#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
|
#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
|
#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
|
#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
|
#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
|
#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
|
#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
|
#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
|
#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
|
#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
|
#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
|
#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
|
#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
|
#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
|
#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
|
#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
|
#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
|
#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
|
#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
|
#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
|
#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
|
#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
|
#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
|
#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
|
#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
|
#define MTX_MTX2PHY_SLOW_MSK 0x00000001
|
#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
|
#define MTX_MTX2PHY_SLOW_SFT 0
|
#define MTX_MTX2PHY_SLOW_HI 0
|
#define MTX_MTX2PHY_SLOW_SZ 1
|
#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
|
#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
|
#define MTX_M2M_SLOW_PRD_SFT 1
|
#define MTX_M2M_SLOW_PRD_HI 3
|
#define MTX_M2M_SLOW_PRD_SZ 3
|
#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
|
#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
|
#define MTX_AMPDU_CRC_AUTO_SFT 5
|
#define MTX_AMPDU_CRC_AUTO_HI 5
|
#define MTX_AMPDU_CRC_AUTO_SZ 1
|
#define MTX_FAST_RSP_MODE_MSK 0x00000040
|
#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
|
#define MTX_FAST_RSP_MODE_SFT 6
|
#define MTX_FAST_RSP_MODE_HI 6
|
#define MTX_FAST_RSP_MODE_SZ 1
|
#define MTX_RAW_DATA_MODE_MSK 0x00000080
|
#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
|
#define MTX_RAW_DATA_MODE_SFT 7
|
#define MTX_RAW_DATA_MODE_HI 7
|
#define MTX_RAW_DATA_MODE_SZ 1
|
#define MTX_ACK_DUR0_MSK 0x00000100
|
#define MTX_ACK_DUR0_I_MSK 0xfffffeff
|
#define MTX_ACK_DUR0_SFT 8
|
#define MTX_ACK_DUR0_HI 8
|
#define MTX_ACK_DUR0_SZ 1
|
#define MTX_TSF_AUTO_BCN_MSK 0x00000400
|
#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
|
#define MTX_TSF_AUTO_BCN_SFT 10
|
#define MTX_TSF_AUTO_BCN_HI 10
|
#define MTX_TSF_AUTO_BCN_SZ 1
|
#define MTX_TSF_AUTO_MISC_MSK 0x00000800
|
#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
|
#define MTX_TSF_AUTO_MISC_SFT 11
|
#define MTX_TSF_AUTO_MISC_HI 11
|
#define MTX_TSF_AUTO_MISC_SZ 1
|
#define MTX_FORCE_CS_IDLE_MSK 0x00001000
|
#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
|
#define MTX_FORCE_CS_IDLE_SFT 12
|
#define MTX_FORCE_CS_IDLE_HI 12
|
#define MTX_FORCE_CS_IDLE_SZ 1
|
#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
|
#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
|
#define MTX_FORCE_BKF_RXEN0_SFT 13
|
#define MTX_FORCE_BKF_RXEN0_HI 13
|
#define MTX_FORCE_BKF_RXEN0_SZ 1
|
#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
|
#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
|
#define MTX_FORCE_DMA_RXEN0_SFT 14
|
#define MTX_FORCE_DMA_RXEN0_HI 14
|
#define MTX_FORCE_DMA_RXEN0_SZ 1
|
#define MTX_FORCE_RXEN0_MSK 0x00008000
|
#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
|
#define MTX_FORCE_RXEN0_SFT 15
|
#define MTX_FORCE_RXEN0_HI 15
|
#define MTX_FORCE_RXEN0_SZ 1
|
#define MTX_HALT_Q_MB_MSK 0x003f0000
|
#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
|
#define MTX_HALT_Q_MB_SFT 16
|
#define MTX_HALT_Q_MB_HI 21
|
#define MTX_HALT_Q_MB_SZ 6
|
#define MTX_CTS_SET_DIF_MSK 0x00400000
|
#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
|
#define MTX_CTS_SET_DIF_SFT 22
|
#define MTX_CTS_SET_DIF_HI 22
|
#define MTX_CTS_SET_DIF_SZ 1
|
#define MTX_AMPDU_SET_DIF_MSK 0x00800000
|
#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
|
#define MTX_AMPDU_SET_DIF_SFT 23
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#define MTX_AMPDU_SET_DIF_HI 23
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#define MTX_AMPDU_SET_DIF_SZ 1
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#define MTX_EDCCA_TOUT_MSK 0x000003ff
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#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
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#define MTX_EDCCA_TOUT_SFT 0
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#define MTX_EDCCA_TOUT_HI 9
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#define MTX_EDCCA_TOUT_SZ 10
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#define MTX_INT_BCN_MSK 0x00000002
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#define MTX_INT_BCN_I_MSK 0xfffffffd
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#define MTX_INT_BCN_SFT 1
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#define MTX_INT_BCN_HI 1
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#define MTX_INT_BCN_SZ 1
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#define MTX_INT_DTIM_MSK 0x00000008
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#define MTX_INT_DTIM_I_MSK 0xfffffff7
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#define MTX_INT_DTIM_SFT 3
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#define MTX_INT_DTIM_HI 3
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#define MTX_INT_DTIM_SZ 1
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#define MTX_EN_INT_BCN_MSK 0x00000002
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#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
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#define MTX_EN_INT_BCN_SFT 1
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#define MTX_EN_INT_BCN_HI 1
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#define MTX_EN_INT_BCN_SZ 1
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#define MTX_EN_INT_DTIM_MSK 0x00000008
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#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
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#define MTX_EN_INT_DTIM_SFT 3
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#define MTX_EN_INT_DTIM_HI 3
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#define MTX_EN_INT_DTIM_SZ 1
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#define MTX_BCN_TIMER_EN_MSK 0x00000001
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#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
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#define MTX_BCN_TIMER_EN_SFT 0
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#define MTX_BCN_TIMER_EN_HI 0
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#define MTX_BCN_TIMER_EN_SZ 1
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#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
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#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
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#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
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#define MTX_TIME_STAMP_AUTO_FILL_HI 1
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#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
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#define MTX_TSF_TIMER_EN_MSK 0x00000020
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#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
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#define MTX_TSF_TIMER_EN_SFT 5
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#define MTX_TSF_TIMER_EN_HI 5
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#define MTX_TSF_TIMER_EN_SZ 1
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#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
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#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
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#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
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#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
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#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
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#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
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#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
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#define MTX_INT_DTIM_NUM_SFT 8
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#define MTX_INT_DTIM_NUM_HI 15
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#define MTX_INT_DTIM_NUM_SZ 8
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#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
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#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
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#define MTX_AUTO_FLUSH_Q4_SFT 16
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#define MTX_AUTO_FLUSH_Q4_HI 16
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#define MTX_AUTO_FLUSH_Q4_SZ 1
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#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
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#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
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#define MTX_BCN_PKTID_CH_LOCK_SFT 0
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#define MTX_BCN_PKTID_CH_LOCK_HI 0
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#define MTX_BCN_PKTID_CH_LOCK_SZ 1
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#define MTX_BCN_CFG_VLD_MSK 0x00000006
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#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
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#define MTX_BCN_CFG_VLD_SFT 1
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#define MTX_BCN_CFG_VLD_HI 2
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#define MTX_BCN_CFG_VLD_SZ 2
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#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
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#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
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#define MTX_AUTO_BCN_ONGOING_SFT 3
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#define MTX_AUTO_BCN_ONGOING_HI 3
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#define MTX_AUTO_BCN_ONGOING_SZ 1
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#define MTX_BCN_TIMER_MSK 0xffff0000
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#define MTX_BCN_TIMER_I_MSK 0x0000ffff
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#define MTX_BCN_TIMER_SFT 16
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#define MTX_BCN_TIMER_HI 31
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#define MTX_BCN_TIMER_SZ 16
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#define MTX_BCN_PERIOD_MSK 0x0000ffff
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#define MTX_BCN_PERIOD_I_MSK 0xffff0000
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#define MTX_BCN_PERIOD_SFT 0
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#define MTX_BCN_PERIOD_HI 15
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#define MTX_BCN_PERIOD_SZ 16
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#define MTX_DTIM_NUM_MSK 0xff000000
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#define MTX_DTIM_NUM_I_MSK 0x00ffffff
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#define MTX_DTIM_NUM_SFT 24
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#define MTX_DTIM_NUM_HI 31
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#define MTX_DTIM_NUM_SZ 8
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#define MTX_BCN_TSF_L_MSK 0xffffffff
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#define MTX_BCN_TSF_L_I_MSK 0x00000000
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#define MTX_BCN_TSF_L_SFT 0
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#define MTX_BCN_TSF_L_HI 31
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#define MTX_BCN_TSF_L_SZ 32
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#define MTX_BCN_TSF_U_MSK 0xffffffff
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#define MTX_BCN_TSF_U_I_MSK 0x00000000
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#define MTX_BCN_TSF_U_SFT 0
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#define MTX_BCN_TSF_U_HI 31
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#define MTX_BCN_TSF_U_SZ 32
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#define MTX_BCN_PKT_ID0_MSK 0x0000007f
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#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
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#define MTX_BCN_PKT_ID0_SFT 0
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#define MTX_BCN_PKT_ID0_HI 6
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#define MTX_BCN_PKT_ID0_SZ 7
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#define MTX_DTIM_OFST0_MSK 0x03ff0000
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#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
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#define MTX_DTIM_OFST0_SFT 16
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#define MTX_DTIM_OFST0_HI 25
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#define MTX_DTIM_OFST0_SZ 10
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#define MTX_BCN_PKT_ID1_MSK 0x0000007f
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#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
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#define MTX_BCN_PKT_ID1_SFT 0
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#define MTX_BCN_PKT_ID1_HI 6
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#define MTX_BCN_PKT_ID1_SZ 7
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#define MTX_DTIM_OFST1_MSK 0x03ff0000
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#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
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#define MTX_DTIM_OFST1_SFT 16
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#define MTX_DTIM_OFST1_HI 25
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#define MTX_DTIM_OFST1_SZ 10
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#define MTX_CCA_MSK 0x00000001
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#define MTX_CCA_I_MSK 0xfffffffe
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#define MTX_CCA_SFT 0
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#define MTX_CCA_HI 0
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#define MTX_CCA_SZ 1
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#define MRX_CCA_MSK 0x00000002
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#define MRX_CCA_I_MSK 0xfffffffd
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#define MRX_CCA_SFT 1
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#define MRX_CCA_HI 1
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#define MRX_CCA_SZ 1
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#define MTX_DMA_FSM_MSK 0x0000001c
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#define MTX_DMA_FSM_I_MSK 0xffffffe3
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#define MTX_DMA_FSM_SFT 2
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#define MTX_DMA_FSM_HI 4
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#define MTX_DMA_FSM_SZ 3
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#define CH_ST_FSM_MSK 0x000000e0
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#define CH_ST_FSM_I_MSK 0xffffff1f
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#define CH_ST_FSM_SFT 5
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#define CH_ST_FSM_HI 7
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#define CH_ST_FSM_SZ 3
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#define MTX_GNT_LOCK_MSK 0x00000100
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#define MTX_GNT_LOCK_I_MSK 0xfffffeff
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#define MTX_GNT_LOCK_SFT 8
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#define MTX_GNT_LOCK_HI 8
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#define MTX_GNT_LOCK_SZ 1
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#define MTX_DMA_REQ_MSK 0x00000200
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#define MTX_DMA_REQ_I_MSK 0xfffffdff
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#define MTX_DMA_REQ_SFT 9
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#define MTX_DMA_REQ_HI 9
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#define MTX_DMA_REQ_SZ 1
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#define MTX_Q_REQ_MSK 0x00000400
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#define MTX_Q_REQ_I_MSK 0xfffffbff
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#define MTX_Q_REQ_SFT 10
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#define MTX_Q_REQ_HI 10
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#define MTX_Q_REQ_SZ 1
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#define MTX_TX_EN_MSK 0x00000800
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#define MTX_TX_EN_I_MSK 0xfffff7ff
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#define MTX_TX_EN_SFT 11
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#define MTX_TX_EN_HI 11
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#define MTX_TX_EN_SZ 1
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#define MRX_RX_EN_MSK 0x00001000
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#define MRX_RX_EN_I_MSK 0xffffefff
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#define MRX_RX_EN_SFT 12
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#define MRX_RX_EN_HI 12
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#define MRX_RX_EN_SZ 1
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#define DBG_PRTC_PRD_MSK 0x00002000
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#define DBG_PRTC_PRD_I_MSK 0xffffdfff
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#define DBG_PRTC_PRD_SFT 13
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#define DBG_PRTC_PRD_HI 13
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#define DBG_PRTC_PRD_SZ 1
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#define DBG_DMA_RDY_MSK 0x00004000
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#define DBG_DMA_RDY_I_MSK 0xffffbfff
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#define DBG_DMA_RDY_SFT 14
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#define DBG_DMA_RDY_HI 14
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#define DBG_DMA_RDY_SZ 1
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#define DBG_WAIT_RSP_MSK 0x00008000
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#define DBG_WAIT_RSP_I_MSK 0xffff7fff
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#define DBG_WAIT_RSP_SFT 15
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#define DBG_WAIT_RSP_HI 15
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#define DBG_WAIT_RSP_SZ 1
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#define DBG_CFRM_BUSY_MSK 0x00010000
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#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
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#define DBG_CFRM_BUSY_SFT 16
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#define DBG_CFRM_BUSY_HI 16
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#define DBG_CFRM_BUSY_SZ 1
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#define DBG_RST_MSK 0x00000001
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#define DBG_RST_I_MSK 0xfffffffe
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#define DBG_RST_SFT 0
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#define DBG_RST_HI 0
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#define DBG_RST_SZ 1
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#define DBG_MODE_MSK 0x00000002
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#define DBG_MODE_I_MSK 0xfffffffd
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#define DBG_MODE_SFT 1
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#define DBG_MODE_HI 1
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#define DBG_MODE_SZ 1
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#define MB_REQ_DUR_MSK 0x0000ffff
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#define MB_REQ_DUR_I_MSK 0xffff0000
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#define MB_REQ_DUR_SFT 0
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#define MB_REQ_DUR_HI 15
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#define MB_REQ_DUR_SZ 16
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#define RX_EN_DUR_MSK 0xffff0000
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#define RX_EN_DUR_I_MSK 0x0000ffff
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#define RX_EN_DUR_SFT 16
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#define RX_EN_DUR_HI 31
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#define RX_EN_DUR_SZ 16
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#define RX_CS_DUR_MSK 0x0000ffff
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#define RX_CS_DUR_I_MSK 0xffff0000
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#define RX_CS_DUR_SFT 0
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#define RX_CS_DUR_HI 15
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#define RX_CS_DUR_SZ 16
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#define TX_CCA_DUR_MSK 0xffff0000
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#define TX_CCA_DUR_I_MSK 0x0000ffff
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#define TX_CCA_DUR_SFT 16
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#define TX_CCA_DUR_HI 31
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#define TX_CCA_DUR_SZ 16
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#define Q_REQ_DUR_MSK 0x0000ffff
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#define Q_REQ_DUR_I_MSK 0xffff0000
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#define Q_REQ_DUR_SFT 0
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#define Q_REQ_DUR_HI 15
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#define Q_REQ_DUR_SZ 16
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#define CH_STA0_DUR_MSK 0xffff0000
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#define CH_STA0_DUR_I_MSK 0x0000ffff
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#define CH_STA0_DUR_SFT 16
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#define CH_STA0_DUR_HI 31
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#define CH_STA0_DUR_SZ 16
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#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
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#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
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#define MTX_DUR_RSP_TOUT_B_SFT 0
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#define MTX_DUR_RSP_TOUT_B_HI 7
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#define MTX_DUR_RSP_TOUT_B_SZ 8
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#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
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#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
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#define MTX_DUR_RSP_TOUT_G_SFT 8
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#define MTX_DUR_RSP_TOUT_G_HI 15
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#define MTX_DUR_RSP_TOUT_G_SZ 8
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#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
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#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
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#define MTX_DUR_RSP_SIFS_SFT 0
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#define MTX_DUR_RSP_SIFS_HI 7
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#define MTX_DUR_RSP_SIFS_SZ 8
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#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
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#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
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#define MTX_DUR_BURST_SIFS_SFT 8
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#define MTX_DUR_BURST_SIFS_HI 15
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#define MTX_DUR_BURST_SIFS_SZ 8
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#define MTX_DUR_SLOT_MSK 0x003f0000
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#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
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#define MTX_DUR_SLOT_SFT 16
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#define MTX_DUR_SLOT_HI 21
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#define MTX_DUR_SLOT_SZ 6
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#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
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#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
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#define MTX_DUR_RSP_EIFS_SFT 22
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#define MTX_DUR_RSP_EIFS_HI 31
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#define MTX_DUR_RSP_EIFS_SZ 10
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#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
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#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
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#define MTX_DUR_RSP_SIFS_G_SFT 0
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#define MTX_DUR_RSP_SIFS_G_HI 7
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#define MTX_DUR_RSP_SIFS_G_SZ 8
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#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
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#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
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#define MTX_DUR_BURST_SIFS_G_SFT 8
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#define MTX_DUR_BURST_SIFS_G_HI 15
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#define MTX_DUR_BURST_SIFS_G_SZ 8
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#define MTX_DUR_SLOT_G_MSK 0x003f0000
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#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
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#define MTX_DUR_SLOT_G_SFT 16
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#define MTX_DUR_SLOT_G_HI 21
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#define MTX_DUR_SLOT_G_SZ 6
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#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
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#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
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#define MTX_DUR_RSP_EIFS_G_SFT 22
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#define MTX_DUR_RSP_EIFS_G_HI 31
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#define MTX_DUR_RSP_EIFS_G_SZ 10
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#define CH_STA1_DUR_MSK 0x0000ffff
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#define CH_STA1_DUR_I_MSK 0xffff0000
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#define CH_STA1_DUR_SFT 0
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#define CH_STA1_DUR_HI 15
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#define CH_STA1_DUR_SZ 16
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#define CH_STA2_DUR_MSK 0xffff0000
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#define CH_STA2_DUR_I_MSK 0x0000ffff
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#define CH_STA2_DUR_SFT 16
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#define CH_STA2_DUR_HI 31
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#define CH_STA2_DUR_SZ 16
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#define MTX_NAV_MSK 0x0000ffff
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#define MTX_NAV_I_MSK 0xffff0000
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#define MTX_NAV_SFT 0
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#define MTX_NAV_HI 15
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#define MTX_NAV_SZ 16
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#define MTX_MIB_CNT0_MSK 0x3fffffff
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#define MTX_MIB_CNT0_I_MSK 0xc0000000
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#define MTX_MIB_CNT0_SFT 0
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#define MTX_MIB_CNT0_HI 29
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#define MTX_MIB_CNT0_SZ 30
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#define MTX_MIB_EN0_MSK 0x40000000
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#define MTX_MIB_EN0_I_MSK 0xbfffffff
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#define MTX_MIB_EN0_SFT 30
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#define MTX_MIB_EN0_HI 30
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#define MTX_MIB_EN0_SZ 1
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#define MTX_MIB_CNT1_MSK 0x3fffffff
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#define MTX_MIB_CNT1_I_MSK 0xc0000000
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#define MTX_MIB_CNT1_SFT 0
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#define MTX_MIB_CNT1_HI 29
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#define MTX_MIB_CNT1_SZ 30
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#define MTX_MIB_EN1_MSK 0x40000000
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#define MTX_MIB_EN1_I_MSK 0xbfffffff
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#define MTX_MIB_EN1_SFT 30
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#define MTX_MIB_EN1_HI 30
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#define MTX_MIB_EN1_SZ 1
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#define CH_STA3_DUR_MSK 0x0000ffff
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#define CH_STA3_DUR_I_MSK 0xffff0000
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#define CH_STA3_DUR_SFT 0
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#define CH_STA3_DUR_HI 15
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#define CH_STA3_DUR_SZ 16
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#define CH_STA4_DUR_MSK 0xffff0000
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#define CH_STA4_DUR_I_MSK 0x0000ffff
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#define CH_STA4_DUR_SFT 16
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#define CH_STA4_DUR_HI 31
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#define CH_STA4_DUR_SZ 16
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#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
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#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
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#define TXQ0_MTX_Q_PRE_LD_SFT 1
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#define TXQ0_MTX_Q_PRE_LD_HI 1
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#define TXQ0_MTX_Q_PRE_LD_SZ 1
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#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
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#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
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#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
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#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
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#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
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#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
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#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
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#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
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#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
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#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
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#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
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#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
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#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
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#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
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#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
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#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
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#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
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#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
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#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
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#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
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#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
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#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
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#define TXQ0_MTX_Q_RND_MODE_SFT 6
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#define TXQ0_MTX_Q_RND_MODE_HI 7
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#define TXQ0_MTX_Q_RND_MODE_SZ 2
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#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
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#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
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#define TXQ0_MTX_Q_AIFSN_SFT 0
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#define TXQ0_MTX_Q_AIFSN_HI 3
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#define TXQ0_MTX_Q_AIFSN_SZ 4
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#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
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#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
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#define TXQ0_MTX_Q_ECWMIN_SFT 8
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#define TXQ0_MTX_Q_ECWMIN_HI 11
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#define TXQ0_MTX_Q_ECWMIN_SZ 4
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#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
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#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
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#define TXQ0_MTX_Q_ECWMAX_SFT 12
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#define TXQ0_MTX_Q_ECWMAX_HI 15
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#define TXQ0_MTX_Q_ECWMAX_SZ 4
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#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
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#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
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#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
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#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
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#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
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#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
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#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
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#define TXQ0_MTX_Q_BKF_CNT_SFT 0
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#define TXQ0_MTX_Q_BKF_CNT_HI 15
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#define TXQ0_MTX_Q_BKF_CNT_SZ 16
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#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
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#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
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#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
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#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
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#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
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#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
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#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
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#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
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#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
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#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
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#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
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#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
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#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
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#define TXQ0_MTX_Q_ID_MAP_L_HI 31
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#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
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#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
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#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
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#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
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#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
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#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
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#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
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#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
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#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
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#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
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#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
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#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
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#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
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#define TXQ1_MTX_Q_PRE_LD_SFT 1
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#define TXQ1_MTX_Q_PRE_LD_HI 1
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#define TXQ1_MTX_Q_PRE_LD_SZ 1
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#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
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#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
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#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
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#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
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#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
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#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
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#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
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#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
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#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
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#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
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#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
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#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
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#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
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#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
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#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
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#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
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#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
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#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
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#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
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#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
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#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
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#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
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#define TXQ1_MTX_Q_RND_MODE_SFT 6
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#define TXQ1_MTX_Q_RND_MODE_HI 7
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#define TXQ1_MTX_Q_RND_MODE_SZ 2
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#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
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#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
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#define TXQ1_MTX_Q_AIFSN_SFT 0
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#define TXQ1_MTX_Q_AIFSN_HI 3
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#define TXQ1_MTX_Q_AIFSN_SZ 4
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#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
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#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
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#define TXQ1_MTX_Q_ECWMIN_SFT 8
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#define TXQ1_MTX_Q_ECWMIN_HI 11
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#define TXQ1_MTX_Q_ECWMIN_SZ 4
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#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
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#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
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#define TXQ1_MTX_Q_ECWMAX_SFT 12
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#define TXQ1_MTX_Q_ECWMAX_HI 15
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#define TXQ1_MTX_Q_ECWMAX_SZ 4
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#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
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#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
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#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
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#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
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#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
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#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
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#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
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#define TXQ1_MTX_Q_BKF_CNT_SFT 0
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#define TXQ1_MTX_Q_BKF_CNT_HI 15
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#define TXQ1_MTX_Q_BKF_CNT_SZ 16
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#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
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#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
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#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
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#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
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#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
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#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
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#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
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#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
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#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
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#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
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#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
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#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
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#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
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#define TXQ1_MTX_Q_ID_MAP_L_HI 31
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#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
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#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
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#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
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#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
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#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
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#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
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#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
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#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
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#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
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#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
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#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
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#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
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#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
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#define TXQ2_MTX_Q_PRE_LD_SFT 1
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#define TXQ2_MTX_Q_PRE_LD_HI 1
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#define TXQ2_MTX_Q_PRE_LD_SZ 1
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#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
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#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
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#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
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#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
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#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
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#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
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#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
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#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
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#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
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#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
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#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
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#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
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#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
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#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
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#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
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#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
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#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
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#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
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#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
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#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
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#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
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#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
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#define TXQ2_MTX_Q_RND_MODE_SFT 6
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#define TXQ2_MTX_Q_RND_MODE_HI 7
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#define TXQ2_MTX_Q_RND_MODE_SZ 2
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#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
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#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
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#define TXQ2_MTX_Q_AIFSN_SFT 0
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#define TXQ2_MTX_Q_AIFSN_HI 3
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#define TXQ2_MTX_Q_AIFSN_SZ 4
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#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
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#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
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#define TXQ2_MTX_Q_ECWMIN_SFT 8
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#define TXQ2_MTX_Q_ECWMIN_HI 11
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#define TXQ2_MTX_Q_ECWMIN_SZ 4
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#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
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#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
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#define TXQ2_MTX_Q_ECWMAX_SFT 12
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#define TXQ2_MTX_Q_ECWMAX_HI 15
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#define TXQ2_MTX_Q_ECWMAX_SZ 4
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#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
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#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
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#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
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#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
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#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
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#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
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#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
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#define TXQ2_MTX_Q_BKF_CNT_SFT 0
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#define TXQ2_MTX_Q_BKF_CNT_HI 15
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#define TXQ2_MTX_Q_BKF_CNT_SZ 16
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#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
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#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
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#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
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#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
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#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
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#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
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#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
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#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
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#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
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#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
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#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
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#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
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#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
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#define TXQ2_MTX_Q_ID_MAP_L_HI 31
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#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
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#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
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#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
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#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
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#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
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#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
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#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
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#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
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#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
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#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
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#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
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#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
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#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
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#define TXQ3_MTX_Q_PRE_LD_SFT 1
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#define TXQ3_MTX_Q_PRE_LD_HI 1
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#define TXQ3_MTX_Q_PRE_LD_SZ 1
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#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
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#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
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#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
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#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
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#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
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#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
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#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
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#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
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#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
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#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
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#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
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#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
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#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
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#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
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#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
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#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
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#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
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#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
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#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
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#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
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#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
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#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
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#define TXQ3_MTX_Q_RND_MODE_SFT 6
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#define TXQ3_MTX_Q_RND_MODE_HI 7
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#define TXQ3_MTX_Q_RND_MODE_SZ 2
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#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
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#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
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#define TXQ3_MTX_Q_AIFSN_SFT 0
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#define TXQ3_MTX_Q_AIFSN_HI 3
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#define TXQ3_MTX_Q_AIFSN_SZ 4
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#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
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#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
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#define TXQ3_MTX_Q_ECWMIN_SFT 8
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#define TXQ3_MTX_Q_ECWMIN_HI 11
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#define TXQ3_MTX_Q_ECWMIN_SZ 4
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#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
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#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
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#define TXQ3_MTX_Q_ECWMAX_SFT 12
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#define TXQ3_MTX_Q_ECWMAX_HI 15
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#define TXQ3_MTX_Q_ECWMAX_SZ 4
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#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
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#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
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#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
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#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
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#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
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#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
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#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
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#define TXQ3_MTX_Q_BKF_CNT_SFT 0
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#define TXQ3_MTX_Q_BKF_CNT_HI 15
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#define TXQ3_MTX_Q_BKF_CNT_SZ 16
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#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
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#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
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#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
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#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
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#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
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#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
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#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
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#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
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#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
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#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
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#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
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#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
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#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
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#define TXQ3_MTX_Q_ID_MAP_L_HI 31
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#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
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#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
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#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
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#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
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#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
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#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
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#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
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#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
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#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
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#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
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#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
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#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
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#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
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#define TXQ4_MTX_Q_PRE_LD_SFT 1
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#define TXQ4_MTX_Q_PRE_LD_HI 1
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#define TXQ4_MTX_Q_PRE_LD_SZ 1
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#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
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#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
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#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
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#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
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#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
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#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
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#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
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#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
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#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
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#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
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#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
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#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
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#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
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#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
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#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
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#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
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#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
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#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
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#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
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#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
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#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
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#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
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#define TXQ4_MTX_Q_RND_MODE_SFT 6
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#define TXQ4_MTX_Q_RND_MODE_HI 7
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#define TXQ4_MTX_Q_RND_MODE_SZ 2
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#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
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#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
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#define TXQ4_MTX_Q_AIFSN_SFT 0
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#define TXQ4_MTX_Q_AIFSN_HI 3
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#define TXQ4_MTX_Q_AIFSN_SZ 4
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#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
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#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
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#define TXQ4_MTX_Q_ECWMIN_SFT 8
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#define TXQ4_MTX_Q_ECWMIN_HI 11
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#define TXQ4_MTX_Q_ECWMIN_SZ 4
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#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
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#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
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#define TXQ4_MTX_Q_ECWMAX_SFT 12
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#define TXQ4_MTX_Q_ECWMAX_HI 15
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#define TXQ4_MTX_Q_ECWMAX_SZ 4
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#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
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#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
|
#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
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#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
|
#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
|
#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
|
#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
|
#define TXQ4_MTX_Q_BKF_CNT_SFT 0
|
#define TXQ4_MTX_Q_BKF_CNT_HI 15
|
#define TXQ4_MTX_Q_BKF_CNT_SZ 16
|
#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
|
#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
|
#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
|
#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
|
#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
|
#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
|
#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
|
#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
|
#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
|
#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
|
#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
|
#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
|
#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
|
#define TXQ4_MTX_Q_ID_MAP_L_HI 31
|
#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
|
#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
|
#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
|
#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
|
#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
|
#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
|
#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
|
#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
|
#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
|
#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
|
#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
|
#define VALID0_MSK 0x00000001
|
#define VALID0_I_MSK 0xfffffffe
|
#define VALID0_SFT 0
|
#define VALID0_HI 0
|
#define VALID0_SZ 1
|
#define PEER_QOS_EN0_MSK 0x00000002
|
#define PEER_QOS_EN0_I_MSK 0xfffffffd
|
#define PEER_QOS_EN0_SFT 1
|
#define PEER_QOS_EN0_HI 1
|
#define PEER_QOS_EN0_SZ 1
|
#define PEER_OP_MODE0_MSK 0x0000000c
|
#define PEER_OP_MODE0_I_MSK 0xfffffff3
|
#define PEER_OP_MODE0_SFT 2
|
#define PEER_OP_MODE0_HI 3
|
#define PEER_OP_MODE0_SZ 2
|
#define PEER_HT_MODE0_MSK 0x00000030
|
#define PEER_HT_MODE0_I_MSK 0xffffffcf
|
#define PEER_HT_MODE0_SFT 4
|
#define PEER_HT_MODE0_HI 5
|
#define PEER_HT_MODE0_SZ 2
|
#define PEER_MAC0_31_0_MSK 0xffffffff
|
#define PEER_MAC0_31_0_I_MSK 0x00000000
|
#define PEER_MAC0_31_0_SFT 0
|
#define PEER_MAC0_31_0_HI 31
|
#define PEER_MAC0_31_0_SZ 32
|
#define PEER_MAC0_47_32_MSK 0x0000ffff
|
#define PEER_MAC0_47_32_I_MSK 0xffff0000
|
#define PEER_MAC0_47_32_SFT 0
|
#define PEER_MAC0_47_32_HI 15
|
#define PEER_MAC0_47_32_SZ 16
|
#define TX_ACK_POLICY_0_0_MSK 0x00000003
|
#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_0_SFT 0
|
#define TX_ACK_POLICY_0_0_HI 1
|
#define TX_ACK_POLICY_0_0_SZ 2
|
#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_0_SFT 0
|
#define TX_SEQ_CTRL_0_0_HI 11
|
#define TX_SEQ_CTRL_0_0_SZ 12
|
#define TX_ACK_POLICY_0_1_MSK 0x00000003
|
#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_1_SFT 0
|
#define TX_ACK_POLICY_0_1_HI 1
|
#define TX_ACK_POLICY_0_1_SZ 2
|
#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_1_SFT 0
|
#define TX_SEQ_CTRL_0_1_HI 11
|
#define TX_SEQ_CTRL_0_1_SZ 12
|
#define TX_ACK_POLICY_0_2_MSK 0x00000003
|
#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_2_SFT 0
|
#define TX_ACK_POLICY_0_2_HI 1
|
#define TX_ACK_POLICY_0_2_SZ 2
|
#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_2_SFT 0
|
#define TX_SEQ_CTRL_0_2_HI 11
|
#define TX_SEQ_CTRL_0_2_SZ 12
|
#define TX_ACK_POLICY_0_3_MSK 0x00000003
|
#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_3_SFT 0
|
#define TX_ACK_POLICY_0_3_HI 1
|
#define TX_ACK_POLICY_0_3_SZ 2
|
#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_3_SFT 0
|
#define TX_SEQ_CTRL_0_3_HI 11
|
#define TX_SEQ_CTRL_0_3_SZ 12
|
#define TX_ACK_POLICY_0_4_MSK 0x00000003
|
#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_4_SFT 0
|
#define TX_ACK_POLICY_0_4_HI 1
|
#define TX_ACK_POLICY_0_4_SZ 2
|
#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_4_SFT 0
|
#define TX_SEQ_CTRL_0_4_HI 11
|
#define TX_SEQ_CTRL_0_4_SZ 12
|
#define TX_ACK_POLICY_0_5_MSK 0x00000003
|
#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_5_SFT 0
|
#define TX_ACK_POLICY_0_5_HI 1
|
#define TX_ACK_POLICY_0_5_SZ 2
|
#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_5_SFT 0
|
#define TX_SEQ_CTRL_0_5_HI 11
|
#define TX_SEQ_CTRL_0_5_SZ 12
|
#define TX_ACK_POLICY_0_6_MSK 0x00000003
|
#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_6_SFT 0
|
#define TX_ACK_POLICY_0_6_HI 1
|
#define TX_ACK_POLICY_0_6_SZ 2
|
#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_6_SFT 0
|
#define TX_SEQ_CTRL_0_6_HI 11
|
#define TX_SEQ_CTRL_0_6_SZ 12
|
#define TX_ACK_POLICY_0_7_MSK 0x00000003
|
#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_0_7_SFT 0
|
#define TX_ACK_POLICY_0_7_HI 1
|
#define TX_ACK_POLICY_0_7_SZ 2
|
#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
|
#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_0_7_SFT 0
|
#define TX_SEQ_CTRL_0_7_HI 11
|
#define TX_SEQ_CTRL_0_7_SZ 12
|
#define VALID1_MSK 0x00000001
|
#define VALID1_I_MSK 0xfffffffe
|
#define VALID1_SFT 0
|
#define VALID1_HI 0
|
#define VALID1_SZ 1
|
#define PEER_QOS_EN1_MSK 0x00000002
|
#define PEER_QOS_EN1_I_MSK 0xfffffffd
|
#define PEER_QOS_EN1_SFT 1
|
#define PEER_QOS_EN1_HI 1
|
#define PEER_QOS_EN1_SZ 1
|
#define PEER_OP_MODE1_MSK 0x0000000c
|
#define PEER_OP_MODE1_I_MSK 0xfffffff3
|
#define PEER_OP_MODE1_SFT 2
|
#define PEER_OP_MODE1_HI 3
|
#define PEER_OP_MODE1_SZ 2
|
#define PEER_HT_MODE1_MSK 0x00000030
|
#define PEER_HT_MODE1_I_MSK 0xffffffcf
|
#define PEER_HT_MODE1_SFT 4
|
#define PEER_HT_MODE1_HI 5
|
#define PEER_HT_MODE1_SZ 2
|
#define PEER_MAC1_31_0_MSK 0xffffffff
|
#define PEER_MAC1_31_0_I_MSK 0x00000000
|
#define PEER_MAC1_31_0_SFT 0
|
#define PEER_MAC1_31_0_HI 31
|
#define PEER_MAC1_31_0_SZ 32
|
#define PEER_MAC1_47_32_MSK 0x0000ffff
|
#define PEER_MAC1_47_32_I_MSK 0xffff0000
|
#define PEER_MAC1_47_32_SFT 0
|
#define PEER_MAC1_47_32_HI 15
|
#define PEER_MAC1_47_32_SZ 16
|
#define TX_ACK_POLICY_1_0_MSK 0x00000003
|
#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_0_SFT 0
|
#define TX_ACK_POLICY_1_0_HI 1
|
#define TX_ACK_POLICY_1_0_SZ 2
|
#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_0_SFT 0
|
#define TX_SEQ_CTRL_1_0_HI 11
|
#define TX_SEQ_CTRL_1_0_SZ 12
|
#define TX_ACK_POLICY_1_1_MSK 0x00000003
|
#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_1_SFT 0
|
#define TX_ACK_POLICY_1_1_HI 1
|
#define TX_ACK_POLICY_1_1_SZ 2
|
#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_1_SFT 0
|
#define TX_SEQ_CTRL_1_1_HI 11
|
#define TX_SEQ_CTRL_1_1_SZ 12
|
#define TX_ACK_POLICY_1_2_MSK 0x00000003
|
#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_2_SFT 0
|
#define TX_ACK_POLICY_1_2_HI 1
|
#define TX_ACK_POLICY_1_2_SZ 2
|
#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_2_SFT 0
|
#define TX_SEQ_CTRL_1_2_HI 11
|
#define TX_SEQ_CTRL_1_2_SZ 12
|
#define TX_ACK_POLICY_1_3_MSK 0x00000003
|
#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_3_SFT 0
|
#define TX_ACK_POLICY_1_3_HI 1
|
#define TX_ACK_POLICY_1_3_SZ 2
|
#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_3_SFT 0
|
#define TX_SEQ_CTRL_1_3_HI 11
|
#define TX_SEQ_CTRL_1_3_SZ 12
|
#define TX_ACK_POLICY_1_4_MSK 0x00000003
|
#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_4_SFT 0
|
#define TX_ACK_POLICY_1_4_HI 1
|
#define TX_ACK_POLICY_1_4_SZ 2
|
#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_4_SFT 0
|
#define TX_SEQ_CTRL_1_4_HI 11
|
#define TX_SEQ_CTRL_1_4_SZ 12
|
#define TX_ACK_POLICY_1_5_MSK 0x00000003
|
#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_5_SFT 0
|
#define TX_ACK_POLICY_1_5_HI 1
|
#define TX_ACK_POLICY_1_5_SZ 2
|
#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_5_SFT 0
|
#define TX_SEQ_CTRL_1_5_HI 11
|
#define TX_SEQ_CTRL_1_5_SZ 12
|
#define TX_ACK_POLICY_1_6_MSK 0x00000003
|
#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_6_SFT 0
|
#define TX_ACK_POLICY_1_6_HI 1
|
#define TX_ACK_POLICY_1_6_SZ 2
|
#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_6_SFT 0
|
#define TX_SEQ_CTRL_1_6_HI 11
|
#define TX_SEQ_CTRL_1_6_SZ 12
|
#define TX_ACK_POLICY_1_7_MSK 0x00000003
|
#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
|
#define TX_ACK_POLICY_1_7_SFT 0
|
#define TX_ACK_POLICY_1_7_HI 1
|
#define TX_ACK_POLICY_1_7_SZ 2
|
#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
|
#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
|
#define TX_SEQ_CTRL_1_7_SFT 0
|
#define TX_SEQ_CTRL_1_7_HI 11
|
#define TX_SEQ_CTRL_1_7_SZ 12
|
#define INFO0_MSK 0xffffffff
|
#define INFO0_I_MSK 0x00000000
|
#define INFO0_SFT 0
|
#define INFO0_HI 31
|
#define INFO0_SZ 32
|
#define INFO1_MSK 0xffffffff
|
#define INFO1_I_MSK 0x00000000
|
#define INFO1_SFT 0
|
#define INFO1_HI 31
|
#define INFO1_SZ 32
|
#define INFO2_MSK 0xffffffff
|
#define INFO2_I_MSK 0x00000000
|
#define INFO2_SFT 0
|
#define INFO2_HI 31
|
#define INFO2_SZ 32
|
#define INFO3_MSK 0xffffffff
|
#define INFO3_I_MSK 0x00000000
|
#define INFO3_SFT 0
|
#define INFO3_HI 31
|
#define INFO3_SZ 32
|
#define INFO4_MSK 0xffffffff
|
#define INFO4_I_MSK 0x00000000
|
#define INFO4_SFT 0
|
#define INFO4_HI 31
|
#define INFO4_SZ 32
|
#define INFO5_MSK 0xffffffff
|
#define INFO5_I_MSK 0x00000000
|
#define INFO5_SFT 0
|
#define INFO5_HI 31
|
#define INFO5_SZ 32
|
#define INFO6_MSK 0xffffffff
|
#define INFO6_I_MSK 0x00000000
|
#define INFO6_SFT 0
|
#define INFO6_HI 31
|
#define INFO6_SZ 32
|
#define INFO7_MSK 0xffffffff
|
#define INFO7_I_MSK 0x00000000
|
#define INFO7_SFT 0
|
#define INFO7_HI 31
|
#define INFO7_SZ 32
|
#define INFO8_MSK 0xffffffff
|
#define INFO8_I_MSK 0x00000000
|
#define INFO8_SFT 0
|
#define INFO8_HI 31
|
#define INFO8_SZ 32
|
#define INFO9_MSK 0xffffffff
|
#define INFO9_I_MSK 0x00000000
|
#define INFO9_SFT 0
|
#define INFO9_HI 31
|
#define INFO9_SZ 32
|
#define INFO10_MSK 0xffffffff
|
#define INFO10_I_MSK 0x00000000
|
#define INFO10_SFT 0
|
#define INFO10_HI 31
|
#define INFO10_SZ 32
|
#define INFO11_MSK 0xffffffff
|
#define INFO11_I_MSK 0x00000000
|
#define INFO11_SFT 0
|
#define INFO11_HI 31
|
#define INFO11_SZ 32
|
#define INFO12_MSK 0xffffffff
|
#define INFO12_I_MSK 0x00000000
|
#define INFO12_SFT 0
|
#define INFO12_HI 31
|
#define INFO12_SZ 32
|
#define INFO13_MSK 0xffffffff
|
#define INFO13_I_MSK 0x00000000
|
#define INFO13_SFT 0
|
#define INFO13_HI 31
|
#define INFO13_SZ 32
|
#define INFO14_MSK 0xffffffff
|
#define INFO14_I_MSK 0x00000000
|
#define INFO14_SFT 0
|
#define INFO14_HI 31
|
#define INFO14_SZ 32
|
#define INFO15_MSK 0xffffffff
|
#define INFO15_I_MSK 0x00000000
|
#define INFO15_SFT 0
|
#define INFO15_HI 31
|
#define INFO15_SZ 32
|
#define INFO16_MSK 0xffffffff
|
#define INFO16_I_MSK 0x00000000
|
#define INFO16_SFT 0
|
#define INFO16_HI 31
|
#define INFO16_SZ 32
|
#define INFO17_MSK 0xffffffff
|
#define INFO17_I_MSK 0x00000000
|
#define INFO17_SFT 0
|
#define INFO17_HI 31
|
#define INFO17_SZ 32
|
#define INFO18_MSK 0xffffffff
|
#define INFO18_I_MSK 0x00000000
|
#define INFO18_SFT 0
|
#define INFO18_HI 31
|
#define INFO18_SZ 32
|
#define INFO19_MSK 0xffffffff
|
#define INFO19_I_MSK 0x00000000
|
#define INFO19_SFT 0
|
#define INFO19_HI 31
|
#define INFO19_SZ 32
|
#define INFO20_MSK 0xffffffff
|
#define INFO20_I_MSK 0x00000000
|
#define INFO20_SFT 0
|
#define INFO20_HI 31
|
#define INFO20_SZ 32
|
#define INFO21_MSK 0xffffffff
|
#define INFO21_I_MSK 0x00000000
|
#define INFO21_SFT 0
|
#define INFO21_HI 31
|
#define INFO21_SZ 32
|
#define INFO22_MSK 0xffffffff
|
#define INFO22_I_MSK 0x00000000
|
#define INFO22_SFT 0
|
#define INFO22_HI 31
|
#define INFO22_SZ 32
|
#define INFO23_MSK 0xffffffff
|
#define INFO23_I_MSK 0x00000000
|
#define INFO23_SFT 0
|
#define INFO23_HI 31
|
#define INFO23_SZ 32
|
#define INFO24_MSK 0xffffffff
|
#define INFO24_I_MSK 0x00000000
|
#define INFO24_SFT 0
|
#define INFO24_HI 31
|
#define INFO24_SZ 32
|
#define INFO25_MSK 0xffffffff
|
#define INFO25_I_MSK 0x00000000
|
#define INFO25_SFT 0
|
#define INFO25_HI 31
|
#define INFO25_SZ 32
|
#define INFO26_MSK 0xffffffff
|
#define INFO26_I_MSK 0x00000000
|
#define INFO26_SFT 0
|
#define INFO26_HI 31
|
#define INFO26_SZ 32
|
#define INFO27_MSK 0xffffffff
|
#define INFO27_I_MSK 0x00000000
|
#define INFO27_SFT 0
|
#define INFO27_HI 31
|
#define INFO27_SZ 32
|
#define INFO28_MSK 0xffffffff
|
#define INFO28_I_MSK 0x00000000
|
#define INFO28_SFT 0
|
#define INFO28_HI 31
|
#define INFO28_SZ 32
|
#define INFO29_MSK 0xffffffff
|
#define INFO29_I_MSK 0x00000000
|
#define INFO29_SFT 0
|
#define INFO29_HI 31
|
#define INFO29_SZ 32
|
#define INFO30_MSK 0xffffffff
|
#define INFO30_I_MSK 0x00000000
|
#define INFO30_SFT 0
|
#define INFO30_HI 31
|
#define INFO30_SZ 32
|
#define INFO31_MSK 0xffffffff
|
#define INFO31_I_MSK 0x00000000
|
#define INFO31_SFT 0
|
#define INFO31_HI 31
|
#define INFO31_SZ 32
|
#define INFO32_MSK 0xffffffff
|
#define INFO32_I_MSK 0x00000000
|
#define INFO32_SFT 0
|
#define INFO32_HI 31
|
#define INFO32_SZ 32
|
#define INFO33_MSK 0xffffffff
|
#define INFO33_I_MSK 0x00000000
|
#define INFO33_SFT 0
|
#define INFO33_HI 31
|
#define INFO33_SZ 32
|
#define INFO34_MSK 0xffffffff
|
#define INFO34_I_MSK 0x00000000
|
#define INFO34_SFT 0
|
#define INFO34_HI 31
|
#define INFO34_SZ 32
|
#define INFO35_MSK 0xffffffff
|
#define INFO35_I_MSK 0x00000000
|
#define INFO35_SFT 0
|
#define INFO35_HI 31
|
#define INFO35_SZ 32
|
#define INFO36_MSK 0xffffffff
|
#define INFO36_I_MSK 0x00000000
|
#define INFO36_SFT 0
|
#define INFO36_HI 31
|
#define INFO36_SZ 32
|
#define INFO37_MSK 0xffffffff
|
#define INFO37_I_MSK 0x00000000
|
#define INFO37_SFT 0
|
#define INFO37_HI 31
|
#define INFO37_SZ 32
|
#define INFO38_MSK 0xffffffff
|
#define INFO38_I_MSK 0x00000000
|
#define INFO38_SFT 0
|
#define INFO38_HI 31
|
#define INFO38_SZ 32
|
#define INFO_MASK_MSK 0xffffffff
|
#define INFO_MASK_I_MSK 0x00000000
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#define INFO_MASK_SFT 0
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#define INFO_MASK_HI 31
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#define INFO_MASK_SZ 32
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#define INFO_DEF_RATE_MSK 0x0000003f
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#define INFO_DEF_RATE_I_MSK 0xffffffc0
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#define INFO_DEF_RATE_SFT 0
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#define INFO_DEF_RATE_HI 5
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#define INFO_DEF_RATE_SZ 6
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#define INFO_MRX_OFFSET_MSK 0x000f0000
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#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
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#define INFO_MRX_OFFSET_SFT 16
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#define INFO_MRX_OFFSET_HI 19
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#define INFO_MRX_OFFSET_SZ 4
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#define BCAST_RATEUNKNOW_MSK 0x3f000000
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#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
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#define BCAST_RATEUNKNOW_SFT 24
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#define BCAST_RATEUNKNOW_HI 29
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#define BCAST_RATEUNKNOW_SZ 6
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#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
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#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
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#define INFO_IDX_TBL_ADDR_SFT 0
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#define INFO_IDX_TBL_ADDR_HI 31
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#define INFO_IDX_TBL_ADDR_SZ 32
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#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
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#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
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#define INFO_LEN_TBL_ADDR_SFT 0
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#define INFO_LEN_TBL_ADDR_HI 31
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#define INFO_LEN_TBL_ADDR_SZ 32
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#define IC_TAG_31_0_MSK 0xffffffff
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#define IC_TAG_31_0_I_MSK 0x00000000
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#define IC_TAG_31_0_SFT 0
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#define IC_TAG_31_0_HI 31
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#define IC_TAG_31_0_SZ 32
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#define IC_TAG_63_32_MSK 0xffffffff
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#define IC_TAG_63_32_I_MSK 0x00000000
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#define IC_TAG_63_32_SFT 0
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#define IC_TAG_63_32_HI 31
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#define IC_TAG_63_32_SZ 32
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#define CH1_PRI_MSK 0x00000003
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#define CH1_PRI_I_MSK 0xfffffffc
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#define CH1_PRI_SFT 0
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#define CH1_PRI_HI 1
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#define CH1_PRI_SZ 2
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#define CH2_PRI_MSK 0x00000300
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#define CH2_PRI_I_MSK 0xfffffcff
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#define CH2_PRI_SFT 8
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#define CH2_PRI_HI 9
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#define CH2_PRI_SZ 2
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#define CH3_PRI_MSK 0x00030000
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#define CH3_PRI_I_MSK 0xfffcffff
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#define CH3_PRI_SFT 16
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#define CH3_PRI_HI 17
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#define CH3_PRI_SZ 2
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#define RG_MAC_LPBK_MSK 0x00000001
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#define RG_MAC_LPBK_I_MSK 0xfffffffe
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#define RG_MAC_LPBK_SFT 0
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#define RG_MAC_LPBK_HI 0
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#define RG_MAC_LPBK_SZ 1
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#define RG_MAC_M2M_MSK 0x00000002
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#define RG_MAC_M2M_I_MSK 0xfffffffd
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#define RG_MAC_M2M_SFT 1
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#define RG_MAC_M2M_HI 1
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#define RG_MAC_M2M_SZ 1
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#define RG_PHY_LPBK_MSK 0x00000004
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#define RG_PHY_LPBK_I_MSK 0xfffffffb
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#define RG_PHY_LPBK_SFT 2
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#define RG_PHY_LPBK_HI 2
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#define RG_PHY_LPBK_SZ 1
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#define RG_LPBK_RX_EN_MSK 0x00000008
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#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
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#define RG_LPBK_RX_EN_SFT 3
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#define RG_LPBK_RX_EN_HI 3
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#define RG_LPBK_RX_EN_SZ 1
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#define EXT_MAC_MODE_MSK 0x00000010
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#define EXT_MAC_MODE_I_MSK 0xffffffef
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#define EXT_MAC_MODE_SFT 4
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#define EXT_MAC_MODE_HI 4
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#define EXT_MAC_MODE_SZ 1
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#define EXT_PHY_MODE_MSK 0x00000020
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#define EXT_PHY_MODE_I_MSK 0xffffffdf
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#define EXT_PHY_MODE_SFT 5
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#define EXT_PHY_MODE_HI 5
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#define EXT_PHY_MODE_SZ 1
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#define ASIC_TAG_MSK 0xff000000
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#define ASIC_TAG_I_MSK 0x00ffffff
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#define ASIC_TAG_SFT 24
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#define ASIC_TAG_HI 31
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#define ASIC_TAG_SZ 8
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#define HCI_SW_RST_MSK 0x00000001
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#define HCI_SW_RST_I_MSK 0xfffffffe
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#define HCI_SW_RST_SFT 0
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#define HCI_SW_RST_HI 0
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#define HCI_SW_RST_SZ 1
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#define CO_PROC_SW_RST_MSK 0x00000002
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#define CO_PROC_SW_RST_I_MSK 0xfffffffd
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#define CO_PROC_SW_RST_SFT 1
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#define CO_PROC_SW_RST_HI 1
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#define CO_PROC_SW_RST_SZ 1
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#define MTX_MISC_SW_RST_MSK 0x00000008
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#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
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#define MTX_MISC_SW_RST_SFT 3
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#define MTX_MISC_SW_RST_HI 3
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#define MTX_MISC_SW_RST_SZ 1
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#define MTX_QUE_SW_RST_MSK 0x00000010
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#define MTX_QUE_SW_RST_I_MSK 0xffffffef
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#define MTX_QUE_SW_RST_SFT 4
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#define MTX_QUE_SW_RST_HI 4
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#define MTX_QUE_SW_RST_SZ 1
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#define MTX_CHST_SW_RST_MSK 0x00000020
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#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
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#define MTX_CHST_SW_RST_SFT 5
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#define MTX_CHST_SW_RST_HI 5
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#define MTX_CHST_SW_RST_SZ 1
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#define MTX_BCN_SW_RST_MSK 0x00000040
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#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
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#define MTX_BCN_SW_RST_SFT 6
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#define MTX_BCN_SW_RST_HI 6
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#define MTX_BCN_SW_RST_SZ 1
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#define MRX_SW_RST_MSK 0x00000080
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#define MRX_SW_RST_I_MSK 0xffffff7f
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#define MRX_SW_RST_SFT 7
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#define MRX_SW_RST_HI 7
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#define MRX_SW_RST_SZ 1
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#define AMPDU_SW_RST_MSK 0x00000100
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#define AMPDU_SW_RST_I_MSK 0xfffffeff
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#define AMPDU_SW_RST_SFT 8
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#define AMPDU_SW_RST_HI 8
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#define AMPDU_SW_RST_SZ 1
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#define MMU_SW_RST_MSK 0x00000200
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#define MMU_SW_RST_I_MSK 0xfffffdff
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#define MMU_SW_RST_SFT 9
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#define MMU_SW_RST_HI 9
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#define MMU_SW_RST_SZ 1
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#define ID_MNG_SW_RST_MSK 0x00000800
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#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
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#define ID_MNG_SW_RST_SFT 11
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#define ID_MNG_SW_RST_HI 11
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#define ID_MNG_SW_RST_SZ 1
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#define MBOX_SW_RST_MSK 0x00001000
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#define MBOX_SW_RST_I_MSK 0xffffefff
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#define MBOX_SW_RST_SFT 12
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#define MBOX_SW_RST_HI 12
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#define MBOX_SW_RST_SZ 1
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#define SCRT_SW_RST_MSK 0x00002000
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#define SCRT_SW_RST_I_MSK 0xffffdfff
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#define SCRT_SW_RST_SFT 13
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#define SCRT_SW_RST_HI 13
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#define SCRT_SW_RST_SZ 1
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#define MIC_SW_RST_MSK 0x00004000
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#define MIC_SW_RST_I_MSK 0xffffbfff
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#define MIC_SW_RST_SFT 14
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#define MIC_SW_RST_HI 14
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#define MIC_SW_RST_SZ 1
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#define CO_PROC_ENG_RST_MSK 0x00000002
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#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
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#define CO_PROC_ENG_RST_SFT 1
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#define CO_PROC_ENG_RST_HI 1
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#define CO_PROC_ENG_RST_SZ 1
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#define MTX_MISC_ENG_RST_MSK 0x00000008
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#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
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#define MTX_MISC_ENG_RST_SFT 3
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#define MTX_MISC_ENG_RST_HI 3
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#define MTX_MISC_ENG_RST_SZ 1
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#define MTX_QUE_ENG_RST_MSK 0x00000010
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#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
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#define MTX_QUE_ENG_RST_SFT 4
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#define MTX_QUE_ENG_RST_HI 4
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#define MTX_QUE_ENG_RST_SZ 1
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#define MTX_CHST_ENG_RST_MSK 0x00000020
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#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
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#define MTX_CHST_ENG_RST_SFT 5
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#define MTX_CHST_ENG_RST_HI 5
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#define MTX_CHST_ENG_RST_SZ 1
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#define MTX_BCN_ENG_RST_MSK 0x00000040
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#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
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#define MTX_BCN_ENG_RST_SFT 6
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#define MTX_BCN_ENG_RST_HI 6
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#define MTX_BCN_ENG_RST_SZ 1
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#define MRX_ENG_RST_MSK 0x00000080
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#define MRX_ENG_RST_I_MSK 0xffffff7f
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#define MRX_ENG_RST_SFT 7
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#define MRX_ENG_RST_HI 7
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#define MRX_ENG_RST_SZ 1
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#define AMPDU_ENG_RST_MSK 0x00000100
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#define AMPDU_ENG_RST_I_MSK 0xfffffeff
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#define AMPDU_ENG_RST_SFT 8
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#define AMPDU_ENG_RST_HI 8
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#define AMPDU_ENG_RST_SZ 1
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#define ID_MNG_ENG_RST_MSK 0x00004000
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#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
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#define ID_MNG_ENG_RST_SFT 14
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#define ID_MNG_ENG_RST_HI 14
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#define ID_MNG_ENG_RST_SZ 1
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#define MBOX_ENG_RST_MSK 0x00008000
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#define MBOX_ENG_RST_I_MSK 0xffff7fff
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#define MBOX_ENG_RST_SFT 15
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#define MBOX_ENG_RST_HI 15
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#define MBOX_ENG_RST_SZ 1
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#define SCRT_ENG_RST_MSK 0x00010000
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#define SCRT_ENG_RST_I_MSK 0xfffeffff
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#define SCRT_ENG_RST_SFT 16
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#define SCRT_ENG_RST_HI 16
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#define SCRT_ENG_RST_SZ 1
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#define MIC_ENG_RST_MSK 0x00020000
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#define MIC_ENG_RST_I_MSK 0xfffdffff
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#define MIC_ENG_RST_SFT 17
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#define MIC_ENG_RST_HI 17
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#define MIC_ENG_RST_SZ 1
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#define CO_PROC_CSR_RST_MSK 0x00000002
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#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
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#define CO_PROC_CSR_RST_SFT 1
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#define CO_PROC_CSR_RST_HI 1
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#define CO_PROC_CSR_RST_SZ 1
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#define MTX_MISC_CSR_RST_MSK 0x00000008
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#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
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#define MTX_MISC_CSR_RST_SFT 3
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#define MTX_MISC_CSR_RST_HI 3
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#define MTX_MISC_CSR_RST_SZ 1
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#define MTX_QUE0_CSR_RST_MSK 0x00000010
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#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
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#define MTX_QUE0_CSR_RST_SFT 4
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#define MTX_QUE0_CSR_RST_HI 4
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#define MTX_QUE0_CSR_RST_SZ 1
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#define MTX_QUE1_CSR_RST_MSK 0x00000020
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#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
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#define MTX_QUE1_CSR_RST_SFT 5
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#define MTX_QUE1_CSR_RST_HI 5
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#define MTX_QUE1_CSR_RST_SZ 1
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#define MTX_QUE2_CSR_RST_MSK 0x00000040
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#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
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#define MTX_QUE2_CSR_RST_SFT 6
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#define MTX_QUE2_CSR_RST_HI 6
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#define MTX_QUE2_CSR_RST_SZ 1
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#define MTX_QUE3_CSR_RST_MSK 0x00000080
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#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
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#define MTX_QUE3_CSR_RST_SFT 7
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#define MTX_QUE3_CSR_RST_HI 7
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#define MTX_QUE3_CSR_RST_SZ 1
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#define MTX_QUE4_CSR_RST_MSK 0x00000100
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#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
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#define MTX_QUE4_CSR_RST_SFT 8
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#define MTX_QUE4_CSR_RST_HI 8
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#define MTX_QUE4_CSR_RST_SZ 1
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#define MTX_QUE5_CSR_RST_MSK 0x00000200
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#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
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#define MTX_QUE5_CSR_RST_SFT 9
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#define MTX_QUE5_CSR_RST_HI 9
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#define MTX_QUE5_CSR_RST_SZ 1
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#define MRX_CSR_RST_MSK 0x00000400
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#define MRX_CSR_RST_I_MSK 0xfffffbff
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#define MRX_CSR_RST_SFT 10
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#define MRX_CSR_RST_HI 10
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#define MRX_CSR_RST_SZ 1
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#define AMPDU_CSR_RST_MSK 0x00000800
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#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
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#define AMPDU_CSR_RST_SFT 11
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#define AMPDU_CSR_RST_HI 11
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#define AMPDU_CSR_RST_SZ 1
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#define SCRT_CSR_RST_MSK 0x00002000
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#define SCRT_CSR_RST_I_MSK 0xffffdfff
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#define SCRT_CSR_RST_SFT 13
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#define SCRT_CSR_RST_HI 13
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#define SCRT_CSR_RST_SZ 1
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#define ID_MNG_CSR_RST_MSK 0x00004000
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#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
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#define ID_MNG_CSR_RST_SFT 14
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#define ID_MNG_CSR_RST_HI 14
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#define ID_MNG_CSR_RST_SZ 1
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#define MBOX_CSR_RST_MSK 0x00008000
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#define MBOX_CSR_RST_I_MSK 0xffff7fff
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#define MBOX_CSR_RST_SFT 15
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#define MBOX_CSR_RST_HI 15
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#define MBOX_CSR_RST_SZ 1
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#define HCI_CLK_EN_MSK 0x00000001
|
#define HCI_CLK_EN_I_MSK 0xfffffffe
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#define HCI_CLK_EN_SFT 0
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#define HCI_CLK_EN_HI 0
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#define HCI_CLK_EN_SZ 1
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#define CO_PROC_CLK_EN_MSK 0x00000002
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#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
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#define CO_PROC_CLK_EN_SFT 1
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#define CO_PROC_CLK_EN_HI 1
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#define CO_PROC_CLK_EN_SZ 1
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#define MTX_MISC_CLK_EN_MSK 0x00000008
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#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
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#define MTX_MISC_CLK_EN_SFT 3
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#define MTX_MISC_CLK_EN_HI 3
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#define MTX_MISC_CLK_EN_SZ 1
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#define MTX_QUE_CLK_EN_MSK 0x00000010
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#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
|
#define MTX_QUE_CLK_EN_SFT 4
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#define MTX_QUE_CLK_EN_HI 4
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#define MTX_QUE_CLK_EN_SZ 1
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#define MRX_CLK_EN_MSK 0x00000020
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#define MRX_CLK_EN_I_MSK 0xffffffdf
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#define MRX_CLK_EN_SFT 5
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#define MRX_CLK_EN_HI 5
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#define MRX_CLK_EN_SZ 1
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#define AMPDU_CLK_EN_MSK 0x00000040
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#define AMPDU_CLK_EN_I_MSK 0xffffffbf
|
#define AMPDU_CLK_EN_SFT 6
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#define AMPDU_CLK_EN_HI 6
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#define AMPDU_CLK_EN_SZ 1
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#define MMU_CLK_EN_MSK 0x00000080
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#define MMU_CLK_EN_I_MSK 0xffffff7f
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#define MMU_CLK_EN_SFT 7
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#define MMU_CLK_EN_HI 7
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#define MMU_CLK_EN_SZ 1
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#define ID_MNG_CLK_EN_MSK 0x00000200
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#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
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#define ID_MNG_CLK_EN_SFT 9
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#define ID_MNG_CLK_EN_HI 9
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#define ID_MNG_CLK_EN_SZ 1
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#define MBOX_CLK_EN_MSK 0x00000400
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#define MBOX_CLK_EN_I_MSK 0xfffffbff
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#define MBOX_CLK_EN_SFT 10
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#define MBOX_CLK_EN_HI 10
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#define MBOX_CLK_EN_SZ 1
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#define SCRT_CLK_EN_MSK 0x00000800
|
#define SCRT_CLK_EN_I_MSK 0xfffff7ff
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#define SCRT_CLK_EN_SFT 11
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#define SCRT_CLK_EN_HI 11
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#define SCRT_CLK_EN_SZ 1
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#define MIC_CLK_EN_MSK 0x00001000
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#define MIC_CLK_EN_I_MSK 0xffffefff
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#define MIC_CLK_EN_SFT 12
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#define MIC_CLK_EN_HI 12
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#define MIC_CLK_EN_SZ 1
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#define MIB_CLK_EN_MSK 0x00002000
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#define MIB_CLK_EN_I_MSK 0xffffdfff
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#define MIB_CLK_EN_SFT 13
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#define MIB_CLK_EN_HI 13
|
#define MIB_CLK_EN_SZ 1
|
#define HCI_ENG_CLK_EN_MSK 0x00000001
|
#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
|
#define HCI_ENG_CLK_EN_SFT 0
|
#define HCI_ENG_CLK_EN_HI 0
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#define HCI_ENG_CLK_EN_SZ 1
|
#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
|
#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
|
#define CO_PROC_ENG_CLK_EN_SFT 1
|
#define CO_PROC_ENG_CLK_EN_HI 1
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#define CO_PROC_ENG_CLK_EN_SZ 1
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#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
|
#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
|
#define MTX_MISC_ENG_CLK_EN_SFT 3
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#define MTX_MISC_ENG_CLK_EN_HI 3
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#define MTX_MISC_ENG_CLK_EN_SZ 1
|
#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
|
#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
|
#define MTX_QUE_ENG_CLK_EN_SFT 4
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#define MTX_QUE_ENG_CLK_EN_HI 4
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#define MTX_QUE_ENG_CLK_EN_SZ 1
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#define MRX_ENG_CLK_EN_MSK 0x00000020
|
#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
|
#define MRX_ENG_CLK_EN_SFT 5
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#define MRX_ENG_CLK_EN_HI 5
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#define MRX_ENG_CLK_EN_SZ 1
|
#define AMPDU_ENG_CLK_EN_MSK 0x00000040
|
#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
|
#define AMPDU_ENG_CLK_EN_SFT 6
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#define AMPDU_ENG_CLK_EN_HI 6
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#define AMPDU_ENG_CLK_EN_SZ 1
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#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
|
#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
|
#define ID_MNG_ENG_CLK_EN_SFT 12
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#define ID_MNG_ENG_CLK_EN_HI 12
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#define ID_MNG_ENG_CLK_EN_SZ 1
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#define MBOX_ENG_CLK_EN_MSK 0x00002000
|
#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
|
#define MBOX_ENG_CLK_EN_SFT 13
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#define MBOX_ENG_CLK_EN_HI 13
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#define MBOX_ENG_CLK_EN_SZ 1
|
#define SCRT_ENG_CLK_EN_MSK 0x00004000
|
#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
|
#define SCRT_ENG_CLK_EN_SFT 14
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#define SCRT_ENG_CLK_EN_HI 14
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#define SCRT_ENG_CLK_EN_SZ 1
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#define MIC_ENG_CLK_EN_MSK 0x00008000
|
#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
|
#define MIC_ENG_CLK_EN_SFT 15
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#define MIC_ENG_CLK_EN_HI 15
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#define MIC_ENG_CLK_EN_SZ 1
|
#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
|
#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
|
#define CO_PROC_CSR_CLK_EN_SFT 1
|
#define CO_PROC_CSR_CLK_EN_HI 1
|
#define CO_PROC_CSR_CLK_EN_SZ 1
|
#define MRX_CSR_CLK_EN_MSK 0x00000400
|
#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
|
#define MRX_CSR_CLK_EN_SFT 10
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#define MRX_CSR_CLK_EN_HI 10
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#define MRX_CSR_CLK_EN_SZ 1
|
#define AMPDU_CSR_CLK_EN_MSK 0x00000800
|
#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
|
#define AMPDU_CSR_CLK_EN_SFT 11
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#define AMPDU_CSR_CLK_EN_HI 11
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#define AMPDU_CSR_CLK_EN_SZ 1
|
#define SCRT_CSR_CLK_EN_MSK 0x00002000
|
#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
|
#define SCRT_CSR_CLK_EN_SFT 13
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#define SCRT_CSR_CLK_EN_HI 13
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#define SCRT_CSR_CLK_EN_SZ 1
|
#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
|
#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
|
#define ID_MNG_CSR_CLK_EN_SFT 14
|
#define ID_MNG_CSR_CLK_EN_HI 14
|
#define ID_MNG_CSR_CLK_EN_SZ 1
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#define MBOX_CSR_CLK_EN_MSK 0x00008000
|
#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
|
#define MBOX_CSR_CLK_EN_SFT 15
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#define MBOX_CSR_CLK_EN_HI 15
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#define MBOX_CSR_CLK_EN_SZ 1
|
#define OP_MODE_MSK 0x00000003
|
#define OP_MODE_I_MSK 0xfffffffc
|
#define OP_MODE_SFT 0
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#define OP_MODE_HI 1
|
#define OP_MODE_SZ 2
|
#define HT_MODE_MSK 0x0000000c
|
#define HT_MODE_I_MSK 0xfffffff3
|
#define HT_MODE_SFT 2
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#define HT_MODE_HI 3
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#define HT_MODE_SZ 2
|
#define QOS_EN_MSK 0x00000010
|
#define QOS_EN_I_MSK 0xffffffef
|
#define QOS_EN_SFT 4
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#define QOS_EN_HI 4
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#define QOS_EN_SZ 1
|
#define PB_OFFSET_MSK 0x0000ff00
|
#define PB_OFFSET_I_MSK 0xffff00ff
|
#define PB_OFFSET_SFT 8
|
#define PB_OFFSET_HI 15
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#define PB_OFFSET_SZ 8
|
#define SNIFFER_MODE_MSK 0x00010000
|
#define SNIFFER_MODE_I_MSK 0xfffeffff
|
#define SNIFFER_MODE_SFT 16
|
#define SNIFFER_MODE_HI 16
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#define SNIFFER_MODE_SZ 1
|
#define DUP_FLT_MSK 0x00020000
|
#define DUP_FLT_I_MSK 0xfffdffff
|
#define DUP_FLT_SFT 17
|
#define DUP_FLT_HI 17
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#define DUP_FLT_SZ 1
|
#define TX_PKT_RSVD_MSK 0x001c0000
|
#define TX_PKT_RSVD_I_MSK 0xffe3ffff
|
#define TX_PKT_RSVD_SFT 18
|
#define TX_PKT_RSVD_HI 20
|
#define TX_PKT_RSVD_SZ 3
|
#define AMPDU_SNIFFER_MSK 0x00200000
|
#define AMPDU_SNIFFER_I_MSK 0xffdfffff
|
#define AMPDU_SNIFFER_SFT 21
|
#define AMPDU_SNIFFER_HI 21
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#define AMPDU_SNIFFER_SZ 1
|
#define REASON_TRAP0_MSK 0xffffffff
|
#define REASON_TRAP0_I_MSK 0x00000000
|
#define REASON_TRAP0_SFT 0
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#define REASON_TRAP0_HI 31
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#define REASON_TRAP0_SZ 32
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#define REASON_TRAP1_MSK 0xffffffff
|
#define REASON_TRAP1_I_MSK 0x00000000
|
#define REASON_TRAP1_SFT 0
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#define REASON_TRAP1_HI 31
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#define REASON_TRAP1_SZ 32
|
#define BSSID_31_0_MSK 0xffffffff
|
#define BSSID_31_0_I_MSK 0x00000000
|
#define BSSID_31_0_SFT 0
|
#define BSSID_31_0_HI 31
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#define BSSID_31_0_SZ 32
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#define BSSID_47_32_MSK 0x0000ffff
|
#define BSSID_47_32_I_MSK 0xffff0000
|
#define BSSID_47_32_SFT 0
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#define BSSID_47_32_HI 15
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#define BSSID_47_32_SZ 16
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#define SCRT_STATE_MSK 0x0000000f
|
#define SCRT_STATE_I_MSK 0xfffffff0
|
#define SCRT_STATE_SFT 0
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#define SCRT_STATE_HI 3
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#define SCRT_STATE_SZ 4
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#define STA_MAC_31_0_MSK 0xffffffff
|
#define STA_MAC_31_0_I_MSK 0x00000000
|
#define STA_MAC_31_0_SFT 0
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#define STA_MAC_31_0_HI 31
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#define STA_MAC_31_0_SZ 32
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#define STA_MAC_47_32_MSK 0x0000ffff
|
#define STA_MAC_47_32_I_MSK 0xffff0000
|
#define STA_MAC_47_32_SFT 0
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#define STA_MAC_47_32_HI 15
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#define STA_MAC_47_32_SZ 16
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#define PAIR_SCRT_MSK 0x00000007
|
#define PAIR_SCRT_I_MSK 0xfffffff8
|
#define PAIR_SCRT_SFT 0
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#define PAIR_SCRT_HI 2
|
#define PAIR_SCRT_SZ 3
|
#define GRP_SCRT_MSK 0x00000038
|
#define GRP_SCRT_I_MSK 0xffffffc7
|
#define GRP_SCRT_SFT 3
|
#define GRP_SCRT_HI 5
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#define GRP_SCRT_SZ 3
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#define SCRT_PKT_ID_MSK 0x00001fc0
|
#define SCRT_PKT_ID_I_MSK 0xffffe03f
|
#define SCRT_PKT_ID_SFT 6
|
#define SCRT_PKT_ID_HI 12
|
#define SCRT_PKT_ID_SZ 7
|
#define SCRT_RPLY_IGNORE_MSK 0x00010000
|
#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
|
#define SCRT_RPLY_IGNORE_SFT 16
|
#define SCRT_RPLY_IGNORE_HI 16
|
#define SCRT_RPLY_IGNORE_SZ 1
|
#define COEXIST_EN_MSK 0x00000001
|
#define COEXIST_EN_I_MSK 0xfffffffe
|
#define COEXIST_EN_SFT 0
|
#define COEXIST_EN_HI 0
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#define COEXIST_EN_SZ 1
|
#define WIRE_MODE_MSK 0x0000000e
|
#define WIRE_MODE_I_MSK 0xfffffff1
|
#define WIRE_MODE_SFT 1
|
#define WIRE_MODE_HI 3
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#define WIRE_MODE_SZ 3
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#define WL_RX_PRI_MSK 0x00000010
|
#define WL_RX_PRI_I_MSK 0xffffffef
|
#define WL_RX_PRI_SFT 4
|
#define WL_RX_PRI_HI 4
|
#define WL_RX_PRI_SZ 1
|
#define WL_TX_PRI_MSK 0x00000020
|
#define WL_TX_PRI_I_MSK 0xffffffdf
|
#define WL_TX_PRI_SFT 5
|
#define WL_TX_PRI_HI 5
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#define WL_TX_PRI_SZ 1
|
#define GURAN_USE_EN_MSK 0x00000100
|
#define GURAN_USE_EN_I_MSK 0xfffffeff
|
#define GURAN_USE_EN_SFT 8
|
#define GURAN_USE_EN_HI 8
|
#define GURAN_USE_EN_SZ 1
|
#define GURAN_USE_CTRL_MSK 0x00000200
|
#define GURAN_USE_CTRL_I_MSK 0xfffffdff
|
#define GURAN_USE_CTRL_SFT 9
|
#define GURAN_USE_CTRL_HI 9
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#define GURAN_USE_CTRL_SZ 1
|
#define BEACON_TIMEOUT_EN_MSK 0x00000400
|
#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
|
#define BEACON_TIMEOUT_EN_SFT 10
|
#define BEACON_TIMEOUT_EN_HI 10
|
#define BEACON_TIMEOUT_EN_SZ 1
|
#define WLAN_ACT_POL_MSK 0x00000800
|
#define WLAN_ACT_POL_I_MSK 0xfffff7ff
|
#define WLAN_ACT_POL_SFT 11
|
#define WLAN_ACT_POL_HI 11
|
#define WLAN_ACT_POL_SZ 1
|
#define DUAL_ANT_EN_MSK 0x00001000
|
#define DUAL_ANT_EN_I_MSK 0xffffefff
|
#define DUAL_ANT_EN_SFT 12
|
#define DUAL_ANT_EN_HI 12
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#define DUAL_ANT_EN_SZ 1
|
#define TRSW_PHY_POL_MSK 0x00010000
|
#define TRSW_PHY_POL_I_MSK 0xfffeffff
|
#define TRSW_PHY_POL_SFT 16
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#define TRSW_PHY_POL_HI 16
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#define TRSW_PHY_POL_SZ 1
|
#define WIFI_TX_SW_POL_MSK 0x00020000
|
#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
|
#define WIFI_TX_SW_POL_SFT 17
|
#define WIFI_TX_SW_POL_HI 17
|
#define WIFI_TX_SW_POL_SZ 1
|
#define WIFI_RX_SW_POL_MSK 0x00040000
|
#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
|
#define WIFI_RX_SW_POL_SFT 18
|
#define WIFI_RX_SW_POL_HI 18
|
#define WIFI_RX_SW_POL_SZ 1
|
#define BT_SW_POL_MSK 0x00080000
|
#define BT_SW_POL_I_MSK 0xfff7ffff
|
#define BT_SW_POL_SFT 19
|
#define BT_SW_POL_HI 19
|
#define BT_SW_POL_SZ 1
|
#define BT_PRI_SMP_TIME_MSK 0x000000ff
|
#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
|
#define BT_PRI_SMP_TIME_SFT 0
|
#define BT_PRI_SMP_TIME_HI 7
|
#define BT_PRI_SMP_TIME_SZ 8
|
#define BT_STA_SMP_TIME_MSK 0x0000ff00
|
#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
|
#define BT_STA_SMP_TIME_SFT 8
|
#define BT_STA_SMP_TIME_HI 15
|
#define BT_STA_SMP_TIME_SZ 8
|
#define BEACON_TIMEOUT_MSK 0x00ff0000
|
#define BEACON_TIMEOUT_I_MSK 0xff00ffff
|
#define BEACON_TIMEOUT_SFT 16
|
#define BEACON_TIMEOUT_HI 23
|
#define BEACON_TIMEOUT_SZ 8
|
#define WLAN_REMAIN_TIME_MSK 0xff000000
|
#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
|
#define WLAN_REMAIN_TIME_SFT 24
|
#define WLAN_REMAIN_TIME_HI 31
|
#define WLAN_REMAIN_TIME_SZ 8
|
#define SW_MANUAL_EN_MSK 0x00000001
|
#define SW_MANUAL_EN_I_MSK 0xfffffffe
|
#define SW_MANUAL_EN_SFT 0
|
#define SW_MANUAL_EN_HI 0
|
#define SW_MANUAL_EN_SZ 1
|
#define SW_WL_TX_MSK 0x00000002
|
#define SW_WL_TX_I_MSK 0xfffffffd
|
#define SW_WL_TX_SFT 1
|
#define SW_WL_TX_HI 1
|
#define SW_WL_TX_SZ 1
|
#define SW_WL_RX_MSK 0x00000004
|
#define SW_WL_RX_I_MSK 0xfffffffb
|
#define SW_WL_RX_SFT 2
|
#define SW_WL_RX_HI 2
|
#define SW_WL_RX_SZ 1
|
#define SW_BT_TRX_MSK 0x00000008
|
#define SW_BT_TRX_I_MSK 0xfffffff7
|
#define SW_BT_TRX_SFT 3
|
#define SW_BT_TRX_HI 3
|
#define SW_BT_TRX_SZ 1
|
#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
|
#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
|
#define BT_TXBAR_MANUAL_EN_SFT 4
|
#define BT_TXBAR_MANUAL_EN_HI 4
|
#define BT_TXBAR_MANUAL_EN_SZ 1
|
#define BT_TXBAR_SET_MSK 0x00000020
|
#define BT_TXBAR_SET_I_MSK 0xffffffdf
|
#define BT_TXBAR_SET_SFT 5
|
#define BT_TXBAR_SET_HI 5
|
#define BT_TXBAR_SET_SZ 1
|
#define BT_BUSY_MANUAL_EN_MSK 0x00000100
|
#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
|
#define BT_BUSY_MANUAL_EN_SFT 8
|
#define BT_BUSY_MANUAL_EN_HI 8
|
#define BT_BUSY_MANUAL_EN_SZ 1
|
#define BT_BUSY_SET_MSK 0x00000200
|
#define BT_BUSY_SET_I_MSK 0xfffffdff
|
#define BT_BUSY_SET_SFT 9
|
#define BT_BUSY_SET_HI 9
|
#define BT_BUSY_SET_SZ 1
|
#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
|
#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
|
#define G0_PKT_CLS_MIB_EN_SFT 2
|
#define G0_PKT_CLS_MIB_EN_HI 2
|
#define G0_PKT_CLS_MIB_EN_SZ 1
|
#define G0_PKT_CLS_ONGOING_MSK 0x00000008
|
#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
|
#define G0_PKT_CLS_ONGOING_SFT 3
|
#define G0_PKT_CLS_ONGOING_HI 3
|
#define G0_PKT_CLS_ONGOING_SZ 1
|
#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
|
#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
|
#define G1_PKT_CLS_MIB_EN_SFT 4
|
#define G1_PKT_CLS_MIB_EN_HI 4
|
#define G1_PKT_CLS_MIB_EN_SZ 1
|
#define G1_PKT_CLS_ONGOING_MSK 0x00000020
|
#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
|
#define G1_PKT_CLS_ONGOING_SFT 5
|
#define G1_PKT_CLS_ONGOING_HI 5
|
#define G1_PKT_CLS_ONGOING_SZ 1
|
#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
|
#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
|
#define Q0_PKT_CLS_MIB_EN_SFT 6
|
#define Q0_PKT_CLS_MIB_EN_HI 6
|
#define Q0_PKT_CLS_MIB_EN_SZ 1
|
#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
|
#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
|
#define Q0_PKT_CLS_ONGOING_SFT 7
|
#define Q0_PKT_CLS_ONGOING_HI 7
|
#define Q0_PKT_CLS_ONGOING_SZ 1
|
#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
|
#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
|
#define Q1_PKT_CLS_MIB_EN_SFT 8
|
#define Q1_PKT_CLS_MIB_EN_HI 8
|
#define Q1_PKT_CLS_MIB_EN_SZ 1
|
#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
|
#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
|
#define Q1_PKT_CLS_ONGOING_SFT 9
|
#define Q1_PKT_CLS_ONGOING_HI 9
|
#define Q1_PKT_CLS_ONGOING_SZ 1
|
#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
|
#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
|
#define Q2_PKT_CLS_MIB_EN_SFT 10
|
#define Q2_PKT_CLS_MIB_EN_HI 10
|
#define Q2_PKT_CLS_MIB_EN_SZ 1
|
#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
|
#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
|
#define Q2_PKT_CLS_ONGOING_SFT 11
|
#define Q2_PKT_CLS_ONGOING_HI 11
|
#define Q2_PKT_CLS_ONGOING_SZ 1
|
#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
|
#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
|
#define Q3_PKT_CLS_MIB_EN_SFT 12
|
#define Q3_PKT_CLS_MIB_EN_HI 12
|
#define Q3_PKT_CLS_MIB_EN_SZ 1
|
#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
|
#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
|
#define Q3_PKT_CLS_ONGOING_SFT 13
|
#define Q3_PKT_CLS_ONGOING_HI 13
|
#define Q3_PKT_CLS_ONGOING_SZ 1
|
#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
|
#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
|
#define SCRT_PKT_CLS_MIB_EN_SFT 14
|
#define SCRT_PKT_CLS_MIB_EN_HI 14
|
#define SCRT_PKT_CLS_MIB_EN_SZ 1
|
#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
|
#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
|
#define SCRT_PKT_CLS_ONGOING_SFT 15
|
#define SCRT_PKT_CLS_ONGOING_HI 15
|
#define SCRT_PKT_CLS_ONGOING_SZ 1
|
#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
|
#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
|
#define MISC_PKT_CLS_MIB_EN_SFT 16
|
#define MISC_PKT_CLS_MIB_EN_HI 16
|
#define MISC_PKT_CLS_MIB_EN_SZ 1
|
#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
|
#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
|
#define MISC_PKT_CLS_ONGOING_SFT 17
|
#define MISC_PKT_CLS_ONGOING_HI 17
|
#define MISC_PKT_CLS_ONGOING_SZ 1
|
#define MTX_WSID0_SUCC_MSK 0x0000ffff
|
#define MTX_WSID0_SUCC_I_MSK 0xffff0000
|
#define MTX_WSID0_SUCC_SFT 0
|
#define MTX_WSID0_SUCC_HI 15
|
#define MTX_WSID0_SUCC_SZ 16
|
#define MTX_WSID0_FRM_MSK 0x0000ffff
|
#define MTX_WSID0_FRM_I_MSK 0xffff0000
|
#define MTX_WSID0_FRM_SFT 0
|
#define MTX_WSID0_FRM_HI 15
|
#define MTX_WSID0_FRM_SZ 16
|
#define MTX_WSID0_RETRY_MSK 0x0000ffff
|
#define MTX_WSID0_RETRY_I_MSK 0xffff0000
|
#define MTX_WSID0_RETRY_SFT 0
|
#define MTX_WSID0_RETRY_HI 15
|
#define MTX_WSID0_RETRY_SZ 16
|
#define MTX_WSID0_TOTAL_MSK 0x0000ffff
|
#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
|
#define MTX_WSID0_TOTAL_SFT 0
|
#define MTX_WSID0_TOTAL_HI 15
|
#define MTX_WSID0_TOTAL_SZ 16
|
#define MTX_GRP_MSK 0x000fffff
|
#define MTX_GRP_I_MSK 0xfff00000
|
#define MTX_GRP_SFT 0
|
#define MTX_GRP_HI 19
|
#define MTX_GRP_SZ 20
|
#define MTX_FAIL_MSK 0x0000ffff
|
#define MTX_FAIL_I_MSK 0xffff0000
|
#define MTX_FAIL_SFT 0
|
#define MTX_FAIL_HI 15
|
#define MTX_FAIL_SZ 16
|
#define MTX_RETRY_MSK 0x000fffff
|
#define MTX_RETRY_I_MSK 0xfff00000
|
#define MTX_RETRY_SFT 0
|
#define MTX_RETRY_HI 19
|
#define MTX_RETRY_SZ 20
|
#define MTX_MULTI_RETRY_MSK 0x000fffff
|
#define MTX_MULTI_RETRY_I_MSK 0xfff00000
|
#define MTX_MULTI_RETRY_SFT 0
|
#define MTX_MULTI_RETRY_HI 19
|
#define MTX_MULTI_RETRY_SZ 20
|
#define MTX_RTS_SUCC_MSK 0x0000ffff
|
#define MTX_RTS_SUCC_I_MSK 0xffff0000
|
#define MTX_RTS_SUCC_SFT 0
|
#define MTX_RTS_SUCC_HI 15
|
#define MTX_RTS_SUCC_SZ 16
|
#define MTX_RTS_FAIL_MSK 0x0000ffff
|
#define MTX_RTS_FAIL_I_MSK 0xffff0000
|
#define MTX_RTS_FAIL_SFT 0
|
#define MTX_RTS_FAIL_HI 15
|
#define MTX_RTS_FAIL_SZ 16
|
#define MTX_ACK_FAIL_MSK 0x0000ffff
|
#define MTX_ACK_FAIL_I_MSK 0xffff0000
|
#define MTX_ACK_FAIL_SFT 0
|
#define MTX_ACK_FAIL_HI 15
|
#define MTX_ACK_FAIL_SZ 16
|
#define MTX_FRM_MSK 0x000fffff
|
#define MTX_FRM_I_MSK 0xfff00000
|
#define MTX_FRM_SFT 0
|
#define MTX_FRM_HI 19
|
#define MTX_FRM_SZ 20
|
#define MTX_ACK_TX_MSK 0x0000ffff
|
#define MTX_ACK_TX_I_MSK 0xffff0000
|
#define MTX_ACK_TX_SFT 0
|
#define MTX_ACK_TX_HI 15
|
#define MTX_ACK_TX_SZ 16
|
#define MTX_CTS_TX_MSK 0x0000ffff
|
#define MTX_CTS_TX_I_MSK 0xffff0000
|
#define MTX_CTS_TX_SFT 0
|
#define MTX_CTS_TX_HI 15
|
#define MTX_CTS_TX_SZ 16
|
#define MRX_DUP_MSK 0x0000ffff
|
#define MRX_DUP_I_MSK 0xffff0000
|
#define MRX_DUP_SFT 0
|
#define MRX_DUP_HI 15
|
#define MRX_DUP_SZ 16
|
#define MRX_FRG_MSK 0x000fffff
|
#define MRX_FRG_I_MSK 0xfff00000
|
#define MRX_FRG_SFT 0
|
#define MRX_FRG_HI 19
|
#define MRX_FRG_SZ 20
|
#define MRX_GRP_MSK 0x000fffff
|
#define MRX_GRP_I_MSK 0xfff00000
|
#define MRX_GRP_SFT 0
|
#define MRX_GRP_HI 19
|
#define MRX_GRP_SZ 20
|
#define MRX_FCS_ERR_MSK 0x0000ffff
|
#define MRX_FCS_ERR_I_MSK 0xffff0000
|
#define MRX_FCS_ERR_SFT 0
|
#define MRX_FCS_ERR_HI 15
|
#define MRX_FCS_ERR_SZ 16
|
#define MRX_FCS_SUC_MSK 0x0000ffff
|
#define MRX_FCS_SUC_I_MSK 0xffff0000
|
#define MRX_FCS_SUC_SFT 0
|
#define MRX_FCS_SUC_HI 15
|
#define MRX_FCS_SUC_SZ 16
|
#define MRX_MISS_MSK 0x0000ffff
|
#define MRX_MISS_I_MSK 0xffff0000
|
#define MRX_MISS_SFT 0
|
#define MRX_MISS_HI 15
|
#define MRX_MISS_SZ 16
|
#define MRX_ALC_FAIL_MSK 0x0000ffff
|
#define MRX_ALC_FAIL_I_MSK 0xffff0000
|
#define MRX_ALC_FAIL_SFT 0
|
#define MRX_ALC_FAIL_HI 15
|
#define MRX_ALC_FAIL_SZ 16
|
#define MRX_DAT_NTF_MSK 0x0000ffff
|
#define MRX_DAT_NTF_I_MSK 0xffff0000
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#define MRX_DAT_NTF_SFT 0
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#define MRX_DAT_NTF_HI 15
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#define MRX_DAT_NTF_SZ 16
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#define MRX_RTS_NTF_MSK 0x0000ffff
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#define MRX_RTS_NTF_I_MSK 0xffff0000
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#define MRX_RTS_NTF_SFT 0
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#define MRX_RTS_NTF_HI 15
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#define MRX_RTS_NTF_SZ 16
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#define MRX_CTS_NTF_MSK 0x0000ffff
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#define MRX_CTS_NTF_I_MSK 0xffff0000
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#define MRX_CTS_NTF_SFT 0
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#define MRX_CTS_NTF_HI 15
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#define MRX_CTS_NTF_SZ 16
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#define MRX_ACK_NTF_MSK 0x0000ffff
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#define MRX_ACK_NTF_I_MSK 0xffff0000
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#define MRX_ACK_NTF_SFT 0
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#define MRX_ACK_NTF_HI 15
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#define MRX_ACK_NTF_SZ 16
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#define MRX_BA_NTF_MSK 0x0000ffff
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#define MRX_BA_NTF_I_MSK 0xffff0000
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#define MRX_BA_NTF_SFT 0
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#define MRX_BA_NTF_HI 15
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#define MRX_BA_NTF_SZ 16
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#define MRX_DATA_NTF_MSK 0x0000ffff
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#define MRX_DATA_NTF_I_MSK 0xffff0000
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#define MRX_DATA_NTF_SFT 0
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#define MRX_DATA_NTF_HI 15
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#define MRX_DATA_NTF_SZ 16
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#define MRX_MNG_NTF_MSK 0x0000ffff
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#define MRX_MNG_NTF_I_MSK 0xffff0000
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#define MRX_MNG_NTF_SFT 0
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#define MRX_MNG_NTF_HI 15
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#define MRX_MNG_NTF_SZ 16
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#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
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#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
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#define MRX_DAT_CRC_NTF_SFT 0
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#define MRX_DAT_CRC_NTF_HI 15
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#define MRX_DAT_CRC_NTF_SZ 16
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#define MRX_BAR_NTF_MSK 0x0000ffff
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#define MRX_BAR_NTF_I_MSK 0xffff0000
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#define MRX_BAR_NTF_SFT 0
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#define MRX_BAR_NTF_HI 15
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#define MRX_BAR_NTF_SZ 16
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#define MRX_MB_MISS_MSK 0x0000ffff
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#define MRX_MB_MISS_I_MSK 0xffff0000
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#define MRX_MB_MISS_SFT 0
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#define MRX_MB_MISS_HI 15
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#define MRX_MB_MISS_SZ 16
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#define MRX_NIDLE_MISS_MSK 0x0000ffff
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#define MRX_NIDLE_MISS_I_MSK 0xffff0000
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#define MRX_NIDLE_MISS_SFT 0
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#define MRX_NIDLE_MISS_HI 15
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#define MRX_NIDLE_MISS_SZ 16
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#define MRX_CSR_NTF_MSK 0x0000ffff
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#define MRX_CSR_NTF_I_MSK 0xffff0000
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#define MRX_CSR_NTF_SFT 0
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#define MRX_CSR_NTF_HI 15
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#define MRX_CSR_NTF_SZ 16
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#define DBG_Q0_SUCC_MSK 0x0000ffff
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#define DBG_Q0_SUCC_I_MSK 0xffff0000
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#define DBG_Q0_SUCC_SFT 0
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#define DBG_Q0_SUCC_HI 15
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#define DBG_Q0_SUCC_SZ 16
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#define DBG_Q0_FAIL_MSK 0x0000ffff
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#define DBG_Q0_FAIL_I_MSK 0xffff0000
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#define DBG_Q0_FAIL_SFT 0
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#define DBG_Q0_FAIL_HI 15
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#define DBG_Q0_FAIL_SZ 16
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#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
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#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
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#define DBG_Q0_ACK_SUCC_SFT 0
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#define DBG_Q0_ACK_SUCC_HI 15
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#define DBG_Q0_ACK_SUCC_SZ 16
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#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
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#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
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#define DBG_Q0_ACK_FAIL_SFT 0
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#define DBG_Q0_ACK_FAIL_HI 15
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#define DBG_Q0_ACK_FAIL_SZ 16
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#define DBG_Q1_SUCC_MSK 0x0000ffff
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#define DBG_Q1_SUCC_I_MSK 0xffff0000
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#define DBG_Q1_SUCC_SFT 0
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#define DBG_Q1_SUCC_HI 15
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#define DBG_Q1_SUCC_SZ 16
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#define DBG_Q1_FAIL_MSK 0x0000ffff
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#define DBG_Q1_FAIL_I_MSK 0xffff0000
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#define DBG_Q1_FAIL_SFT 0
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#define DBG_Q1_FAIL_HI 15
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#define DBG_Q1_FAIL_SZ 16
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#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
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#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
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#define DBG_Q1_ACK_SUCC_SFT 0
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#define DBG_Q1_ACK_SUCC_HI 15
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#define DBG_Q1_ACK_SUCC_SZ 16
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#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
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#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
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#define DBG_Q1_ACK_FAIL_SFT 0
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#define DBG_Q1_ACK_FAIL_HI 15
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#define DBG_Q1_ACK_FAIL_SZ 16
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#define DBG_Q2_SUCC_MSK 0x0000ffff
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#define DBG_Q2_SUCC_I_MSK 0xffff0000
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#define DBG_Q2_SUCC_SFT 0
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#define DBG_Q2_SUCC_HI 15
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#define DBG_Q2_SUCC_SZ 16
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#define DBG_Q2_FAIL_MSK 0x0000ffff
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#define DBG_Q2_FAIL_I_MSK 0xffff0000
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#define DBG_Q2_FAIL_SFT 0
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#define DBG_Q2_FAIL_HI 15
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#define DBG_Q2_FAIL_SZ 16
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#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
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#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
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#define DBG_Q2_ACK_SUCC_SFT 0
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#define DBG_Q2_ACK_SUCC_HI 15
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#define DBG_Q2_ACK_SUCC_SZ 16
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#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
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#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
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#define DBG_Q2_ACK_FAIL_SFT 0
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#define DBG_Q2_ACK_FAIL_HI 15
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#define DBG_Q2_ACK_FAIL_SZ 16
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#define DBG_Q3_SUCC_MSK 0x0000ffff
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#define DBG_Q3_SUCC_I_MSK 0xffff0000
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#define DBG_Q3_SUCC_SFT 0
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#define DBG_Q3_SUCC_HI 15
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#define DBG_Q3_SUCC_SZ 16
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#define DBG_Q3_FAIL_MSK 0x0000ffff
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#define DBG_Q3_FAIL_I_MSK 0xffff0000
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#define DBG_Q3_FAIL_SFT 0
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#define DBG_Q3_FAIL_HI 15
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#define DBG_Q3_FAIL_SZ 16
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#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
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#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
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#define DBG_Q3_ACK_SUCC_SFT 0
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#define DBG_Q3_ACK_SUCC_HI 15
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#define DBG_Q3_ACK_SUCC_SZ 16
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#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
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#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
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#define DBG_Q3_ACK_FAIL_SFT 0
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#define DBG_Q3_ACK_FAIL_HI 15
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#define DBG_Q3_ACK_FAIL_SZ 16
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#define SCRT_TKIP_CERR_MSK 0x000fffff
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#define SCRT_TKIP_CERR_I_MSK 0xfff00000
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#define SCRT_TKIP_CERR_SFT 0
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#define SCRT_TKIP_CERR_HI 19
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#define SCRT_TKIP_CERR_SZ 20
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#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
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#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
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#define SCRT_TKIP_MIC_ERR_SFT 0
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#define SCRT_TKIP_MIC_ERR_HI 19
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#define SCRT_TKIP_MIC_ERR_SZ 20
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#define SCRT_TKIP_RPLY_MSK 0x000fffff
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#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
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#define SCRT_TKIP_RPLY_SFT 0
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#define SCRT_TKIP_RPLY_HI 19
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#define SCRT_TKIP_RPLY_SZ 20
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#define SCRT_CCMP_RPLY_MSK 0x000fffff
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#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
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#define SCRT_CCMP_RPLY_SFT 0
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#define SCRT_CCMP_RPLY_HI 19
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#define SCRT_CCMP_RPLY_SZ 20
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#define SCRT_CCMP_CERR_MSK 0x000fffff
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#define SCRT_CCMP_CERR_I_MSK 0xfff00000
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#define SCRT_CCMP_CERR_SFT 0
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#define SCRT_CCMP_CERR_HI 19
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#define SCRT_CCMP_CERR_SZ 20
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#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
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#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
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#define DBG_LEN_CRC_FAIL_SFT 0
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#define DBG_LEN_CRC_FAIL_HI 15
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#define DBG_LEN_CRC_FAIL_SZ 16
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#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
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#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
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#define DBG_LEN_ALC_FAIL_SFT 0
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#define DBG_LEN_ALC_FAIL_HI 15
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#define DBG_LEN_ALC_FAIL_SZ 16
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#define DBG_AMPDU_PASS_MSK 0x0000ffff
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#define DBG_AMPDU_PASS_I_MSK 0xffff0000
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#define DBG_AMPDU_PASS_SFT 0
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#define DBG_AMPDU_PASS_HI 15
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#define DBG_AMPDU_PASS_SZ 16
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#define DBG_AMPDU_FAIL_MSK 0x0000ffff
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#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
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#define DBG_AMPDU_FAIL_SFT 0
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#define DBG_AMPDU_FAIL_HI 15
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#define DBG_AMPDU_FAIL_SZ 16
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#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
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#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
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#define RXID_ALC_CNT_FAIL_SFT 0
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#define RXID_ALC_CNT_FAIL_HI 15
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#define RXID_ALC_CNT_FAIL_SZ 16
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#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
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#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
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#define RXID_ALC_LEN_FAIL_SFT 0
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#define RXID_ALC_LEN_FAIL_HI 15
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#define RXID_ALC_LEN_FAIL_SZ 16
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#define CBR_RG_EN_MANUAL_MSK 0x00000001
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#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
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#define CBR_RG_EN_MANUAL_SFT 0
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#define CBR_RG_EN_MANUAL_HI 0
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#define CBR_RG_EN_MANUAL_SZ 1
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#define CBR_RG_TX_EN_MSK 0x00000002
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#define CBR_RG_TX_EN_I_MSK 0xfffffffd
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#define CBR_RG_TX_EN_SFT 1
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#define CBR_RG_TX_EN_HI 1
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#define CBR_RG_TX_EN_SZ 1
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#define CBR_RG_TX_PA_EN_MSK 0x00000004
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#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
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#define CBR_RG_TX_PA_EN_SFT 2
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#define CBR_RG_TX_PA_EN_HI 2
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#define CBR_RG_TX_PA_EN_SZ 1
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#define CBR_RG_TX_DAC_EN_MSK 0x00000008
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#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
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#define CBR_RG_TX_DAC_EN_SFT 3
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#define CBR_RG_TX_DAC_EN_HI 3
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#define CBR_RG_TX_DAC_EN_SZ 1
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#define CBR_RG_RX_AGC_MSK 0x00000010
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#define CBR_RG_RX_AGC_I_MSK 0xffffffef
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#define CBR_RG_RX_AGC_SFT 4
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#define CBR_RG_RX_AGC_HI 4
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#define CBR_RG_RX_AGC_SZ 1
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#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
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#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
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#define CBR_RG_RX_GAIN_MANUAL_SFT 5
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#define CBR_RG_RX_GAIN_MANUAL_HI 5
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#define CBR_RG_RX_GAIN_MANUAL_SZ 1
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#define CBR_RG_RFG_MSK 0x000000c0
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#define CBR_RG_RFG_I_MSK 0xffffff3f
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#define CBR_RG_RFG_SFT 6
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#define CBR_RG_RFG_HI 7
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#define CBR_RG_RFG_SZ 2
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#define CBR_RG_PGAG_MSK 0x00000f00
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#define CBR_RG_PGAG_I_MSK 0xfffff0ff
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#define CBR_RG_PGAG_SFT 8
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#define CBR_RG_PGAG_HI 11
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#define CBR_RG_PGAG_SZ 4
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#define CBR_RG_MODE_MSK 0x00003000
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#define CBR_RG_MODE_I_MSK 0xffffcfff
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#define CBR_RG_MODE_SFT 12
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#define CBR_RG_MODE_HI 13
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#define CBR_RG_MODE_SZ 2
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#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
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#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
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#define CBR_RG_EN_TX_TRSW_SFT 14
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#define CBR_RG_EN_TX_TRSW_HI 14
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#define CBR_RG_EN_TX_TRSW_SZ 1
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#define CBR_RG_EN_SX_MSK 0x00008000
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#define CBR_RG_EN_SX_I_MSK 0xffff7fff
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#define CBR_RG_EN_SX_SFT 15
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#define CBR_RG_EN_SX_HI 15
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#define CBR_RG_EN_SX_SZ 1
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#define CBR_RG_EN_RX_LNA_MSK 0x00010000
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#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
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#define CBR_RG_EN_RX_LNA_SFT 16
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#define CBR_RG_EN_RX_LNA_HI 16
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#define CBR_RG_EN_RX_LNA_SZ 1
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#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
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#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
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#define CBR_RG_EN_RX_MIXER_SFT 17
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#define CBR_RG_EN_RX_MIXER_HI 17
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#define CBR_RG_EN_RX_MIXER_SZ 1
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#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
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#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
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#define CBR_RG_EN_RX_DIV2_SFT 18
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#define CBR_RG_EN_RX_DIV2_HI 18
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#define CBR_RG_EN_RX_DIV2_SZ 1
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#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
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#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
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#define CBR_RG_EN_RX_LOBUF_SFT 19
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#define CBR_RG_EN_RX_LOBUF_HI 19
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#define CBR_RG_EN_RX_LOBUF_SZ 1
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#define CBR_RG_EN_RX_TZ_MSK 0x00100000
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#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
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#define CBR_RG_EN_RX_TZ_SFT 20
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#define CBR_RG_EN_RX_TZ_HI 20
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#define CBR_RG_EN_RX_TZ_SZ 1
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#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
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#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
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#define CBR_RG_EN_RX_FILTER_SFT 21
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#define CBR_RG_EN_RX_FILTER_HI 21
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#define CBR_RG_EN_RX_FILTER_SZ 1
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#define CBR_RG_EN_RX_HPF_MSK 0x00400000
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#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
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#define CBR_RG_EN_RX_HPF_SFT 22
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#define CBR_RG_EN_RX_HPF_HI 22
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#define CBR_RG_EN_RX_HPF_SZ 1
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#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
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#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
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#define CBR_RG_EN_RX_RSSI_SFT 23
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#define CBR_RG_EN_RX_RSSI_HI 23
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#define CBR_RG_EN_RX_RSSI_SZ 1
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#define CBR_RG_EN_ADC_MSK 0x01000000
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#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
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#define CBR_RG_EN_ADC_SFT 24
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#define CBR_RG_EN_ADC_HI 24
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#define CBR_RG_EN_ADC_SZ 1
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#define CBR_RG_EN_TX_MOD_MSK 0x02000000
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#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
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#define CBR_RG_EN_TX_MOD_SFT 25
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#define CBR_RG_EN_TX_MOD_HI 25
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#define CBR_RG_EN_TX_MOD_SZ 1
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#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
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#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
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#define CBR_RG_EN_TX_DIV2_SFT 26
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#define CBR_RG_EN_TX_DIV2_HI 26
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#define CBR_RG_EN_TX_DIV2_SZ 1
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#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
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#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
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#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
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#define CBR_RG_EN_TX_DIV2_BUF_HI 27
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#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
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#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
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#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
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#define CBR_RG_EN_TX_LOBF_SFT 28
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#define CBR_RG_EN_TX_LOBF_HI 28
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#define CBR_RG_EN_TX_LOBF_SZ 1
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#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
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#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
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#define CBR_RG_EN_RX_LOBF_SFT 29
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#define CBR_RG_EN_RX_LOBF_HI 29
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#define CBR_RG_EN_RX_LOBF_SZ 1
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#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
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#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
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#define CBR_RG_SEL_DPLL_CLK_SFT 30
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#define CBR_RG_SEL_DPLL_CLK_HI 30
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#define CBR_RG_SEL_DPLL_CLK_SZ 1
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#define CBR_RG_EN_TX_DPD_MSK 0x00000001
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#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
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#define CBR_RG_EN_TX_DPD_SFT 0
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#define CBR_RG_EN_TX_DPD_HI 0
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#define CBR_RG_EN_TX_DPD_SZ 1
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#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
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#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
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#define CBR_RG_EN_TX_TSSI_SFT 1
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#define CBR_RG_EN_TX_TSSI_HI 1
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#define CBR_RG_EN_TX_TSSI_SZ 1
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#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
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#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
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#define CBR_RG_EN_RX_IQCAL_SFT 2
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#define CBR_RG_EN_RX_IQCAL_HI 2
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#define CBR_RG_EN_RX_IQCAL_SZ 1
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#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
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#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
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#define CBR_RG_EN_TX_DAC_CAL_SFT 3
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#define CBR_RG_EN_TX_DAC_CAL_HI 3
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#define CBR_RG_EN_TX_DAC_CAL_SZ 1
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#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
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#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
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#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
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#define CBR_RG_EN_TX_SELF_MIXER_HI 4
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#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
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#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
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#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
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#define CBR_RG_EN_TX_DAC_OUT_SFT 5
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#define CBR_RG_EN_TX_DAC_OUT_HI 5
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#define CBR_RG_EN_TX_DAC_OUT_SZ 1
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#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
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#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
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#define CBR_RG_EN_LDO_RX_FE_SFT 6
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#define CBR_RG_EN_LDO_RX_FE_HI 6
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#define CBR_RG_EN_LDO_RX_FE_SZ 1
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#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
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#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
|
#define CBR_RG_EN_LDO_ABB_SFT 7
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#define CBR_RG_EN_LDO_ABB_HI 7
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#define CBR_RG_EN_LDO_ABB_SZ 1
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#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
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#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
|
#define CBR_RG_EN_LDO_AFE_SFT 8
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#define CBR_RG_EN_LDO_AFE_HI 8
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#define CBR_RG_EN_LDO_AFE_SZ 1
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#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
|
#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
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#define CBR_RG_EN_SX_CHPLDO_SFT 9
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#define CBR_RG_EN_SX_CHPLDO_HI 9
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#define CBR_RG_EN_SX_CHPLDO_SZ 1
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#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
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#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
|
#define CBR_RG_EN_SX_LOBFLDO_SFT 10
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#define CBR_RG_EN_SX_LOBFLDO_HI 10
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#define CBR_RG_EN_SX_LOBFLDO_SZ 1
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#define CBR_RG_EN_IREF_RX_MSK 0x00000800
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#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
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#define CBR_RG_EN_IREF_RX_SFT 11
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#define CBR_RG_EN_IREF_RX_HI 11
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#define CBR_RG_EN_IREF_RX_SZ 1
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#define CBR_RG_DCDC_MODE_MSK 0x00001000
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#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
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#define CBR_RG_DCDC_MODE_SFT 12
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#define CBR_RG_DCDC_MODE_HI 12
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#define CBR_RG_DCDC_MODE_SZ 1
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#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
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#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
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#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
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#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
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#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
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#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
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#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
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#define CBR_RG_LDO_LEVEL_ABB_SFT 3
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#define CBR_RG_LDO_LEVEL_ABB_HI 5
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#define CBR_RG_LDO_LEVEL_ABB_SZ 3
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#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
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#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
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#define CBR_RG_LDO_LEVEL_AFE_SFT 6
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#define CBR_RG_LDO_LEVEL_AFE_HI 8
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#define CBR_RG_LDO_LEVEL_AFE_SZ 3
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#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
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#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
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#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
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#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
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#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
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#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
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#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
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#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
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#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
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#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
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#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
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#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
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#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
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#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
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#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
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#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
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#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
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#define CBR_RG_DP_LDO_LEVEL_SFT 18
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#define CBR_RG_DP_LDO_LEVEL_HI 20
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#define CBR_RG_DP_LDO_LEVEL_SZ 3
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#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
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#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
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#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
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#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
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#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
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#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
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#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
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#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
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#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
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#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
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#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
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#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
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#define CBR_RG_BUCK_LEVEL_SFT 27
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#define CBR_RG_BUCK_LEVEL_HI 29
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#define CBR_RG_BUCK_LEVEL_SZ 3
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#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
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#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
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#define CBR_RG_EN_RX_PADSW_SFT 0
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#define CBR_RG_EN_RX_PADSW_HI 0
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#define CBR_RG_EN_RX_PADSW_SZ 1
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#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
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#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
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#define CBR_RG_EN_RX_TESTNODE_SFT 1
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#define CBR_RG_EN_RX_TESTNODE_HI 1
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#define CBR_RG_EN_RX_TESTNODE_SZ 1
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#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
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#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
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#define CBR_RG_RX_ABBCFIX_SFT 2
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#define CBR_RG_RX_ABBCFIX_HI 2
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#define CBR_RG_RX_ABBCFIX_SZ 1
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#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
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#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
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#define CBR_RG_RX_ABBCTUNE_SFT 3
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#define CBR_RG_RX_ABBCTUNE_HI 8
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#define CBR_RG_RX_ABBCTUNE_SZ 6
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#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
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#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
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#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
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#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
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#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
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#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
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#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
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#define CBR_RG_RX_ABB_N_MODE_SFT 10
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#define CBR_RG_RX_ABB_N_MODE_HI 10
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#define CBR_RG_RX_ABB_N_MODE_SZ 1
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#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
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#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
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#define CBR_RG_RX_EN_LOOPA_SFT 11
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#define CBR_RG_RX_EN_LOOPA_HI 11
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#define CBR_RG_RX_EN_LOOPA_SZ 1
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#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
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#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
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#define CBR_RG_RX_FILTERI1ST_SFT 12
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#define CBR_RG_RX_FILTERI1ST_HI 13
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#define CBR_RG_RX_FILTERI1ST_SZ 2
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#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
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#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
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#define CBR_RG_RX_FILTERI2ND_SFT 14
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#define CBR_RG_RX_FILTERI2ND_HI 15
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#define CBR_RG_RX_FILTERI2ND_SZ 2
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#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
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#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
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#define CBR_RG_RX_FILTERI3RD_SFT 16
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#define CBR_RG_RX_FILTERI3RD_HI 17
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#define CBR_RG_RX_FILTERI3RD_SZ 2
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#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
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#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
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#define CBR_RG_RX_FILTERI_COURSE_SFT 18
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#define CBR_RG_RX_FILTERI_COURSE_HI 19
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#define CBR_RG_RX_FILTERI_COURSE_SZ 2
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#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
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#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
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#define CBR_RG_RX_FILTERVCM_SFT 20
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#define CBR_RG_RX_FILTERVCM_HI 21
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#define CBR_RG_RX_FILTERVCM_SZ 2
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#define CBR_RG_RX_HPF3M_MSK 0x00400000
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#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
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#define CBR_RG_RX_HPF3M_SFT 22
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#define CBR_RG_RX_HPF3M_HI 22
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#define CBR_RG_RX_HPF3M_SZ 1
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#define CBR_RG_RX_HPF300K_MSK 0x00800000
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#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
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#define CBR_RG_RX_HPF300K_SFT 23
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#define CBR_RG_RX_HPF300K_HI 23
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#define CBR_RG_RX_HPF300K_SZ 1
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#define CBR_RG_RX_HPFI_MSK 0x03000000
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#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
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#define CBR_RG_RX_HPFI_SFT 24
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#define CBR_RG_RX_HPFI_HI 25
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#define CBR_RG_RX_HPFI_SZ 2
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#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
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#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
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#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
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#define CBR_RG_RX_HPF_FINALCORNER_HI 27
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#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
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#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
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#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
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#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
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#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
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#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
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#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
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#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
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#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
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#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
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#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
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#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
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#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
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#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
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#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
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#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
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#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
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#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
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#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
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#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
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#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
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#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
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#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
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#define CBR_RG_RX_HPF_VCMCON2_SFT 6
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#define CBR_RG_RX_HPF_VCMCON2_HI 7
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#define CBR_RG_RX_HPF_VCMCON2_SZ 2
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#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
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#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
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#define CBR_RG_RX_HPF_VCMCON_SFT 8
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#define CBR_RG_RX_HPF_VCMCON_HI 9
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#define CBR_RG_RX_HPF_VCMCON_SZ 2
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#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
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#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
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#define CBR_RG_RX_OUTVCM_SFT 10
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#define CBR_RG_RX_OUTVCM_HI 11
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#define CBR_RG_RX_OUTVCM_SZ 2
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#define CBR_RG_RX_TZI_MSK 0x00003000
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#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
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#define CBR_RG_RX_TZI_SFT 12
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#define CBR_RG_RX_TZI_HI 13
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#define CBR_RG_RX_TZI_SZ 2
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#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
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#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
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#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
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#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
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#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
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#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
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#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
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#define CBR_RG_RX_TZ_VCM_SFT 15
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#define CBR_RG_RX_TZ_VCM_HI 16
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#define CBR_RG_RX_TZ_VCM_SZ 2
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#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
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#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
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#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
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#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
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#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
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#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
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#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
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#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
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#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
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#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
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#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
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#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
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#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
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#define CBR_RG_RX_ADCRSSI_VCM_HI 22
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#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
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#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
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#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
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#define CBR_RG_RX_REC_LPFCORNER_SFT 23
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#define CBR_RG_RX_REC_LPFCORNER_HI 24
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#define CBR_RG_RX_REC_LPFCORNER_SZ 2
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#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
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#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
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#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
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#define CBR_RG_RSSI_CLOCK_GATING_HI 25
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#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
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#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
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#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
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#define CBR_RG_TXPGA_CAPSW_SFT 0
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#define CBR_RG_TXPGA_CAPSW_HI 1
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#define CBR_RG_TXPGA_CAPSW_SZ 2
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#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
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#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
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#define CBR_RG_TXPGA_MAIN_SFT 2
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#define CBR_RG_TXPGA_MAIN_HI 7
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#define CBR_RG_TXPGA_MAIN_SZ 6
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#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
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#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
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#define CBR_RG_TXPGA_STEER_SFT 8
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#define CBR_RG_TXPGA_STEER_HI 13
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#define CBR_RG_TXPGA_STEER_SZ 6
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#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
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#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
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#define CBR_RG_TXMOD_GMCELL_SFT 14
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#define CBR_RG_TXMOD_GMCELL_HI 15
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#define CBR_RG_TXMOD_GMCELL_SZ 2
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#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
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#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
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#define CBR_RG_TXLPF_GMCELL_SFT 16
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#define CBR_RG_TXLPF_GMCELL_HI 17
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#define CBR_RG_TXLPF_GMCELL_SZ 2
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#define CBR_RG_PACELL_EN_MSK 0x001c0000
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#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
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#define CBR_RG_PACELL_EN_SFT 18
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#define CBR_RG_PACELL_EN_HI 20
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#define CBR_RG_PACELL_EN_SZ 3
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#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
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#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
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#define CBR_RG_PABIAS_CTRL_SFT 21
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#define CBR_RG_PABIAS_CTRL_HI 24
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#define CBR_RG_PABIAS_CTRL_SZ 4
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#define CBR_RG_PABIAS_AB_MSK 0x02000000
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#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
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#define CBR_RG_PABIAS_AB_SFT 25
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#define CBR_RG_PABIAS_AB_HI 25
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#define CBR_RG_PABIAS_AB_SZ 1
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#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
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#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
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#define CBR_RG_TX_DIV_VSET_SFT 26
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#define CBR_RG_TX_DIV_VSET_HI 27
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#define CBR_RG_TX_DIV_VSET_SZ 2
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#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
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#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
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#define CBR_RG_TX_LOBUF_VSET_SFT 28
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#define CBR_RG_TX_LOBUF_VSET_HI 29
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#define CBR_RG_TX_LOBUF_VSET_SZ 2
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#define CBR_RG_RX_SQDC_MSK 0x00000007
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#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
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#define CBR_RG_RX_SQDC_SFT 0
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#define CBR_RG_RX_SQDC_HI 2
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#define CBR_RG_RX_SQDC_SZ 3
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#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
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#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
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#define CBR_RG_RX_DIV2_CORE_SFT 3
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#define CBR_RG_RX_DIV2_CORE_HI 4
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#define CBR_RG_RX_DIV2_CORE_SZ 2
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#define CBR_RG_RX_LOBUF_MSK 0x00000060
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#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
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#define CBR_RG_RX_LOBUF_SFT 5
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#define CBR_RG_RX_LOBUF_HI 6
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#define CBR_RG_RX_LOBUF_SZ 2
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#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
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#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
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#define CBR_RG_TX_DPDGM_BIAS_SFT 7
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#define CBR_RG_TX_DPDGM_BIAS_HI 10
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#define CBR_RG_TX_DPDGM_BIAS_SZ 4
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#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
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#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
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#define CBR_RG_TX_DPD_DIV_SFT 11
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#define CBR_RG_TX_DPD_DIV_HI 14
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#define CBR_RG_TX_DPD_DIV_SZ 4
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#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
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#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
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#define CBR_RG_TX_TSSI_BIAS_SFT 15
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#define CBR_RG_TX_TSSI_BIAS_HI 17
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#define CBR_RG_TX_TSSI_BIAS_SZ 3
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#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
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#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
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#define CBR_RG_TX_TSSI_DIV_SFT 18
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#define CBR_RG_TX_TSSI_DIV_HI 20
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#define CBR_RG_TX_TSSI_DIV_SZ 3
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#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
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#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
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#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
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#define CBR_RG_TX_TSSI_TESTMODE_HI 21
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#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
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#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
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#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
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#define CBR_RG_TX_TSSI_TEST_SFT 22
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#define CBR_RG_TX_TSSI_TEST_HI 23
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#define CBR_RG_TX_TSSI_TEST_SZ 2
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#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
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#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
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#define CBR_RG_RX_HG_LNA_GC_SFT 0
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#define CBR_RG_RX_HG_LNA_GC_HI 1
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#define CBR_RG_RX_HG_LNA_GC_SZ 2
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#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
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#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
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#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
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#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
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#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
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#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
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#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
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#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
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#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
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#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
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#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
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#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
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#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
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#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
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#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
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#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
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#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
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#define CBR_RG_RX_HG_TZ_GC_SFT 14
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#define CBR_RG_RX_HG_TZ_GC_HI 15
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#define CBR_RG_RX_HG_TZ_GC_SZ 2
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#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
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#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
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#define CBR_RG_RX_HG_TZ_CAP_SFT 16
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#define CBR_RG_RX_HG_TZ_CAP_HI 18
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#define CBR_RG_RX_HG_TZ_CAP_SZ 3
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#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
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#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
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#define CBR_RG_RX_MG_LNA_GC_SFT 0
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#define CBR_RG_RX_MG_LNA_GC_HI 1
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#define CBR_RG_RX_MG_LNA_GC_SZ 2
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#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
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#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
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#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
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#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
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#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
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#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
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#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
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#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
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#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
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#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
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#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
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#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
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#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
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#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
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#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
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#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
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#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
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#define CBR_RG_RX_MG_TZ_GC_SFT 14
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#define CBR_RG_RX_MG_TZ_GC_HI 15
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#define CBR_RG_RX_MG_TZ_GC_SZ 2
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#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
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#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
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#define CBR_RG_RX_MG_TZ_CAP_SFT 16
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#define CBR_RG_RX_MG_TZ_CAP_HI 18
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#define CBR_RG_RX_MG_TZ_CAP_SZ 3
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#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
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#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
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#define CBR_RG_RX_LG_LNA_GC_SFT 0
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#define CBR_RG_RX_LG_LNA_GC_HI 1
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#define CBR_RG_RX_LG_LNA_GC_SZ 2
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#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
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#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
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#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
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#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
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#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
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#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
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#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
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#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
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#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
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#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
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#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
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#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
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#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
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#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
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#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
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#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
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#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
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#define CBR_RG_RX_LG_TZ_GC_SFT 14
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#define CBR_RG_RX_LG_TZ_GC_HI 15
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#define CBR_RG_RX_LG_TZ_GC_SZ 2
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#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
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#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
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#define CBR_RG_RX_LG_TZ_CAP_SFT 16
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#define CBR_RG_RX_LG_TZ_CAP_HI 18
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#define CBR_RG_RX_LG_TZ_CAP_SZ 3
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#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
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#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
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#define CBR_RG_RX_ULG_LNA_GC_SFT 0
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#define CBR_RG_RX_ULG_LNA_GC_HI 1
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#define CBR_RG_RX_ULG_LNA_GC_SZ 2
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#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
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#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
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#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
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#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
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#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
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#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
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#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
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#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
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#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
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#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
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#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
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#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
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#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
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#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
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#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
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#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
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#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
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#define CBR_RG_RX_ULG_TZ_GC_SFT 14
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#define CBR_RG_RX_ULG_TZ_GC_HI 15
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#define CBR_RG_RX_ULG_TZ_GC_SZ 2
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#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
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#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
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#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
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#define CBR_RG_RX_ULG_TZ_CAP_HI 18
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#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
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#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
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#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
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#define CBR_RG_HPF1_FAST_SET_X_SFT 0
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#define CBR_RG_HPF1_FAST_SET_X_HI 0
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#define CBR_RG_HPF1_FAST_SET_X_SZ 1
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#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
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#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
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#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
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#define CBR_RG_HPF1_FAST_SET_Y_HI 1
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#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
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#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
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#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
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#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
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#define CBR_RG_HPF1_FAST_SET_Z_HI 2
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#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
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#define CBR_RG_HPF_T1A_MSK 0x00000018
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#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
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#define CBR_RG_HPF_T1A_SFT 3
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#define CBR_RG_HPF_T1A_HI 4
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#define CBR_RG_HPF_T1A_SZ 2
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#define CBR_RG_HPF_T1B_MSK 0x00000060
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#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
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#define CBR_RG_HPF_T1B_SFT 5
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#define CBR_RG_HPF_T1B_HI 6
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#define CBR_RG_HPF_T1B_SZ 2
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#define CBR_RG_HPF_T1C_MSK 0x00000180
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#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
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#define CBR_RG_HPF_T1C_SFT 7
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#define CBR_RG_HPF_T1C_HI 8
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#define CBR_RG_HPF_T1C_SZ 2
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#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
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#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
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#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
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#define CBR_RG_RX_LNA_TRI_SEL_HI 10
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#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
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#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
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#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
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#define CBR_RG_RX_LNA_SETTLE_SFT 11
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#define CBR_RG_RX_LNA_SETTLE_HI 12
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#define CBR_RG_RX_LNA_SETTLE_SZ 2
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#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
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#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
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#define CBR_RG_ADC_CLKSEL_SFT 0
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#define CBR_RG_ADC_CLKSEL_HI 0
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#define CBR_RG_ADC_CLKSEL_SZ 1
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#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
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#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
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#define CBR_RG_ADC_DIBIAS_SFT 1
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#define CBR_RG_ADC_DIBIAS_HI 2
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#define CBR_RG_ADC_DIBIAS_SZ 2
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#define CBR_RG_ADC_DIVR_MSK 0x00000008
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#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
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#define CBR_RG_ADC_DIVR_SFT 3
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#define CBR_RG_ADC_DIVR_HI 3
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#define CBR_RG_ADC_DIVR_SZ 1
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#define CBR_RG_ADC_DVCMI_MSK 0x00000030
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#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
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#define CBR_RG_ADC_DVCMI_SFT 4
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#define CBR_RG_ADC_DVCMI_HI 5
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#define CBR_RG_ADC_DVCMI_SZ 2
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#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
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#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
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#define CBR_RG_ADC_SAMSEL_SFT 6
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#define CBR_RG_ADC_SAMSEL_HI 9
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#define CBR_RG_ADC_SAMSEL_SZ 4
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#define CBR_RG_ADC_STNBY_MSK 0x00000400
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#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
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#define CBR_RG_ADC_STNBY_SFT 10
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#define CBR_RG_ADC_STNBY_HI 10
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#define CBR_RG_ADC_STNBY_SZ 1
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#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
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#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
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#define CBR_RG_ADC_TESTMODE_SFT 11
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#define CBR_RG_ADC_TESTMODE_HI 11
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#define CBR_RG_ADC_TESTMODE_SZ 1
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#define CBR_RG_ADC_TSEL_MSK 0x0000f000
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#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
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#define CBR_RG_ADC_TSEL_SFT 12
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#define CBR_RG_ADC_TSEL_HI 15
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#define CBR_RG_ADC_TSEL_SZ 4
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#define CBR_RG_ADC_VRSEL_MSK 0x00030000
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#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
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#define CBR_RG_ADC_VRSEL_SFT 16
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#define CBR_RG_ADC_VRSEL_HI 17
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#define CBR_RG_ADC_VRSEL_SZ 2
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#define CBR_RG_DICMP_MSK 0x000c0000
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#define CBR_RG_DICMP_I_MSK 0xfff3ffff
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#define CBR_RG_DICMP_SFT 18
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#define CBR_RG_DICMP_HI 19
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#define CBR_RG_DICMP_SZ 2
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#define CBR_RG_DIOP_MSK 0x00300000
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#define CBR_RG_DIOP_I_MSK 0xffcfffff
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#define CBR_RG_DIOP_SFT 20
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#define CBR_RG_DIOP_HI 21
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#define CBR_RG_DIOP_SZ 2
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#define CBR_RG_DACI1ST_MSK 0x00000003
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#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
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#define CBR_RG_DACI1ST_SFT 0
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#define CBR_RG_DACI1ST_HI 1
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#define CBR_RG_DACI1ST_SZ 2
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#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
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#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
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#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
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#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
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#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
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#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
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#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
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#define CBR_RG_TX_DACLPF_IFINE_SFT 4
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#define CBR_RG_TX_DACLPF_IFINE_HI 5
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#define CBR_RG_TX_DACLPF_IFINE_SZ 2
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#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
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#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
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#define CBR_RG_TX_DACLPF_VCM_SFT 6
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#define CBR_RG_TX_DACLPF_VCM_HI 7
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#define CBR_RG_TX_DACLPF_VCM_SZ 2
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#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
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#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
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#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
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#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
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#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
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#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
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#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
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#define CBR_RG_TX_DAC_IBIAS_SFT 9
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#define CBR_RG_TX_DAC_IBIAS_HI 10
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#define CBR_RG_TX_DAC_IBIAS_SZ 2
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#define CBR_RG_TX_DAC_OS_MSK 0x00003800
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#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
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#define CBR_RG_TX_DAC_OS_SFT 11
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#define CBR_RG_TX_DAC_OS_HI 13
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#define CBR_RG_TX_DAC_OS_SZ 3
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#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
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#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
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#define CBR_RG_TX_DAC_RCAL_SFT 14
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#define CBR_RG_TX_DAC_RCAL_HI 15
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#define CBR_RG_TX_DAC_RCAL_SZ 2
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#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
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#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
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#define CBR_RG_TX_DAC_TSEL_SFT 16
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#define CBR_RG_TX_DAC_TSEL_HI 19
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#define CBR_RG_TX_DAC_TSEL_SZ 4
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#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
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#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
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#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
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#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
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#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
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#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
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#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
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#define CBR_RG_TXLPF_BYPASS_SFT 21
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#define CBR_RG_TXLPF_BYPASS_HI 21
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#define CBR_RG_TXLPF_BYPASS_SZ 1
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#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
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#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
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#define CBR_RG_TXLPF_BOOSTI_SFT 22
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#define CBR_RG_TXLPF_BOOSTI_HI 22
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#define CBR_RG_TXLPF_BOOSTI_SZ 1
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#define CBR_RG_EN_SX_R3_MSK 0x00000001
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#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
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#define CBR_RG_EN_SX_R3_SFT 0
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#define CBR_RG_EN_SX_R3_HI 0
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#define CBR_RG_EN_SX_R3_SZ 1
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#define CBR_RG_EN_SX_CH_MSK 0x00000002
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#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
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#define CBR_RG_EN_SX_CH_SFT 1
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#define CBR_RG_EN_SX_CH_HI 1
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#define CBR_RG_EN_SX_CH_SZ 1
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#define CBR_RG_EN_SX_CHP_MSK 0x00000004
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#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
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#define CBR_RG_EN_SX_CHP_SFT 2
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#define CBR_RG_EN_SX_CHP_HI 2
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#define CBR_RG_EN_SX_CHP_SZ 1
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#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
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#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
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#define CBR_RG_EN_SX_DIVCK_SFT 3
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#define CBR_RG_EN_SX_DIVCK_HI 3
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#define CBR_RG_EN_SX_DIVCK_SZ 1
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#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
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#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
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#define CBR_RG_EN_SX_VCOBF_SFT 4
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#define CBR_RG_EN_SX_VCOBF_HI 4
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#define CBR_RG_EN_SX_VCOBF_SZ 1
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#define CBR_RG_EN_SX_VCO_MSK 0x00000020
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#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
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#define CBR_RG_EN_SX_VCO_SFT 5
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#define CBR_RG_EN_SX_VCO_HI 5
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#define CBR_RG_EN_SX_VCO_SZ 1
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#define CBR_RG_EN_SX_MOD_MSK 0x00000040
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#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
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#define CBR_RG_EN_SX_MOD_SFT 6
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#define CBR_RG_EN_SX_MOD_HI 6
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#define CBR_RG_EN_SX_MOD_SZ 1
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#define CBR_RG_EN_SX_LCK_MSK 0x00000080
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#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
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#define CBR_RG_EN_SX_LCK_SFT 7
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#define CBR_RG_EN_SX_LCK_HI 7
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#define CBR_RG_EN_SX_LCK_SZ 1
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#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
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#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
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#define CBR_RG_EN_SX_DITHER_SFT 8
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#define CBR_RG_EN_SX_DITHER_HI 8
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#define CBR_RG_EN_SX_DITHER_SZ 1
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#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
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#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
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#define CBR_RG_EN_SX_DELCAL_SFT 9
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#define CBR_RG_EN_SX_DELCAL_HI 9
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#define CBR_RG_EN_SX_DELCAL_SZ 1
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#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
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#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
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#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
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#define CBR_RG_EN_SX_PC_BYPASS_HI 10
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#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
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#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
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#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
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#define CBR_RG_EN_SX_VT_MON_SFT 11
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#define CBR_RG_EN_SX_VT_MON_HI 11
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#define CBR_RG_EN_SX_VT_MON_SZ 1
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#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
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#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
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#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
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#define CBR_RG_EN_SX_VT_MON_DG_HI 12
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#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
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#define CBR_RG_EN_SX_DIV_MSK 0x00002000
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#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
|
#define CBR_RG_EN_SX_DIV_SFT 13
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#define CBR_RG_EN_SX_DIV_HI 13
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#define CBR_RG_EN_SX_DIV_SZ 1
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#define CBR_RG_EN_SX_LPF_MSK 0x00004000
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#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
|
#define CBR_RG_EN_SX_LPF_SFT 14
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#define CBR_RG_EN_SX_LPF_HI 14
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#define CBR_RG_EN_SX_LPF_SZ 1
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#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
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#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
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#define CBR_RG_SX_RFCTRL_F_SFT 0
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#define CBR_RG_SX_RFCTRL_F_HI 23
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#define CBR_RG_SX_RFCTRL_F_SZ 24
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#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
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#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
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#define CBR_RG_SX_SEL_CP_SFT 24
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#define CBR_RG_SX_SEL_CP_HI 27
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#define CBR_RG_SX_SEL_CP_SZ 4
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#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
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#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
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#define CBR_RG_SX_SEL_CS_SFT 28
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#define CBR_RG_SX_SEL_CS_HI 31
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#define CBR_RG_SX_SEL_CS_SZ 4
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#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
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#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
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#define CBR_RG_SX_RFCTRL_CH_SFT 0
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#define CBR_RG_SX_RFCTRL_CH_HI 10
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#define CBR_RG_SX_RFCTRL_CH_SZ 11
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#define CBR_RG_SX_SEL_C3_MSK 0x00007800
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#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
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#define CBR_RG_SX_SEL_C3_SFT 11
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#define CBR_RG_SX_SEL_C3_HI 14
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#define CBR_RG_SX_SEL_C3_SZ 4
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#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
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#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
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#define CBR_RG_SX_SEL_RS_SFT 15
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#define CBR_RG_SX_SEL_RS_HI 19
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#define CBR_RG_SX_SEL_RS_SZ 5
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#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
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#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
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#define CBR_RG_SX_SEL_R3_SFT 20
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#define CBR_RG_SX_SEL_R3_HI 24
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#define CBR_RG_SX_SEL_R3_SZ 5
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#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
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#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
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#define CBR_RG_SX_SEL_ICHP_SFT 0
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#define CBR_RG_SX_SEL_ICHP_HI 4
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#define CBR_RG_SX_SEL_ICHP_SZ 5
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#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
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#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
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#define CBR_RG_SX_SEL_PCHP_SFT 5
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#define CBR_RG_SX_SEL_PCHP_HI 9
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#define CBR_RG_SX_SEL_PCHP_SZ 5
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#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
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#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
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#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
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#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
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#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
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#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
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#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
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#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
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#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
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#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
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#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
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#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
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#define CBR_RG_SX_CHP_IOST_POL_SFT 18
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#define CBR_RG_SX_CHP_IOST_POL_HI 18
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#define CBR_RG_SX_CHP_IOST_POL_SZ 1
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#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
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#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
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#define CBR_RG_SX_CHP_IOST_SFT 19
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#define CBR_RG_SX_CHP_IOST_HI 21
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#define CBR_RG_SX_CHP_IOST_SZ 3
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#define CBR_RG_SX_PFDSEL_MSK 0x00400000
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#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
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#define CBR_RG_SX_PFDSEL_SFT 22
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#define CBR_RG_SX_PFDSEL_HI 22
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#define CBR_RG_SX_PFDSEL_SZ 1
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#define CBR_RG_SX_PFD_SET_MSK 0x00800000
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#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
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#define CBR_RG_SX_PFD_SET_SFT 23
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#define CBR_RG_SX_PFD_SET_HI 23
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#define CBR_RG_SX_PFD_SET_SZ 1
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#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
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#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
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#define CBR_RG_SX_PFD_SET1_SFT 24
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#define CBR_RG_SX_PFD_SET1_HI 24
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#define CBR_RG_SX_PFD_SET1_SZ 1
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#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
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#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
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#define CBR_RG_SX_PFD_SET2_SFT 25
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#define CBR_RG_SX_PFD_SET2_HI 25
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#define CBR_RG_SX_PFD_SET2_SZ 1
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#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
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#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
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#define CBR_RG_SX_VBNCAS_SEL_SFT 26
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#define CBR_RG_SX_VBNCAS_SEL_HI 26
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#define CBR_RG_SX_VBNCAS_SEL_SZ 1
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#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
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#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
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#define CBR_RG_SX_PFD_RST_H_SFT 27
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#define CBR_RG_SX_PFD_RST_H_HI 27
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#define CBR_RG_SX_PFD_RST_H_SZ 1
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#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
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#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
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#define CBR_RG_SX_PFD_TRUP_SFT 28
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#define CBR_RG_SX_PFD_TRUP_HI 28
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#define CBR_RG_SX_PFD_TRUP_SZ 1
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#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
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#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
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#define CBR_RG_SX_PFD_TRDN_SFT 29
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#define CBR_RG_SX_PFD_TRDN_HI 29
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#define CBR_RG_SX_PFD_TRDN_SZ 1
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#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
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#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
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#define CBR_RG_SX_PFD_TRSEL_SFT 30
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#define CBR_RG_SX_PFD_TRSEL_HI 30
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#define CBR_RG_SX_PFD_TRSEL_SZ 1
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#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
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#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
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#define CBR_RG_SX_VCOBA_R_SFT 0
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#define CBR_RG_SX_VCOBA_R_HI 2
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#define CBR_RG_SX_VCOBA_R_SZ 3
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#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
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#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
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#define CBR_RG_SX_VCORSEL_SFT 3
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#define CBR_RG_SX_VCORSEL_HI 7
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#define CBR_RG_SX_VCORSEL_SZ 5
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#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
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#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
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#define CBR_RG_SX_VCOCUSEL_SFT 8
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#define CBR_RG_SX_VCOCUSEL_HI 11
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#define CBR_RG_SX_VCOCUSEL_SZ 4
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#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
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#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
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#define CBR_RG_SX_RXBFSEL_SFT 12
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#define CBR_RG_SX_RXBFSEL_HI 15
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#define CBR_RG_SX_RXBFSEL_SZ 4
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#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
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#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
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#define CBR_RG_SX_TXBFSEL_SFT 16
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#define CBR_RG_SX_TXBFSEL_HI 19
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#define CBR_RG_SX_TXBFSEL_SZ 4
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#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
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#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
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#define CBR_RG_SX_VCOBFSEL_SFT 20
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#define CBR_RG_SX_VCOBFSEL_HI 23
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#define CBR_RG_SX_VCOBFSEL_SZ 4
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#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
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#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
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#define CBR_RG_SX_DIVBFSEL_SFT 24
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#define CBR_RG_SX_DIVBFSEL_HI 27
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#define CBR_RG_SX_DIVBFSEL_SZ 4
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#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
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#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
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#define CBR_RG_SX_GNDR_SEL_SFT 28
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#define CBR_RG_SX_GNDR_SEL_HI 31
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#define CBR_RG_SX_GNDR_SEL_SZ 4
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#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
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#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
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#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
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#define CBR_RG_SX_DITHER_WEIGHT_HI 1
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#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
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#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
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#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
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#define CBR_RG_SX_MOD_ERRCMP_SFT 2
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#define CBR_RG_SX_MOD_ERRCMP_HI 3
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#define CBR_RG_SX_MOD_ERRCMP_SZ 2
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#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
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#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
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#define CBR_RG_SX_MOD_ORDER_SFT 4
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#define CBR_RG_SX_MOD_ORDER_HI 5
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#define CBR_RG_SX_MOD_ORDER_SZ 2
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#define CBR_RG_SX_SDM_D1_MSK 0x00000040
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#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
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#define CBR_RG_SX_SDM_D1_SFT 6
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#define CBR_RG_SX_SDM_D1_HI 6
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#define CBR_RG_SX_SDM_D1_SZ 1
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#define CBR_RG_SX_SDM_D2_MSK 0x00000080
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#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
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#define CBR_RG_SX_SDM_D2_SFT 7
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#define CBR_RG_SX_SDM_D2_HI 7
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#define CBR_RG_SX_SDM_D2_SZ 1
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#define CBR_RG_SDM_PASS_MSK 0x00000100
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#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
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#define CBR_RG_SDM_PASS_SFT 8
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#define CBR_RG_SDM_PASS_HI 8
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#define CBR_RG_SDM_PASS_SZ 1
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#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
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#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
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#define CBR_RG_SX_RST_H_DIV_SFT 9
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#define CBR_RG_SX_RST_H_DIV_HI 9
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#define CBR_RG_SX_RST_H_DIV_SZ 1
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#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
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#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
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#define CBR_RG_SX_SDM_EDGE_SFT 10
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#define CBR_RG_SX_SDM_EDGE_HI 10
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#define CBR_RG_SX_SDM_EDGE_SZ 1
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#define CBR_RG_SX_XO_GM_MSK 0x00001800
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#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
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#define CBR_RG_SX_XO_GM_SFT 11
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#define CBR_RG_SX_XO_GM_HI 12
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#define CBR_RG_SX_XO_GM_SZ 2
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#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
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#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
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#define CBR_RG_SX_REFBYTWO_SFT 13
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#define CBR_RG_SX_REFBYTWO_HI 13
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#define CBR_RG_SX_REFBYTWO_SZ 1
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#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
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#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
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#define CBR_RG_SX_XO_SWCAP_SFT 14
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#define CBR_RG_SX_XO_SWCAP_HI 17
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#define CBR_RG_SX_XO_SWCAP_SZ 4
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#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
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#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
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#define CBR_RG_SX_SDMLUT_INV_SFT 18
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#define CBR_RG_SX_SDMLUT_INV_HI 18
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#define CBR_RG_SX_SDMLUT_INV_SZ 1
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#define CBR_RG_SX_LCKEN_MSK 0x00080000
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#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
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#define CBR_RG_SX_LCKEN_SFT 19
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#define CBR_RG_SX_LCKEN_HI 19
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#define CBR_RG_SX_LCKEN_SZ 1
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#define CBR_RG_SX_PREVDD_MSK 0x00f00000
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#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
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#define CBR_RG_SX_PREVDD_SFT 20
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#define CBR_RG_SX_PREVDD_HI 23
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#define CBR_RG_SX_PREVDD_SZ 4
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#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
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#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
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#define CBR_RG_SX_PSCONTERVDD_SFT 24
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#define CBR_RG_SX_PSCONTERVDD_HI 27
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#define CBR_RG_SX_PSCONTERVDD_SZ 4
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#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
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#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
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#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
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#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
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#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
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#define CBR_RG_SX_MODDB_MSK 0x40000000
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#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
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#define CBR_RG_SX_MODDB_SFT 30
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#define CBR_RG_SX_MODDB_HI 30
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#define CBR_RG_SX_MODDB_SZ 1
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#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
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#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
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#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
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#define CBR_RG_SX_CV_CURVE_SEL_HI 1
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#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
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#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
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#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
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#define CBR_RG_SX_SEL_DELAY_SFT 2
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#define CBR_RG_SX_SEL_DELAY_HI 6
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#define CBR_RG_SX_SEL_DELAY_SZ 5
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#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
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#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
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#define CBR_RG_SX_REF_CYCLE_SFT 7
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#define CBR_RG_SX_REF_CYCLE_HI 10
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#define CBR_RG_SX_REF_CYCLE_SZ 4
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#define CBR_RG_SX_VCOBY16_MSK 0x00000800
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#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
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#define CBR_RG_SX_VCOBY16_SFT 11
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#define CBR_RG_SX_VCOBY16_HI 11
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#define CBR_RG_SX_VCOBY16_SZ 1
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#define CBR_RG_SX_VCOBY32_MSK 0x00001000
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#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
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#define CBR_RG_SX_VCOBY32_SFT 12
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#define CBR_RG_SX_VCOBY32_HI 12
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#define CBR_RG_SX_VCOBY32_SZ 1
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#define CBR_RG_SX_PH_MSK 0x00002000
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#define CBR_RG_SX_PH_I_MSK 0xffffdfff
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#define CBR_RG_SX_PH_SFT 13
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#define CBR_RG_SX_PH_HI 13
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#define CBR_RG_SX_PH_SZ 1
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#define CBR_RG_SX_PL_MSK 0x00004000
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#define CBR_RG_SX_PL_I_MSK 0xffffbfff
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#define CBR_RG_SX_PL_SFT 14
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#define CBR_RG_SX_PL_HI 14
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#define CBR_RG_SX_PL_SZ 1
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#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
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#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
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#define CBR_RG_SX_VT_MON_MODE_SFT 0
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#define CBR_RG_SX_VT_MON_MODE_HI 0
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#define CBR_RG_SX_VT_MON_MODE_SZ 1
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#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
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#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
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#define CBR_RG_SX_VT_TH_HI_SFT 1
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#define CBR_RG_SX_VT_TH_HI_HI 2
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#define CBR_RG_SX_VT_TH_HI_SZ 2
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#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
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#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
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#define CBR_RG_SX_VT_TH_LO_SFT 3
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#define CBR_RG_SX_VT_TH_LO_HI 4
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#define CBR_RG_SX_VT_TH_LO_SZ 2
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#define CBR_RG_SX_VT_SET_MSK 0x00000020
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#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
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#define CBR_RG_SX_VT_SET_SFT 5
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#define CBR_RG_SX_VT_SET_HI 5
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#define CBR_RG_SX_VT_SET_SZ 1
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#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
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#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
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#define CBR_RG_SX_VT_MON_TMR_SFT 6
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#define CBR_RG_SX_VT_MON_TMR_HI 14
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#define CBR_RG_SX_VT_MON_TMR_SZ 9
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#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
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#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
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#define CBR_RG_IDEAL_CYCLE_SFT 15
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#define CBR_RG_IDEAL_CYCLE_HI 27
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#define CBR_RG_IDEAL_CYCLE_SZ 13
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#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
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#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
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#define CBR_RG_EN_DP_VT_MON_SFT 0
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#define CBR_RG_EN_DP_VT_MON_HI 0
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#define CBR_RG_EN_DP_VT_MON_SZ 1
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#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
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#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
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#define CBR_RG_DP_VT_TH_HI_SFT 1
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#define CBR_RG_DP_VT_TH_HI_HI 2
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#define CBR_RG_DP_VT_TH_HI_SZ 2
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#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
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#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
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#define CBR_RG_DP_VT_TH_LO_SFT 3
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#define CBR_RG_DP_VT_TH_LO_HI 4
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#define CBR_RG_DP_VT_TH_LO_SZ 2
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#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
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#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
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#define CBR_RG_DP_VT_MON_TMR_SFT 5
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#define CBR_RG_DP_VT_MON_TMR_HI 13
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#define CBR_RG_DP_VT_MON_TMR_SZ 9
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#define CBR_RG_DP_CK320BY2_MSK 0x00004000
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#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
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#define CBR_RG_DP_CK320BY2_SFT 14
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#define CBR_RG_DP_CK320BY2_HI 14
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#define CBR_RG_DP_CK320BY2_SZ 1
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#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
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#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
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#define CBR_RG_SX_DELCTRL_SFT 15
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#define CBR_RG_SX_DELCTRL_HI 20
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#define CBR_RG_SX_DELCTRL_SZ 6
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#define CBR_RG_DP_OD_TEST_MSK 0x00200000
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#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
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#define CBR_RG_DP_OD_TEST_SFT 21
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#define CBR_RG_DP_OD_TEST_HI 21
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#define CBR_RG_DP_OD_TEST_SZ 1
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#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
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#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
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#define CBR_RG_DP_BBPLL_BP_SFT 0
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#define CBR_RG_DP_BBPLL_BP_HI 0
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#define CBR_RG_DP_BBPLL_BP_SZ 1
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#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
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#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
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#define CBR_RG_DP_BBPLL_ICP_SFT 1
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#define CBR_RG_DP_BBPLL_ICP_HI 2
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#define CBR_RG_DP_BBPLL_ICP_SZ 2
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#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
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#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
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#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
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#define CBR_RG_DP_BBPLL_IDUAL_HI 4
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#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
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#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
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#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
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#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
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#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
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#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
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#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
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#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
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#define CBR_RG_DP_BBPLL_PD_SFT 9
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#define CBR_RG_DP_BBPLL_PD_HI 9
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#define CBR_RG_DP_BBPLL_PD_SZ 1
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#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
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#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
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#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
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#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
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#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
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#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
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#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
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#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
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#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
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#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
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#define CBR_RG_DP_RP_MSK 0x00038000
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#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
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#define CBR_RG_DP_RP_SFT 15
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#define CBR_RG_DP_RP_HI 17
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#define CBR_RG_DP_RP_SZ 3
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#define CBR_RG_DP_RHP_MSK 0x000c0000
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#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
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#define CBR_RG_DP_RHP_SFT 18
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#define CBR_RG_DP_RHP_HI 19
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#define CBR_RG_DP_RHP_SZ 2
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#define CBR_RG_DP_DR3_MSK 0x00700000
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#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
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#define CBR_RG_DP_DR3_SFT 20
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#define CBR_RG_DP_DR3_HI 22
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#define CBR_RG_DP_DR3_SZ 3
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#define CBR_RG_DP_DCP_MSK 0x07800000
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#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
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#define CBR_RG_DP_DCP_SFT 23
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#define CBR_RG_DP_DCP_HI 26
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#define CBR_RG_DP_DCP_SZ 4
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#define CBR_RG_DP_DCS_MSK 0x78000000
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#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
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#define CBR_RG_DP_DCS_SFT 27
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#define CBR_RG_DP_DCS_HI 30
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#define CBR_RG_DP_DCS_SZ 4
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#define CBR_RG_DP_FBDIV_MSK 0x00000fff
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#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
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#define CBR_RG_DP_FBDIV_SFT 0
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#define CBR_RG_DP_FBDIV_HI 11
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#define CBR_RG_DP_FBDIV_SZ 12
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#define CBR_RG_DP_FODIV_MSK 0x003ff000
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#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
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#define CBR_RG_DP_FODIV_SFT 12
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#define CBR_RG_DP_FODIV_HI 21
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#define CBR_RG_DP_FODIV_SZ 10
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#define CBR_RG_DP_REFDIV_MSK 0xffc00000
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#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
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#define CBR_RG_DP_REFDIV_SFT 22
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#define CBR_RG_DP_REFDIV_HI 31
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#define CBR_RG_DP_REFDIV_SZ 10
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#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG15_SFT 0
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#define CBR_RG_IDACAI_PGAG15_HI 5
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#define CBR_RG_IDACAI_PGAG15_SZ 6
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#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG15_SFT 6
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#define CBR_RG_IDACAQ_PGAG15_HI 11
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#define CBR_RG_IDACAQ_PGAG15_SZ 6
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#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG14_SFT 12
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#define CBR_RG_IDACAI_PGAG14_HI 17
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#define CBR_RG_IDACAI_PGAG14_SZ 6
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#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG14_SFT 18
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#define CBR_RG_IDACAQ_PGAG14_HI 23
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#define CBR_RG_IDACAQ_PGAG14_SZ 6
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#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG13_SFT 0
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#define CBR_RG_IDACAI_PGAG13_HI 5
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#define CBR_RG_IDACAI_PGAG13_SZ 6
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#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG13_SFT 6
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#define CBR_RG_IDACAQ_PGAG13_HI 11
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#define CBR_RG_IDACAQ_PGAG13_SZ 6
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#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG12_SFT 12
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#define CBR_RG_IDACAI_PGAG12_HI 17
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#define CBR_RG_IDACAI_PGAG12_SZ 6
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#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG12_SFT 18
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#define CBR_RG_IDACAQ_PGAG12_HI 23
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#define CBR_RG_IDACAQ_PGAG12_SZ 6
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#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG11_SFT 0
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#define CBR_RG_IDACAI_PGAG11_HI 5
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#define CBR_RG_IDACAI_PGAG11_SZ 6
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#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG11_SFT 6
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#define CBR_RG_IDACAQ_PGAG11_HI 11
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#define CBR_RG_IDACAQ_PGAG11_SZ 6
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#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG10_SFT 12
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#define CBR_RG_IDACAI_PGAG10_HI 17
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#define CBR_RG_IDACAI_PGAG10_SZ 6
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#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG10_SFT 18
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#define CBR_RG_IDACAQ_PGAG10_HI 23
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#define CBR_RG_IDACAQ_PGAG10_SZ 6
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#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG9_SFT 0
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#define CBR_RG_IDACAI_PGAG9_HI 5
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#define CBR_RG_IDACAI_PGAG9_SZ 6
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#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG9_SFT 6
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#define CBR_RG_IDACAQ_PGAG9_HI 11
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#define CBR_RG_IDACAQ_PGAG9_SZ 6
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#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG8_SFT 12
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#define CBR_RG_IDACAI_PGAG8_HI 17
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#define CBR_RG_IDACAI_PGAG8_SZ 6
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#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG8_SFT 18
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#define CBR_RG_IDACAQ_PGAG8_HI 23
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#define CBR_RG_IDACAQ_PGAG8_SZ 6
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#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG7_SFT 0
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#define CBR_RG_IDACAI_PGAG7_HI 5
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#define CBR_RG_IDACAI_PGAG7_SZ 6
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#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG7_SFT 6
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#define CBR_RG_IDACAQ_PGAG7_HI 11
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#define CBR_RG_IDACAQ_PGAG7_SZ 6
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#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG6_SFT 12
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#define CBR_RG_IDACAI_PGAG6_HI 17
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#define CBR_RG_IDACAI_PGAG6_SZ 6
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#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG6_SFT 18
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#define CBR_RG_IDACAQ_PGAG6_HI 23
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#define CBR_RG_IDACAQ_PGAG6_SZ 6
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#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG5_SFT 0
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#define CBR_RG_IDACAI_PGAG5_HI 5
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#define CBR_RG_IDACAI_PGAG5_SZ 6
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#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG5_SFT 6
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#define CBR_RG_IDACAQ_PGAG5_HI 11
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#define CBR_RG_IDACAQ_PGAG5_SZ 6
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#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG4_SFT 12
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#define CBR_RG_IDACAI_PGAG4_HI 17
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#define CBR_RG_IDACAI_PGAG4_SZ 6
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#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG4_SFT 18
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#define CBR_RG_IDACAQ_PGAG4_HI 23
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#define CBR_RG_IDACAQ_PGAG4_SZ 6
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#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG3_SFT 0
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#define CBR_RG_IDACAI_PGAG3_HI 5
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#define CBR_RG_IDACAI_PGAG3_SZ 6
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#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG3_SFT 6
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#define CBR_RG_IDACAQ_PGAG3_HI 11
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#define CBR_RG_IDACAQ_PGAG3_SZ 6
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#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG2_SFT 12
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#define CBR_RG_IDACAI_PGAG2_HI 17
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#define CBR_RG_IDACAI_PGAG2_SZ 6
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#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG2_SFT 18
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#define CBR_RG_IDACAQ_PGAG2_HI 23
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#define CBR_RG_IDACAQ_PGAG2_SZ 6
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#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
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#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
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#define CBR_RG_IDACAI_PGAG1_SFT 0
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#define CBR_RG_IDACAI_PGAG1_HI 5
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#define CBR_RG_IDACAI_PGAG1_SZ 6
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#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
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#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
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#define CBR_RG_IDACAQ_PGAG1_SFT 6
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#define CBR_RG_IDACAQ_PGAG1_HI 11
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#define CBR_RG_IDACAQ_PGAG1_SZ 6
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#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
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#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
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#define CBR_RG_IDACAI_PGAG0_SFT 12
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#define CBR_RG_IDACAI_PGAG0_HI 17
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#define CBR_RG_IDACAI_PGAG0_SZ 6
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#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
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#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
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#define CBR_RG_IDACAQ_PGAG0_SFT 18
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#define CBR_RG_IDACAQ_PGAG0_HI 23
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#define CBR_RG_IDACAQ_PGAG0_SZ 6
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#define CBR_RG_EN_RCAL_MSK 0x00000001
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#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
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#define CBR_RG_EN_RCAL_SFT 0
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#define CBR_RG_EN_RCAL_HI 0
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#define CBR_RG_EN_RCAL_SZ 1
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#define CBR_RG_RCAL_SPD_MSK 0x00000002
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#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
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#define CBR_RG_RCAL_SPD_SFT 1
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#define CBR_RG_RCAL_SPD_HI 1
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#define CBR_RG_RCAL_SPD_SZ 1
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#define CBR_RG_RCAL_TMR_MSK 0x000001fc
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#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
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#define CBR_RG_RCAL_TMR_SFT 2
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#define CBR_RG_RCAL_TMR_HI 8
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#define CBR_RG_RCAL_TMR_SZ 7
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#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
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#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
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#define CBR_RG_RCAL_CODE_CWR_SFT 9
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#define CBR_RG_RCAL_CODE_CWR_HI 9
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#define CBR_RG_RCAL_CODE_CWR_SZ 1
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#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
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#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
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#define CBR_RG_RCAL_CODE_CWD_SFT 10
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#define CBR_RG_RCAL_CODE_CWD_HI 14
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#define CBR_RG_RCAL_CODE_CWD_SZ 5
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#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
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#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
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#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
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#define CBR_RG_SX_SUB_SEL_CWR_HI 0
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#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
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#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
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#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
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#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
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#define CBR_RG_SX_SUB_SEL_CWD_HI 7
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#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
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#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
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#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
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#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
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#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
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#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
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#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
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#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
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#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
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#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
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#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
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#define CBR_RCAL_RDY_MSK 0x00000001
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#define CBR_RCAL_RDY_I_MSK 0xfffffffe
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#define CBR_RCAL_RDY_SFT 0
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#define CBR_RCAL_RDY_HI 0
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#define CBR_RCAL_RDY_SZ 1
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#define CBR_DA_LCK_RDY_MSK 0x00000002
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#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
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#define CBR_DA_LCK_RDY_SFT 1
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#define CBR_DA_LCK_RDY_HI 1
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#define CBR_DA_LCK_RDY_SZ 1
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#define CBR_VT_MON_RDY_MSK 0x00000004
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#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
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#define CBR_VT_MON_RDY_SFT 2
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#define CBR_VT_MON_RDY_HI 2
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#define CBR_VT_MON_RDY_SZ 1
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#define CBR_DP_VT_MON_RDY_MSK 0x00000008
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#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
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#define CBR_DP_VT_MON_RDY_SFT 3
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#define CBR_DP_VT_MON_RDY_HI 3
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#define CBR_DP_VT_MON_RDY_SZ 1
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#define CBR_CH_RDY_MSK 0x00000010
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#define CBR_CH_RDY_I_MSK 0xffffffef
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#define CBR_CH_RDY_SFT 4
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#define CBR_CH_RDY_HI 4
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#define CBR_CH_RDY_SZ 1
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#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
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#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
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#define CBR_DA_R_CODE_LUT_SFT 6
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#define CBR_DA_R_CODE_LUT_HI 10
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#define CBR_DA_R_CODE_LUT_SZ 5
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#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
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#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
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#define CBR_AD_SX_VT_MON_Q_SFT 11
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#define CBR_AD_SX_VT_MON_Q_HI 12
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#define CBR_AD_SX_VT_MON_Q_SZ 2
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#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
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#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
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#define CBR_AD_DP_VT_MON_Q_SFT 13
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#define CBR_AD_DP_VT_MON_Q_HI 14
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#define CBR_AD_DP_VT_MON_Q_SZ 2
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#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
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#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
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#define CBR_DA_R_CAL_CODE_SFT 0
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#define CBR_DA_R_CAL_CODE_HI 4
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#define CBR_DA_R_CAL_CODE_SZ 5
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#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
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#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
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#define CBR_DA_SX_SUB_SEL_SFT 5
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#define CBR_DA_SX_SUB_SEL_HI 11
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#define CBR_DA_SX_SUB_SEL_SZ 7
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#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
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#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
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#define CBR_DA_DP_BBPLL_BS_SFT 12
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#define CBR_DA_DP_BBPLL_BS_HI 17
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#define CBR_DA_DP_BBPLL_BS_SZ 6
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#define CBR_TX_EN_MSK 0x00000001
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#define CBR_TX_EN_I_MSK 0xfffffffe
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#define CBR_TX_EN_SFT 0
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#define CBR_TX_EN_HI 0
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#define CBR_TX_EN_SZ 1
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#define CBR_TX_CNT_RST_MSK 0x00000002
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#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
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#define CBR_TX_CNT_RST_SFT 1
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#define CBR_TX_CNT_RST_HI 1
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#define CBR_TX_CNT_RST_SZ 1
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#define CBR_IFS_TIME_MSK 0x000000fc
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#define CBR_IFS_TIME_I_MSK 0xffffff03
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#define CBR_IFS_TIME_SFT 2
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#define CBR_IFS_TIME_HI 7
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#define CBR_IFS_TIME_SZ 6
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#define CBR_LENGTH_TARGET_MSK 0x000fff00
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#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
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#define CBR_LENGTH_TARGET_SFT 8
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#define CBR_LENGTH_TARGET_HI 19
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#define CBR_LENGTH_TARGET_SZ 12
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#define CBR_TX_CNT_TARGET_MSK 0xff000000
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#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
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#define CBR_TX_CNT_TARGET_SFT 24
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#define CBR_TX_CNT_TARGET_HI 31
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#define CBR_TX_CNT_TARGET_SZ 8
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#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
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#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
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#define CBR_TC_CNT_TARGET_SFT 0
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#define CBR_TC_CNT_TARGET_HI 23
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#define CBR_TC_CNT_TARGET_SZ 24
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#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
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#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
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#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
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#define CBR_PLCP_PSDU_DATA_MEM_HI 7
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#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
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#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
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#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
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#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
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#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
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#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
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#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
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#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
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#define CBR_PLCP_BYTE_LENGTH_SFT 9
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#define CBR_PLCP_BYTE_LENGTH_HI 20
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#define CBR_PLCP_BYTE_LENGTH_SZ 12
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#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
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#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
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#define CBR_PLCP_PSDU_RATE_SFT 21
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#define CBR_PLCP_PSDU_RATE_HI 22
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#define CBR_PLCP_PSDU_RATE_SZ 2
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#define CBR_TAIL_TIME_MSK 0x1f800000
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#define CBR_TAIL_TIME_I_MSK 0xe07fffff
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#define CBR_TAIL_TIME_SFT 23
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#define CBR_TAIL_TIME_HI 28
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#define CBR_TAIL_TIME_SZ 6
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#define CBR_RG_O_PAD_PD_MSK 0x00000001
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#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
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#define CBR_RG_O_PAD_PD_SFT 0
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#define CBR_RG_O_PAD_PD_HI 0
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#define CBR_RG_O_PAD_PD_SZ 1
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#define CBR_RG_I_PAD_PD_MSK 0x00000002
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#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
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#define CBR_RG_I_PAD_PD_SFT 1
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#define CBR_RG_I_PAD_PD_HI 1
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#define CBR_RG_I_PAD_PD_SZ 1
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#define CBR_SEL_ADCKP_INV_MSK 0x00000004
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#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
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#define CBR_SEL_ADCKP_INV_SFT 2
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#define CBR_SEL_ADCKP_INV_HI 2
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#define CBR_SEL_ADCKP_INV_SZ 1
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#define CBR_RG_PAD_DS_MSK 0x00000008
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#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
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#define CBR_RG_PAD_DS_SFT 3
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#define CBR_RG_PAD_DS_HI 3
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#define CBR_RG_PAD_DS_SZ 1
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#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
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#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
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#define CBR_SEL_ADCKP_MUX_SFT 4
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#define CBR_SEL_ADCKP_MUX_HI 4
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#define CBR_SEL_ADCKP_MUX_SZ 1
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#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
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#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
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#define CBR_RG_PAD_DS_CLK_SFT 5
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#define CBR_RG_PAD_DS_CLK_HI 5
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#define CBR_RG_PAD_DS_CLK_SZ 1
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#define CBR_INTP_SEL_MSK 0x00000200
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#define CBR_INTP_SEL_I_MSK 0xfffffdff
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#define CBR_INTP_SEL_SFT 9
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#define CBR_INTP_SEL_HI 9
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#define CBR_INTP_SEL_SZ 1
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#define CBR_IQ_SWP_MSK 0x00000400
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#define CBR_IQ_SWP_I_MSK 0xfffffbff
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#define CBR_IQ_SWP_SFT 10
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#define CBR_IQ_SWP_HI 10
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#define CBR_IQ_SWP_SZ 1
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#define CBR_RG_EN_EXT_DA_MSK 0x00000800
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#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
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#define CBR_RG_EN_EXT_DA_SFT 11
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#define CBR_RG_EN_EXT_DA_HI 11
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#define CBR_RG_EN_EXT_DA_SZ 1
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#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
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#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
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#define CBR_RG_DIS_DA_OFFSET_SFT 12
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#define CBR_RG_DIS_DA_OFFSET_HI 12
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#define CBR_RG_DIS_DA_OFFSET_SZ 1
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#define CBR_DBG_SEL_MSK 0x000f0000
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#define CBR_DBG_SEL_I_MSK 0xfff0ffff
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#define CBR_DBG_SEL_SFT 16
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#define CBR_DBG_SEL_HI 19
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#define CBR_DBG_SEL_SZ 4
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#define CBR_DBG_EN_MSK 0x00100000
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#define CBR_DBG_EN_I_MSK 0xffefffff
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#define CBR_DBG_EN_SFT 20
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#define CBR_DBG_EN_HI 20
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#define CBR_DBG_EN_SZ 1
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#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
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#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
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#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
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#define CBR_RG_PKT_GEN_TX_CNT_HI 31
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#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
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#define CBR_TP_SEL_MSK 0x0000001f
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#define CBR_TP_SEL_I_MSK 0xffffffe0
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#define CBR_TP_SEL_SFT 0
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#define CBR_TP_SEL_HI 4
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#define CBR_TP_SEL_SZ 5
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#define CBR_IDEAL_IQ_EN_MSK 0x00000020
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#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
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#define CBR_IDEAL_IQ_EN_SFT 5
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#define CBR_IDEAL_IQ_EN_HI 5
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#define CBR_IDEAL_IQ_EN_SZ 1
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#define CBR_DATA_OUT_SEL_MSK 0x000001c0
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#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
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#define CBR_DATA_OUT_SEL_SFT 6
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#define CBR_DATA_OUT_SEL_HI 8
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#define CBR_DATA_OUT_SEL_SZ 3
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#define CBR_TWO_TONE_EN_MSK 0x00000200
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#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
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#define CBR_TWO_TONE_EN_SFT 9
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#define CBR_TWO_TONE_EN_HI 9
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#define CBR_TWO_TONE_EN_SZ 1
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#define CBR_FREQ_SEL_MSK 0x00ff0000
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#define CBR_FREQ_SEL_I_MSK 0xff00ffff
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#define CBR_FREQ_SEL_SFT 16
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#define CBR_FREQ_SEL_HI 23
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#define CBR_FREQ_SEL_SZ 8
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#define CBR_IQ_SCALE_MSK 0xff000000
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#define CBR_IQ_SCALE_I_MSK 0x00ffffff
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#define CBR_IQ_SCALE_SFT 24
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#define CBR_IQ_SCALE_HI 31
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#define CBR_IQ_SCALE_SZ 8
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#define CPU_QUE_POP_MSK 0x00000001
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#define CPU_QUE_POP_I_MSK 0xfffffffe
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#define CPU_QUE_POP_SFT 0
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#define CPU_QUE_POP_HI 0
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#define CPU_QUE_POP_SZ 1
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#define CPU_INT_MSK 0x00000004
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#define CPU_INT_I_MSK 0xfffffffb
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#define CPU_INT_SFT 2
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#define CPU_INT_HI 2
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#define CPU_INT_SZ 1
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#define CPU_ID_TB0_MSK 0xffffffff
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#define CPU_ID_TB0_I_MSK 0x00000000
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#define CPU_ID_TB0_SFT 0
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#define CPU_ID_TB0_HI 31
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#define CPU_ID_TB0_SZ 32
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#define CPU_ID_TB1_MSK 0xffffffff
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#define CPU_ID_TB1_I_MSK 0x00000000
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#define CPU_ID_TB1_SFT 0
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#define CPU_ID_TB1_HI 31
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#define CPU_ID_TB1_SZ 32
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#define HW_PKTID_MSK 0x000007ff
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#define HW_PKTID_I_MSK 0xfffff800
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#define HW_PKTID_SFT 0
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#define HW_PKTID_HI 10
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#define HW_PKTID_SZ 11
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#define CH0_INT_ADDR_MSK 0xffffffff
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#define CH0_INT_ADDR_I_MSK 0x00000000
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#define CH0_INT_ADDR_SFT 0
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#define CH0_INT_ADDR_HI 31
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#define CH0_INT_ADDR_SZ 32
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#define PRI_HW_PKTID_MSK 0x000007ff
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#define PRI_HW_PKTID_I_MSK 0xfffff800
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#define PRI_HW_PKTID_SFT 0
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#define PRI_HW_PKTID_HI 10
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#define PRI_HW_PKTID_SZ 11
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#define CH0_FULL_MSK 0x00000001
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#define CH0_FULL_I_MSK 0xfffffffe
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#define CH0_FULL_SFT 0
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#define CH0_FULL_HI 0
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#define CH0_FULL_SZ 1
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#define FF0_EMPTY_MSK 0x00000002
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#define FF0_EMPTY_I_MSK 0xfffffffd
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#define FF0_EMPTY_SFT 1
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#define FF0_EMPTY_HI 1
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#define FF0_EMPTY_SZ 1
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#define RLS_BUSY_MSK 0x00000200
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#define RLS_BUSY_I_MSK 0xfffffdff
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#define RLS_BUSY_SFT 9
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#define RLS_BUSY_HI 9
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#define RLS_BUSY_SZ 1
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#define RLS_COUNT_CLR_MSK 0x00000400
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#define RLS_COUNT_CLR_I_MSK 0xfffffbff
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#define RLS_COUNT_CLR_SFT 10
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#define RLS_COUNT_CLR_HI 10
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#define RLS_COUNT_CLR_SZ 1
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#define RTN_COUNT_CLR_MSK 0x00000800
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#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
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#define RTN_COUNT_CLR_SFT 11
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#define RTN_COUNT_CLR_HI 11
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#define RTN_COUNT_CLR_SZ 1
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#define RLS_COUNT_MSK 0x00ff0000
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#define RLS_COUNT_I_MSK 0xff00ffff
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#define RLS_COUNT_SFT 16
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#define RLS_COUNT_HI 23
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#define RLS_COUNT_SZ 8
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#define RTN_COUNT_MSK 0xff000000
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#define RTN_COUNT_I_MSK 0x00ffffff
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#define RTN_COUNT_SFT 24
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#define RTN_COUNT_HI 31
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#define RTN_COUNT_SZ 8
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#define FF0_CNT_MSK 0x0000001f
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#define FF0_CNT_I_MSK 0xffffffe0
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#define FF0_CNT_SFT 0
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#define FF0_CNT_HI 4
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#define FF0_CNT_SZ 5
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#define FF1_CNT_MSK 0x000001e0
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#define FF1_CNT_I_MSK 0xfffffe1f
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#define FF1_CNT_SFT 5
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#define FF1_CNT_HI 8
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#define FF1_CNT_SZ 4
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#define FF3_CNT_MSK 0x00003800
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#define FF3_CNT_I_MSK 0xffffc7ff
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#define FF3_CNT_SFT 11
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#define FF3_CNT_HI 13
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#define FF3_CNT_SZ 3
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#define FF5_CNT_MSK 0x000e0000
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#define FF5_CNT_I_MSK 0xfff1ffff
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#define FF5_CNT_SFT 17
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#define FF5_CNT_HI 19
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#define FF5_CNT_SZ 3
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#define FF6_CNT_MSK 0x00700000
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#define FF6_CNT_I_MSK 0xff8fffff
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#define FF6_CNT_SFT 20
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#define FF6_CNT_HI 22
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#define FF6_CNT_SZ 3
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#define FF7_CNT_MSK 0x03800000
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#define FF7_CNT_I_MSK 0xfc7fffff
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#define FF7_CNT_SFT 23
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#define FF7_CNT_HI 25
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#define FF7_CNT_SZ 3
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#define FF8_CNT_MSK 0x1c000000
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#define FF8_CNT_I_MSK 0xe3ffffff
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#define FF8_CNT_SFT 26
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#define FF8_CNT_HI 28
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#define FF8_CNT_SZ 3
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#define FF9_CNT_MSK 0xe0000000
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#define FF9_CNT_I_MSK 0x1fffffff
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#define FF9_CNT_SFT 29
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#define FF9_CNT_HI 31
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#define FF9_CNT_SZ 3
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#define FF10_CNT_MSK 0x00000007
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#define FF10_CNT_I_MSK 0xfffffff8
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#define FF10_CNT_SFT 0
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#define FF10_CNT_HI 2
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#define FF10_CNT_SZ 3
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#define FF11_CNT_MSK 0x00000038
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#define FF11_CNT_I_MSK 0xffffffc7
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#define FF11_CNT_SFT 3
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#define FF11_CNT_HI 5
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#define FF11_CNT_SZ 3
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#define FF12_CNT_MSK 0x000001c0
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#define FF12_CNT_I_MSK 0xfffffe3f
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#define FF12_CNT_SFT 6
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#define FF12_CNT_HI 8
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#define FF12_CNT_SZ 3
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#define FF13_CNT_MSK 0x00000600
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#define FF13_CNT_I_MSK 0xfffff9ff
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#define FF13_CNT_SFT 9
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#define FF13_CNT_HI 10
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#define FF13_CNT_SZ 2
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#define FF14_CNT_MSK 0x00001800
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#define FF14_CNT_I_MSK 0xffffe7ff
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#define FF14_CNT_SFT 11
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#define FF14_CNT_HI 12
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#define FF14_CNT_SZ 2
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#define FF15_CNT_MSK 0x00006000
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#define FF15_CNT_I_MSK 0xffff9fff
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#define FF15_CNT_SFT 13
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#define FF15_CNT_HI 14
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#define FF15_CNT_SZ 2
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#define FF4_CNT_MSK 0x000f8000
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#define FF4_CNT_I_MSK 0xfff07fff
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#define FF4_CNT_SFT 15
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#define FF4_CNT_HI 19
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#define FF4_CNT_SZ 5
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#define FF2_CNT_MSK 0x00700000
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#define FF2_CNT_I_MSK 0xff8fffff
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#define FF2_CNT_SFT 20
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#define FF2_CNT_HI 22
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#define FF2_CNT_SZ 3
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#define CH1_FULL_MSK 0x00000002
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#define CH1_FULL_I_MSK 0xfffffffd
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#define CH1_FULL_SFT 1
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#define CH1_FULL_HI 1
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#define CH1_FULL_SZ 1
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#define CH2_FULL_MSK 0x00000004
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#define CH2_FULL_I_MSK 0xfffffffb
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#define CH2_FULL_SFT 2
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#define CH2_FULL_HI 2
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#define CH2_FULL_SZ 1
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#define CH3_FULL_MSK 0x00000008
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#define CH3_FULL_I_MSK 0xfffffff7
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#define CH3_FULL_SFT 3
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#define CH3_FULL_HI 3
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#define CH3_FULL_SZ 1
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#define CH4_FULL_MSK 0x00000010
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#define CH4_FULL_I_MSK 0xffffffef
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#define CH4_FULL_SFT 4
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#define CH4_FULL_HI 4
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#define CH4_FULL_SZ 1
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#define CH5_FULL_MSK 0x00000020
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#define CH5_FULL_I_MSK 0xffffffdf
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#define CH5_FULL_SFT 5
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#define CH5_FULL_HI 5
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#define CH5_FULL_SZ 1
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#define CH6_FULL_MSK 0x00000040
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#define CH6_FULL_I_MSK 0xffffffbf
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#define CH6_FULL_SFT 6
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#define CH6_FULL_HI 6
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#define CH6_FULL_SZ 1
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#define CH7_FULL_MSK 0x00000080
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#define CH7_FULL_I_MSK 0xffffff7f
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#define CH7_FULL_SFT 7
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#define CH7_FULL_HI 7
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#define CH7_FULL_SZ 1
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#define CH8_FULL_MSK 0x00000100
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#define CH8_FULL_I_MSK 0xfffffeff
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#define CH8_FULL_SFT 8
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#define CH8_FULL_HI 8
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#define CH8_FULL_SZ 1
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#define CH9_FULL_MSK 0x00000200
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#define CH9_FULL_I_MSK 0xfffffdff
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#define CH9_FULL_SFT 9
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#define CH9_FULL_HI 9
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#define CH9_FULL_SZ 1
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#define CH10_FULL_MSK 0x00000400
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#define CH10_FULL_I_MSK 0xfffffbff
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#define CH10_FULL_SFT 10
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#define CH10_FULL_HI 10
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#define CH10_FULL_SZ 1
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#define CH11_FULL_MSK 0x00000800
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#define CH11_FULL_I_MSK 0xfffff7ff
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#define CH11_FULL_SFT 11
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#define CH11_FULL_HI 11
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#define CH11_FULL_SZ 1
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#define CH12_FULL_MSK 0x00001000
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#define CH12_FULL_I_MSK 0xffffefff
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#define CH12_FULL_SFT 12
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#define CH12_FULL_HI 12
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#define CH12_FULL_SZ 1
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#define CH13_FULL_MSK 0x00002000
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#define CH13_FULL_I_MSK 0xffffdfff
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#define CH13_FULL_SFT 13
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#define CH13_FULL_HI 13
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#define CH13_FULL_SZ 1
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#define CH14_FULL_MSK 0x00004000
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#define CH14_FULL_I_MSK 0xffffbfff
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#define CH14_FULL_SFT 14
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#define CH14_FULL_HI 14
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#define CH14_FULL_SZ 1
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#define CH15_FULL_MSK 0x00008000
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#define CH15_FULL_I_MSK 0xffff7fff
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#define CH15_FULL_SFT 15
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#define CH15_FULL_HI 15
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#define CH15_FULL_SZ 1
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#define HALT_CH0_MSK 0x00000001
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#define HALT_CH0_I_MSK 0xfffffffe
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#define HALT_CH0_SFT 0
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#define HALT_CH0_HI 0
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#define HALT_CH0_SZ 1
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#define HALT_CH1_MSK 0x00000002
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#define HALT_CH1_I_MSK 0xfffffffd
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#define HALT_CH1_SFT 1
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#define HALT_CH1_HI 1
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#define HALT_CH1_SZ 1
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#define HALT_CH2_MSK 0x00000004
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#define HALT_CH2_I_MSK 0xfffffffb
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#define HALT_CH2_SFT 2
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#define HALT_CH2_HI 2
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#define HALT_CH2_SZ 1
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#define HALT_CH3_MSK 0x00000008
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#define HALT_CH3_I_MSK 0xfffffff7
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#define HALT_CH3_SFT 3
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#define HALT_CH3_HI 3
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#define HALT_CH3_SZ 1
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#define HALT_CH4_MSK 0x00000010
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#define HALT_CH4_I_MSK 0xffffffef
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#define HALT_CH4_SFT 4
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#define HALT_CH4_HI 4
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#define HALT_CH4_SZ 1
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#define HALT_CH5_MSK 0x00000020
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#define HALT_CH5_I_MSK 0xffffffdf
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#define HALT_CH5_SFT 5
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#define HALT_CH5_HI 5
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#define HALT_CH5_SZ 1
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#define HALT_CH6_MSK 0x00000040
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#define HALT_CH6_I_MSK 0xffffffbf
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#define HALT_CH6_SFT 6
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#define HALT_CH6_HI 6
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#define HALT_CH6_SZ 1
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#define HALT_CH7_MSK 0x00000080
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#define HALT_CH7_I_MSK 0xffffff7f
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#define HALT_CH7_SFT 7
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#define HALT_CH7_HI 7
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#define HALT_CH7_SZ 1
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#define HALT_CH8_MSK 0x00000100
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#define HALT_CH8_I_MSK 0xfffffeff
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#define HALT_CH8_SFT 8
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#define HALT_CH8_HI 8
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#define HALT_CH8_SZ 1
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#define HALT_CH9_MSK 0x00000200
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#define HALT_CH9_I_MSK 0xfffffdff
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#define HALT_CH9_SFT 9
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#define HALT_CH9_HI 9
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#define HALT_CH9_SZ 1
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#define HALT_CH10_MSK 0x00000400
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#define HALT_CH10_I_MSK 0xfffffbff
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#define HALT_CH10_SFT 10
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#define HALT_CH10_HI 10
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#define HALT_CH10_SZ 1
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#define HALT_CH11_MSK 0x00000800
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#define HALT_CH11_I_MSK 0xfffff7ff
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#define HALT_CH11_SFT 11
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#define HALT_CH11_HI 11
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#define HALT_CH11_SZ 1
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#define HALT_CH12_MSK 0x00001000
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#define HALT_CH12_I_MSK 0xffffefff
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#define HALT_CH12_SFT 12
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#define HALT_CH12_HI 12
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#define HALT_CH12_SZ 1
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#define HALT_CH13_MSK 0x00002000
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#define HALT_CH13_I_MSK 0xffffdfff
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#define HALT_CH13_SFT 13
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#define HALT_CH13_HI 13
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#define HALT_CH13_SZ 1
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#define HALT_CH14_MSK 0x00004000
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#define HALT_CH14_I_MSK 0xffffbfff
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#define HALT_CH14_SFT 14
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#define HALT_CH14_HI 14
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#define HALT_CH14_SZ 1
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#define HALT_CH15_MSK 0x00008000
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#define HALT_CH15_I_MSK 0xffff7fff
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#define HALT_CH15_SFT 15
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#define HALT_CH15_HI 15
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#define HALT_CH15_SZ 1
|
#define STOP_MBOX_MSK 0x00010000
|
#define STOP_MBOX_I_MSK 0xfffeffff
|
#define STOP_MBOX_SFT 16
|
#define STOP_MBOX_HI 16
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#define STOP_MBOX_SZ 1
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#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
|
#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
|
#define MB_ERR_AUTO_HALT_EN_SFT 20
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#define MB_ERR_AUTO_HALT_EN_HI 20
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#define MB_ERR_AUTO_HALT_EN_SZ 1
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#define MB_EXCEPT_CLR_MSK 0x00200000
|
#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
|
#define MB_EXCEPT_CLR_SFT 21
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#define MB_EXCEPT_CLR_HI 21
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#define MB_EXCEPT_CLR_SZ 1
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#define MB_EXCEPT_CASE_MSK 0xff000000
|
#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
|
#define MB_EXCEPT_CASE_SFT 24
|
#define MB_EXCEPT_CASE_HI 31
|
#define MB_EXCEPT_CASE_SZ 8
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#define MB_DBG_TIME_STEP_MSK 0x0000ffff
|
#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
|
#define MB_DBG_TIME_STEP_SFT 0
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#define MB_DBG_TIME_STEP_HI 15
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#define MB_DBG_TIME_STEP_SZ 16
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#define DBG_TYPE_MSK 0x00030000
|
#define DBG_TYPE_I_MSK 0xfffcffff
|
#define DBG_TYPE_SFT 16
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#define DBG_TYPE_HI 17
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#define DBG_TYPE_SZ 2
|
#define MB_DBG_CLR_MSK 0x00040000
|
#define MB_DBG_CLR_I_MSK 0xfffbffff
|
#define MB_DBG_CLR_SFT 18
|
#define MB_DBG_CLR_HI 18
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#define MB_DBG_CLR_SZ 1
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#define DBG_ALC_LOG_EN_MSK 0x00080000
|
#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
|
#define DBG_ALC_LOG_EN_SFT 19
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#define DBG_ALC_LOG_EN_HI 19
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#define DBG_ALC_LOG_EN_SZ 1
|
#define MB_DBG_COUNTER_EN_MSK 0x01000000
|
#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
|
#define MB_DBG_COUNTER_EN_SFT 24
|
#define MB_DBG_COUNTER_EN_HI 24
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#define MB_DBG_COUNTER_EN_SZ 1
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#define MB_DBG_EN_MSK 0x80000000
|
#define MB_DBG_EN_I_MSK 0x7fffffff
|
#define MB_DBG_EN_SFT 31
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#define MB_DBG_EN_HI 31
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#define MB_DBG_EN_SZ 1
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#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
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#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
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#define MB_DBG_RECORD_CNT_SFT 0
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#define MB_DBG_RECORD_CNT_HI 15
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#define MB_DBG_RECORD_CNT_SZ 16
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#define MB_DBG_LENGTH_MSK 0xffff0000
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#define MB_DBG_LENGTH_I_MSK 0x0000ffff
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#define MB_DBG_LENGTH_SFT 16
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#define MB_DBG_LENGTH_HI 31
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#define MB_DBG_LENGTH_SZ 16
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#define MB_DBG_CFG_ADDR_MSK 0xffffffff
|
#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
|
#define MB_DBG_CFG_ADDR_SFT 0
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#define MB_DBG_CFG_ADDR_HI 31
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#define MB_DBG_CFG_ADDR_SZ 32
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#define DBG_HWID0_WR_EN_MSK 0x00000001
|
#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
|
#define DBG_HWID0_WR_EN_SFT 0
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#define DBG_HWID0_WR_EN_HI 0
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#define DBG_HWID0_WR_EN_SZ 1
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#define DBG_HWID1_WR_EN_MSK 0x00000002
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#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
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#define DBG_HWID1_WR_EN_SFT 1
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#define DBG_HWID1_WR_EN_HI 1
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#define DBG_HWID1_WR_EN_SZ 1
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#define DBG_HWID2_WR_EN_MSK 0x00000004
|
#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
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#define DBG_HWID2_WR_EN_SFT 2
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#define DBG_HWID2_WR_EN_HI 2
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#define DBG_HWID2_WR_EN_SZ 1
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#define DBG_HWID3_WR_EN_MSK 0x00000008
|
#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
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#define DBG_HWID3_WR_EN_SFT 3
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#define DBG_HWID3_WR_EN_HI 3
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#define DBG_HWID3_WR_EN_SZ 1
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#define DBG_HWID4_WR_EN_MSK 0x00000010
|
#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
|
#define DBG_HWID4_WR_EN_SFT 4
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#define DBG_HWID4_WR_EN_HI 4
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#define DBG_HWID4_WR_EN_SZ 1
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#define DBG_HWID5_WR_EN_MSK 0x00000020
|
#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
|
#define DBG_HWID5_WR_EN_SFT 5
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#define DBG_HWID5_WR_EN_HI 5
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#define DBG_HWID5_WR_EN_SZ 1
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#define DBG_HWID6_WR_EN_MSK 0x00000040
|
#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
|
#define DBG_HWID6_WR_EN_SFT 6
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#define DBG_HWID6_WR_EN_HI 6
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#define DBG_HWID6_WR_EN_SZ 1
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#define DBG_HWID7_WR_EN_MSK 0x00000080
|
#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
|
#define DBG_HWID7_WR_EN_SFT 7
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#define DBG_HWID7_WR_EN_HI 7
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#define DBG_HWID7_WR_EN_SZ 1
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#define DBG_HWID8_WR_EN_MSK 0x00000100
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#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
|
#define DBG_HWID8_WR_EN_SFT 8
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#define DBG_HWID8_WR_EN_HI 8
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#define DBG_HWID8_WR_EN_SZ 1
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#define DBG_HWID9_WR_EN_MSK 0x00000200
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#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
|
#define DBG_HWID9_WR_EN_SFT 9
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#define DBG_HWID9_WR_EN_HI 9
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#define DBG_HWID9_WR_EN_SZ 1
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#define DBG_HWID10_WR_EN_MSK 0x00000400
|
#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
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#define DBG_HWID10_WR_EN_SFT 10
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#define DBG_HWID10_WR_EN_HI 10
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#define DBG_HWID10_WR_EN_SZ 1
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#define DBG_HWID11_WR_EN_MSK 0x00000800
|
#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
|
#define DBG_HWID11_WR_EN_SFT 11
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#define DBG_HWID11_WR_EN_HI 11
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#define DBG_HWID11_WR_EN_SZ 1
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#define DBG_HWID12_WR_EN_MSK 0x00001000
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#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
|
#define DBG_HWID12_WR_EN_SFT 12
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#define DBG_HWID12_WR_EN_HI 12
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#define DBG_HWID12_WR_EN_SZ 1
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#define DBG_HWID13_WR_EN_MSK 0x00002000
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#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
|
#define DBG_HWID13_WR_EN_SFT 13
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#define DBG_HWID13_WR_EN_HI 13
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#define DBG_HWID13_WR_EN_SZ 1
|
#define DBG_HWID14_WR_EN_MSK 0x00004000
|
#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
|
#define DBG_HWID14_WR_EN_SFT 14
|
#define DBG_HWID14_WR_EN_HI 14
|
#define DBG_HWID14_WR_EN_SZ 1
|
#define DBG_HWID15_WR_EN_MSK 0x00008000
|
#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
|
#define DBG_HWID15_WR_EN_SFT 15
|
#define DBG_HWID15_WR_EN_HI 15
|
#define DBG_HWID15_WR_EN_SZ 1
|
#define DBG_HWID0_RD_EN_MSK 0x00010000
|
#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
|
#define DBG_HWID0_RD_EN_SFT 16
|
#define DBG_HWID0_RD_EN_HI 16
|
#define DBG_HWID0_RD_EN_SZ 1
|
#define DBG_HWID1_RD_EN_MSK 0x00020000
|
#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
|
#define DBG_HWID1_RD_EN_SFT 17
|
#define DBG_HWID1_RD_EN_HI 17
|
#define DBG_HWID1_RD_EN_SZ 1
|
#define DBG_HWID2_RD_EN_MSK 0x00040000
|
#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
|
#define DBG_HWID2_RD_EN_SFT 18
|
#define DBG_HWID2_RD_EN_HI 18
|
#define DBG_HWID2_RD_EN_SZ 1
|
#define DBG_HWID3_RD_EN_MSK 0x00080000
|
#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
|
#define DBG_HWID3_RD_EN_SFT 19
|
#define DBG_HWID3_RD_EN_HI 19
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#define DBG_HWID3_RD_EN_SZ 1
|
#define DBG_HWID4_RD_EN_MSK 0x00100000
|
#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
|
#define DBG_HWID4_RD_EN_SFT 20
|
#define DBG_HWID4_RD_EN_HI 20
|
#define DBG_HWID4_RD_EN_SZ 1
|
#define DBG_HWID5_RD_EN_MSK 0x00200000
|
#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
|
#define DBG_HWID5_RD_EN_SFT 21
|
#define DBG_HWID5_RD_EN_HI 21
|
#define DBG_HWID5_RD_EN_SZ 1
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#define DBG_HWID6_RD_EN_MSK 0x00400000
|
#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
|
#define DBG_HWID6_RD_EN_SFT 22
|
#define DBG_HWID6_RD_EN_HI 22
|
#define DBG_HWID6_RD_EN_SZ 1
|
#define DBG_HWID7_RD_EN_MSK 0x00800000
|
#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
|
#define DBG_HWID7_RD_EN_SFT 23
|
#define DBG_HWID7_RD_EN_HI 23
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#define DBG_HWID7_RD_EN_SZ 1
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#define DBG_HWID8_RD_EN_MSK 0x01000000
|
#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
|
#define DBG_HWID8_RD_EN_SFT 24
|
#define DBG_HWID8_RD_EN_HI 24
|
#define DBG_HWID8_RD_EN_SZ 1
|
#define DBG_HWID9_RD_EN_MSK 0x02000000
|
#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
|
#define DBG_HWID9_RD_EN_SFT 25
|
#define DBG_HWID9_RD_EN_HI 25
|
#define DBG_HWID9_RD_EN_SZ 1
|
#define DBG_HWID10_RD_EN_MSK 0x04000000
|
#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
|
#define DBG_HWID10_RD_EN_SFT 26
|
#define DBG_HWID10_RD_EN_HI 26
|
#define DBG_HWID10_RD_EN_SZ 1
|
#define DBG_HWID11_RD_EN_MSK 0x08000000
|
#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
|
#define DBG_HWID11_RD_EN_SFT 27
|
#define DBG_HWID11_RD_EN_HI 27
|
#define DBG_HWID11_RD_EN_SZ 1
|
#define DBG_HWID12_RD_EN_MSK 0x10000000
|
#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
|
#define DBG_HWID12_RD_EN_SFT 28
|
#define DBG_HWID12_RD_EN_HI 28
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#define DBG_HWID12_RD_EN_SZ 1
|
#define DBG_HWID13_RD_EN_MSK 0x20000000
|
#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
|
#define DBG_HWID13_RD_EN_SFT 29
|
#define DBG_HWID13_RD_EN_HI 29
|
#define DBG_HWID13_RD_EN_SZ 1
|
#define DBG_HWID14_RD_EN_MSK 0x40000000
|
#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
|
#define DBG_HWID14_RD_EN_SFT 30
|
#define DBG_HWID14_RD_EN_HI 30
|
#define DBG_HWID14_RD_EN_SZ 1
|
#define DBG_HWID15_RD_EN_MSK 0x80000000
|
#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
|
#define DBG_HWID15_RD_EN_SFT 31
|
#define DBG_HWID15_RD_EN_HI 31
|
#define DBG_HWID15_RD_EN_SZ 1
|
#define MB_OUT_QUEUE_EN_MSK 0x00000002
|
#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
|
#define MB_OUT_QUEUE_EN_SFT 1
|
#define MB_OUT_QUEUE_EN_HI 1
|
#define MB_OUT_QUEUE_EN_SZ 1
|
#define CH0_QUEUE_FLUSH_MSK 0x00000001
|
#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
|
#define CH0_QUEUE_FLUSH_SFT 0
|
#define CH0_QUEUE_FLUSH_HI 0
|
#define CH0_QUEUE_FLUSH_SZ 1
|
#define CH1_QUEUE_FLUSH_MSK 0x00000002
|
#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
|
#define CH1_QUEUE_FLUSH_SFT 1
|
#define CH1_QUEUE_FLUSH_HI 1
|
#define CH1_QUEUE_FLUSH_SZ 1
|
#define CH2_QUEUE_FLUSH_MSK 0x00000004
|
#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
|
#define CH2_QUEUE_FLUSH_SFT 2
|
#define CH2_QUEUE_FLUSH_HI 2
|
#define CH2_QUEUE_FLUSH_SZ 1
|
#define CH3_QUEUE_FLUSH_MSK 0x00000008
|
#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
|
#define CH3_QUEUE_FLUSH_SFT 3
|
#define CH3_QUEUE_FLUSH_HI 3
|
#define CH3_QUEUE_FLUSH_SZ 1
|
#define CH4_QUEUE_FLUSH_MSK 0x00000010
|
#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
|
#define CH4_QUEUE_FLUSH_SFT 4
|
#define CH4_QUEUE_FLUSH_HI 4
|
#define CH4_QUEUE_FLUSH_SZ 1
|
#define CH5_QUEUE_FLUSH_MSK 0x00000020
|
#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
|
#define CH5_QUEUE_FLUSH_SFT 5
|
#define CH5_QUEUE_FLUSH_HI 5
|
#define CH5_QUEUE_FLUSH_SZ 1
|
#define CH6_QUEUE_FLUSH_MSK 0x00000040
|
#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
|
#define CH6_QUEUE_FLUSH_SFT 6
|
#define CH6_QUEUE_FLUSH_HI 6
|
#define CH6_QUEUE_FLUSH_SZ 1
|
#define CH7_QUEUE_FLUSH_MSK 0x00000080
|
#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
|
#define CH7_QUEUE_FLUSH_SFT 7
|
#define CH7_QUEUE_FLUSH_HI 7
|
#define CH7_QUEUE_FLUSH_SZ 1
|
#define CH8_QUEUE_FLUSH_MSK 0x00000100
|
#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
|
#define CH8_QUEUE_FLUSH_SFT 8
|
#define CH8_QUEUE_FLUSH_HI 8
|
#define CH8_QUEUE_FLUSH_SZ 1
|
#define CH9_QUEUE_FLUSH_MSK 0x00000200
|
#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
|
#define CH9_QUEUE_FLUSH_SFT 9
|
#define CH9_QUEUE_FLUSH_HI 9
|
#define CH9_QUEUE_FLUSH_SZ 1
|
#define CH10_QUEUE_FLUSH_MSK 0x00000400
|
#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
|
#define CH10_QUEUE_FLUSH_SFT 10
|
#define CH10_QUEUE_FLUSH_HI 10
|
#define CH10_QUEUE_FLUSH_SZ 1
|
#define CH11_QUEUE_FLUSH_MSK 0x00000800
|
#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
|
#define CH11_QUEUE_FLUSH_SFT 11
|
#define CH11_QUEUE_FLUSH_HI 11
|
#define CH11_QUEUE_FLUSH_SZ 1
|
#define CH12_QUEUE_FLUSH_MSK 0x00001000
|
#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
|
#define CH12_QUEUE_FLUSH_SFT 12
|
#define CH12_QUEUE_FLUSH_HI 12
|
#define CH12_QUEUE_FLUSH_SZ 1
|
#define CH13_QUEUE_FLUSH_MSK 0x00002000
|
#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
|
#define CH13_QUEUE_FLUSH_SFT 13
|
#define CH13_QUEUE_FLUSH_HI 13
|
#define CH13_QUEUE_FLUSH_SZ 1
|
#define CH14_QUEUE_FLUSH_MSK 0x00004000
|
#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
|
#define CH14_QUEUE_FLUSH_SFT 14
|
#define CH14_QUEUE_FLUSH_HI 14
|
#define CH14_QUEUE_FLUSH_SZ 1
|
#define CH15_QUEUE_FLUSH_MSK 0x00008000
|
#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
|
#define CH15_QUEUE_FLUSH_SFT 15
|
#define CH15_QUEUE_FLUSH_HI 15
|
#define CH15_QUEUE_FLUSH_SZ 1
|
#define FFO0_CNT_MSK 0x0000001f
|
#define FFO0_CNT_I_MSK 0xffffffe0
|
#define FFO0_CNT_SFT 0
|
#define FFO0_CNT_HI 4
|
#define FFO0_CNT_SZ 5
|
#define FFO1_CNT_MSK 0x000003e0
|
#define FFO1_CNT_I_MSK 0xfffffc1f
|
#define FFO1_CNT_SFT 5
|
#define FFO1_CNT_HI 9
|
#define FFO1_CNT_SZ 5
|
#define FFO2_CNT_MSK 0x00000c00
|
#define FFO2_CNT_I_MSK 0xfffff3ff
|
#define FFO2_CNT_SFT 10
|
#define FFO2_CNT_HI 11
|
#define FFO2_CNT_SZ 2
|
#define FFO3_CNT_MSK 0x000f8000
|
#define FFO3_CNT_I_MSK 0xfff07fff
|
#define FFO3_CNT_SFT 15
|
#define FFO3_CNT_HI 19
|
#define FFO3_CNT_SZ 5
|
#define FFO4_CNT_MSK 0x00300000
|
#define FFO4_CNT_I_MSK 0xffcfffff
|
#define FFO4_CNT_SFT 20
|
#define FFO4_CNT_HI 21
|
#define FFO4_CNT_SZ 2
|
#define FFO5_CNT_MSK 0x0e000000
|
#define FFO5_CNT_I_MSK 0xf1ffffff
|
#define FFO5_CNT_SFT 25
|
#define FFO5_CNT_HI 27
|
#define FFO5_CNT_SZ 3
|
#define FFO6_CNT_MSK 0x0000000f
|
#define FFO6_CNT_I_MSK 0xfffffff0
|
#define FFO6_CNT_SFT 0
|
#define FFO6_CNT_HI 3
|
#define FFO6_CNT_SZ 4
|
#define FFO7_CNT_MSK 0x000003e0
|
#define FFO7_CNT_I_MSK 0xfffffc1f
|
#define FFO7_CNT_SFT 5
|
#define FFO7_CNT_HI 9
|
#define FFO7_CNT_SZ 5
|
#define FFO8_CNT_MSK 0x00007c00
|
#define FFO8_CNT_I_MSK 0xffff83ff
|
#define FFO8_CNT_SFT 10
|
#define FFO8_CNT_HI 14
|
#define FFO8_CNT_SZ 5
|
#define FFO9_CNT_MSK 0x000f8000
|
#define FFO9_CNT_I_MSK 0xfff07fff
|
#define FFO9_CNT_SFT 15
|
#define FFO9_CNT_HI 19
|
#define FFO9_CNT_SZ 5
|
#define FFO10_CNT_MSK 0x00f00000
|
#define FFO10_CNT_I_MSK 0xff0fffff
|
#define FFO10_CNT_SFT 20
|
#define FFO10_CNT_HI 23
|
#define FFO10_CNT_SZ 4
|
#define FFO11_CNT_MSK 0x3e000000
|
#define FFO11_CNT_I_MSK 0xc1ffffff
|
#define FFO11_CNT_SFT 25
|
#define FFO11_CNT_HI 29
|
#define FFO11_CNT_SZ 5
|
#define FFO12_CNT_MSK 0x00000007
|
#define FFO12_CNT_I_MSK 0xfffffff8
|
#define FFO12_CNT_SFT 0
|
#define FFO12_CNT_HI 2
|
#define FFO12_CNT_SZ 3
|
#define FFO13_CNT_MSK 0x00000060
|
#define FFO13_CNT_I_MSK 0xffffff9f
|
#define FFO13_CNT_SFT 5
|
#define FFO13_CNT_HI 6
|
#define FFO13_CNT_SZ 2
|
#define FFO14_CNT_MSK 0x00000c00
|
#define FFO14_CNT_I_MSK 0xfffff3ff
|
#define FFO14_CNT_SFT 10
|
#define FFO14_CNT_HI 11
|
#define FFO14_CNT_SZ 2
|
#define FFO15_CNT_MSK 0x001f8000
|
#define FFO15_CNT_I_MSK 0xffe07fff
|
#define FFO15_CNT_SFT 15
|
#define FFO15_CNT_HI 20
|
#define FFO15_CNT_SZ 6
|
#define CH0_FFO_FULL_MSK 0x00000001
|
#define CH0_FFO_FULL_I_MSK 0xfffffffe
|
#define CH0_FFO_FULL_SFT 0
|
#define CH0_FFO_FULL_HI 0
|
#define CH0_FFO_FULL_SZ 1
|
#define CH1_FFO_FULL_MSK 0x00000002
|
#define CH1_FFO_FULL_I_MSK 0xfffffffd
|
#define CH1_FFO_FULL_SFT 1
|
#define CH1_FFO_FULL_HI 1
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#define CH1_FFO_FULL_SZ 1
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#define CH2_FFO_FULL_MSK 0x00000004
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#define CH2_FFO_FULL_I_MSK 0xfffffffb
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#define CH2_FFO_FULL_SFT 2
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#define CH2_FFO_FULL_HI 2
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#define CH2_FFO_FULL_SZ 1
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#define CH3_FFO_FULL_MSK 0x00000008
|
#define CH3_FFO_FULL_I_MSK 0xfffffff7
|
#define CH3_FFO_FULL_SFT 3
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#define CH3_FFO_FULL_HI 3
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#define CH3_FFO_FULL_SZ 1
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#define CH4_FFO_FULL_MSK 0x00000010
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#define CH4_FFO_FULL_I_MSK 0xffffffef
|
#define CH4_FFO_FULL_SFT 4
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#define CH4_FFO_FULL_HI 4
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#define CH4_FFO_FULL_SZ 1
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#define CH5_FFO_FULL_MSK 0x00000020
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#define CH5_FFO_FULL_I_MSK 0xffffffdf
|
#define CH5_FFO_FULL_SFT 5
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#define CH5_FFO_FULL_HI 5
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#define CH5_FFO_FULL_SZ 1
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#define CH6_FFO_FULL_MSK 0x00000040
|
#define CH6_FFO_FULL_I_MSK 0xffffffbf
|
#define CH6_FFO_FULL_SFT 6
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#define CH6_FFO_FULL_HI 6
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#define CH6_FFO_FULL_SZ 1
|
#define CH7_FFO_FULL_MSK 0x00000080
|
#define CH7_FFO_FULL_I_MSK 0xffffff7f
|
#define CH7_FFO_FULL_SFT 7
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#define CH7_FFO_FULL_HI 7
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#define CH7_FFO_FULL_SZ 1
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#define CH8_FFO_FULL_MSK 0x00000100
|
#define CH8_FFO_FULL_I_MSK 0xfffffeff
|
#define CH8_FFO_FULL_SFT 8
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#define CH8_FFO_FULL_HI 8
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#define CH8_FFO_FULL_SZ 1
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#define CH9_FFO_FULL_MSK 0x00000200
|
#define CH9_FFO_FULL_I_MSK 0xfffffdff
|
#define CH9_FFO_FULL_SFT 9
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#define CH9_FFO_FULL_HI 9
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#define CH9_FFO_FULL_SZ 1
|
#define CH10_FFO_FULL_MSK 0x00000400
|
#define CH10_FFO_FULL_I_MSK 0xfffffbff
|
#define CH10_FFO_FULL_SFT 10
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#define CH10_FFO_FULL_HI 10
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#define CH10_FFO_FULL_SZ 1
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#define CH11_FFO_FULL_MSK 0x00000800
|
#define CH11_FFO_FULL_I_MSK 0xfffff7ff
|
#define CH11_FFO_FULL_SFT 11
|
#define CH11_FFO_FULL_HI 11
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#define CH11_FFO_FULL_SZ 1
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#define CH12_FFO_FULL_MSK 0x00001000
|
#define CH12_FFO_FULL_I_MSK 0xffffefff
|
#define CH12_FFO_FULL_SFT 12
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#define CH12_FFO_FULL_HI 12
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#define CH12_FFO_FULL_SZ 1
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#define CH13_FFO_FULL_MSK 0x00002000
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#define CH13_FFO_FULL_I_MSK 0xffffdfff
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#define CH13_FFO_FULL_SFT 13
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#define CH13_FFO_FULL_HI 13
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#define CH13_FFO_FULL_SZ 1
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#define CH14_FFO_FULL_MSK 0x00004000
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#define CH14_FFO_FULL_I_MSK 0xffffbfff
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#define CH14_FFO_FULL_SFT 14
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#define CH14_FFO_FULL_HI 14
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#define CH14_FFO_FULL_SZ 1
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#define CH15_FFO_FULL_MSK 0x00008000
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#define CH15_FFO_FULL_I_MSK 0xffff7fff
|
#define CH15_FFO_FULL_SFT 15
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#define CH15_FFO_FULL_HI 15
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#define CH15_FFO_FULL_SZ 1
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#define CH0_LOWTHOLD_INT_MSK 0x00000001
|
#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
|
#define CH0_LOWTHOLD_INT_SFT 0
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#define CH0_LOWTHOLD_INT_HI 0
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#define CH0_LOWTHOLD_INT_SZ 1
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#define CH1_LOWTHOLD_INT_MSK 0x00000002
|
#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
|
#define CH1_LOWTHOLD_INT_SFT 1
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#define CH1_LOWTHOLD_INT_HI 1
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#define CH1_LOWTHOLD_INT_SZ 1
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#define CH2_LOWTHOLD_INT_MSK 0x00000004
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#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
|
#define CH2_LOWTHOLD_INT_SFT 2
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#define CH2_LOWTHOLD_INT_HI 2
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#define CH2_LOWTHOLD_INT_SZ 1
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#define CH3_LOWTHOLD_INT_MSK 0x00000008
|
#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
|
#define CH3_LOWTHOLD_INT_SFT 3
|
#define CH3_LOWTHOLD_INT_HI 3
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#define CH3_LOWTHOLD_INT_SZ 1
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#define CH4_LOWTHOLD_INT_MSK 0x00000010
|
#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
|
#define CH4_LOWTHOLD_INT_SFT 4
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#define CH4_LOWTHOLD_INT_HI 4
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#define CH4_LOWTHOLD_INT_SZ 1
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#define CH5_LOWTHOLD_INT_MSK 0x00000020
|
#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
|
#define CH5_LOWTHOLD_INT_SFT 5
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#define CH5_LOWTHOLD_INT_HI 5
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#define CH5_LOWTHOLD_INT_SZ 1
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#define CH6_LOWTHOLD_INT_MSK 0x00000040
|
#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
|
#define CH6_LOWTHOLD_INT_SFT 6
|
#define CH6_LOWTHOLD_INT_HI 6
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#define CH6_LOWTHOLD_INT_SZ 1
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#define CH7_LOWTHOLD_INT_MSK 0x00000080
|
#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
|
#define CH7_LOWTHOLD_INT_SFT 7
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#define CH7_LOWTHOLD_INT_HI 7
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#define CH7_LOWTHOLD_INT_SZ 1
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#define CH8_LOWTHOLD_INT_MSK 0x00000100
|
#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
|
#define CH8_LOWTHOLD_INT_SFT 8
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#define CH8_LOWTHOLD_INT_HI 8
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#define CH8_LOWTHOLD_INT_SZ 1
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#define CH9_LOWTHOLD_INT_MSK 0x00000200
|
#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
|
#define CH9_LOWTHOLD_INT_SFT 9
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#define CH9_LOWTHOLD_INT_HI 9
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#define CH9_LOWTHOLD_INT_SZ 1
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#define CH10_LOWTHOLD_INT_MSK 0x00000400
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#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
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#define CH10_LOWTHOLD_INT_SFT 10
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#define CH10_LOWTHOLD_INT_HI 10
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#define CH10_LOWTHOLD_INT_SZ 1
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#define CH11_LOWTHOLD_INT_MSK 0x00000800
|
#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
|
#define CH11_LOWTHOLD_INT_SFT 11
|
#define CH11_LOWTHOLD_INT_HI 11
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#define CH11_LOWTHOLD_INT_SZ 1
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#define CH12_LOWTHOLD_INT_MSK 0x00001000
|
#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
|
#define CH12_LOWTHOLD_INT_SFT 12
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#define CH12_LOWTHOLD_INT_HI 12
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#define CH12_LOWTHOLD_INT_SZ 1
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#define CH13_LOWTHOLD_INT_MSK 0x00002000
|
#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
|
#define CH13_LOWTHOLD_INT_SFT 13
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#define CH13_LOWTHOLD_INT_HI 13
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#define CH13_LOWTHOLD_INT_SZ 1
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#define CH14_LOWTHOLD_INT_MSK 0x00004000
|
#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
|
#define CH14_LOWTHOLD_INT_SFT 14
|
#define CH14_LOWTHOLD_INT_HI 14
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#define CH14_LOWTHOLD_INT_SZ 1
|
#define CH15_LOWTHOLD_INT_MSK 0x00008000
|
#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
|
#define CH15_LOWTHOLD_INT_SFT 15
|
#define CH15_LOWTHOLD_INT_HI 15
|
#define CH15_LOWTHOLD_INT_SZ 1
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#define MB_LOW_THOLD_EN_MSK 0x80000000
|
#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
|
#define MB_LOW_THOLD_EN_SFT 31
|
#define MB_LOW_THOLD_EN_HI 31
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#define MB_LOW_THOLD_EN_SZ 1
|
#define CH0_LOWTHOLD_MSK 0x0000001f
|
#define CH0_LOWTHOLD_I_MSK 0xffffffe0
|
#define CH0_LOWTHOLD_SFT 0
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#define CH0_LOWTHOLD_HI 4
|
#define CH0_LOWTHOLD_SZ 5
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#define CH1_LOWTHOLD_MSK 0x00001f00
|
#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
|
#define CH1_LOWTHOLD_SFT 8
|
#define CH1_LOWTHOLD_HI 12
|
#define CH1_LOWTHOLD_SZ 5
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#define CH2_LOWTHOLD_MSK 0x001f0000
|
#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
|
#define CH2_LOWTHOLD_SFT 16
|
#define CH2_LOWTHOLD_HI 20
|
#define CH2_LOWTHOLD_SZ 5
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#define CH3_LOWTHOLD_MSK 0x1f000000
|
#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
|
#define CH3_LOWTHOLD_SFT 24
|
#define CH3_LOWTHOLD_HI 28
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#define CH3_LOWTHOLD_SZ 5
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#define CH4_LOWTHOLD_MSK 0x0000001f
|
#define CH4_LOWTHOLD_I_MSK 0xffffffe0
|
#define CH4_LOWTHOLD_SFT 0
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#define CH4_LOWTHOLD_HI 4
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#define CH4_LOWTHOLD_SZ 5
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#define CH5_LOWTHOLD_MSK 0x00001f00
|
#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
|
#define CH5_LOWTHOLD_SFT 8
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#define CH5_LOWTHOLD_HI 12
|
#define CH5_LOWTHOLD_SZ 5
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#define CH6_LOWTHOLD_MSK 0x001f0000
|
#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
|
#define CH6_LOWTHOLD_SFT 16
|
#define CH6_LOWTHOLD_HI 20
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#define CH6_LOWTHOLD_SZ 5
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#define CH7_LOWTHOLD_MSK 0x1f000000
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#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
|
#define CH7_LOWTHOLD_SFT 24
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#define CH7_LOWTHOLD_HI 28
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#define CH7_LOWTHOLD_SZ 5
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#define CH8_LOWTHOLD_MSK 0x0000001f
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#define CH8_LOWTHOLD_I_MSK 0xffffffe0
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#define CH8_LOWTHOLD_SFT 0
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#define CH8_LOWTHOLD_HI 4
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#define CH8_LOWTHOLD_SZ 5
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#define CH9_LOWTHOLD_MSK 0x00001f00
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#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
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#define CH9_LOWTHOLD_SFT 8
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#define CH9_LOWTHOLD_HI 12
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#define CH9_LOWTHOLD_SZ 5
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#define CH10_LOWTHOLD_MSK 0x001f0000
|
#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
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#define CH10_LOWTHOLD_SFT 16
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#define CH10_LOWTHOLD_HI 20
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#define CH10_LOWTHOLD_SZ 5
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#define CH11_LOWTHOLD_MSK 0x1f000000
|
#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
|
#define CH11_LOWTHOLD_SFT 24
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#define CH11_LOWTHOLD_HI 28
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#define CH11_LOWTHOLD_SZ 5
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#define CH12_LOWTHOLD_MSK 0x0000001f
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#define CH12_LOWTHOLD_I_MSK 0xffffffe0
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#define CH12_LOWTHOLD_SFT 0
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#define CH12_LOWTHOLD_HI 4
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#define CH12_LOWTHOLD_SZ 5
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#define CH13_LOWTHOLD_MSK 0x00001f00
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#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
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#define CH13_LOWTHOLD_SFT 8
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#define CH13_LOWTHOLD_HI 12
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#define CH13_LOWTHOLD_SZ 5
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#define CH14_LOWTHOLD_MSK 0x001f0000
|
#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
|
#define CH14_LOWTHOLD_SFT 16
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#define CH14_LOWTHOLD_HI 20
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#define CH14_LOWTHOLD_SZ 5
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#define CH15_LOWTHOLD_MSK 0x1f000000
|
#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
|
#define CH15_LOWTHOLD_SFT 24
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#define CH15_LOWTHOLD_HI 28
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#define CH15_LOWTHOLD_SZ 5
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#define TRASH_TIMEOUT_EN_MSK 0x00000001
|
#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
|
#define TRASH_TIMEOUT_EN_SFT 0
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#define TRASH_TIMEOUT_EN_HI 0
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#define TRASH_TIMEOUT_EN_SZ 1
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#define TRASH_CAN_INT_MSK 0x00000002
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#define TRASH_CAN_INT_I_MSK 0xfffffffd
|
#define TRASH_CAN_INT_SFT 1
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#define TRASH_CAN_INT_HI 1
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#define TRASH_CAN_INT_SZ 1
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#define TRASH_INT_ID_MSK 0x000007f0
|
#define TRASH_INT_ID_I_MSK 0xfffff80f
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#define TRASH_INT_ID_SFT 4
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#define TRASH_INT_ID_HI 10
|
#define TRASH_INT_ID_SZ 7
|
#define TRASH_TIMEOUT_MSK 0x03ff0000
|
#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
|
#define TRASH_TIMEOUT_SFT 16
|
#define TRASH_TIMEOUT_HI 25
|
#define TRASH_TIMEOUT_SZ 10
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#define CH0_WRFF_FLUSH_MSK 0x00000001
|
#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
|
#define CH0_WRFF_FLUSH_SFT 0
|
#define CH0_WRFF_FLUSH_HI 0
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#define CH0_WRFF_FLUSH_SZ 1
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#define CH1_WRFF_FLUSH_MSK 0x00000002
|
#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
|
#define CH1_WRFF_FLUSH_SFT 1
|
#define CH1_WRFF_FLUSH_HI 1
|
#define CH1_WRFF_FLUSH_SZ 1
|
#define CH2_WRFF_FLUSH_MSK 0x00000004
|
#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
|
#define CH2_WRFF_FLUSH_SFT 2
|
#define CH2_WRFF_FLUSH_HI 2
|
#define CH2_WRFF_FLUSH_SZ 1
|
#define CH3_WRFF_FLUSH_MSK 0x00000008
|
#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
|
#define CH3_WRFF_FLUSH_SFT 3
|
#define CH3_WRFF_FLUSH_HI 3
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#define CH3_WRFF_FLUSH_SZ 1
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#define CH4_WRFF_FLUSH_MSK 0x00000010
|
#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
|
#define CH4_WRFF_FLUSH_SFT 4
|
#define CH4_WRFF_FLUSH_HI 4
|
#define CH4_WRFF_FLUSH_SZ 1
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#define CH5_WRFF_FLUSH_MSK 0x00000020
|
#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
|
#define CH5_WRFF_FLUSH_SFT 5
|
#define CH5_WRFF_FLUSH_HI 5
|
#define CH5_WRFF_FLUSH_SZ 1
|
#define CH6_WRFF_FLUSH_MSK 0x00000040
|
#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
|
#define CH6_WRFF_FLUSH_SFT 6
|
#define CH6_WRFF_FLUSH_HI 6
|
#define CH6_WRFF_FLUSH_SZ 1
|
#define CH7_WRFF_FLUSH_MSK 0x00000080
|
#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
|
#define CH7_WRFF_FLUSH_SFT 7
|
#define CH7_WRFF_FLUSH_HI 7
|
#define CH7_WRFF_FLUSH_SZ 1
|
#define CH8_WRFF_FLUSH_MSK 0x00000100
|
#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
|
#define CH8_WRFF_FLUSH_SFT 8
|
#define CH8_WRFF_FLUSH_HI 8
|
#define CH8_WRFF_FLUSH_SZ 1
|
#define CH9_WRFF_FLUSH_MSK 0x00000200
|
#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
|
#define CH9_WRFF_FLUSH_SFT 9
|
#define CH9_WRFF_FLUSH_HI 9
|
#define CH9_WRFF_FLUSH_SZ 1
|
#define CH10_WRFF_FLUSH_MSK 0x00000400
|
#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
|
#define CH10_WRFF_FLUSH_SFT 10
|
#define CH10_WRFF_FLUSH_HI 10
|
#define CH10_WRFF_FLUSH_SZ 1
|
#define CH11_WRFF_FLUSH_MSK 0x00000800
|
#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
|
#define CH11_WRFF_FLUSH_SFT 11
|
#define CH11_WRFF_FLUSH_HI 11
|
#define CH11_WRFF_FLUSH_SZ 1
|
#define CH12_WRFF_FLUSH_MSK 0x00001000
|
#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
|
#define CH12_WRFF_FLUSH_SFT 12
|
#define CH12_WRFF_FLUSH_HI 12
|
#define CH12_WRFF_FLUSH_SZ 1
|
#define CH13_WRFF_FLUSH_MSK 0x00002000
|
#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
|
#define CH13_WRFF_FLUSH_SFT 13
|
#define CH13_WRFF_FLUSH_HI 13
|
#define CH13_WRFF_FLUSH_SZ 1
|
#define CH14_WRFF_FLUSH_MSK 0x00004000
|
#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
|
#define CH14_WRFF_FLUSH_SFT 14
|
#define CH14_WRFF_FLUSH_HI 14
|
#define CH14_WRFF_FLUSH_SZ 1
|
#define CPU_ID_TB2_MSK 0xffffffff
|
#define CPU_ID_TB2_I_MSK 0x00000000
|
#define CPU_ID_TB2_SFT 0
|
#define CPU_ID_TB2_HI 31
|
#define CPU_ID_TB2_SZ 32
|
#define CPU_ID_TB3_MSK 0xffffffff
|
#define CPU_ID_TB3_I_MSK 0x00000000
|
#define CPU_ID_TB3_SFT 0
|
#define CPU_ID_TB3_HI 31
|
#define CPU_ID_TB3_SZ 32
|
#define IQ_LOG_EN_MSK 0x00000001
|
#define IQ_LOG_EN_I_MSK 0xfffffffe
|
#define IQ_LOG_EN_SFT 0
|
#define IQ_LOG_EN_HI 0
|
#define IQ_LOG_EN_SZ 1
|
#define IQ_LOG_STOP_MODE_MSK 0x00000001
|
#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
|
#define IQ_LOG_STOP_MODE_SFT 0
|
#define IQ_LOG_STOP_MODE_HI 0
|
#define IQ_LOG_STOP_MODE_SZ 1
|
#define GPIO_STOP_EN_MSK 0x00000010
|
#define GPIO_STOP_EN_I_MSK 0xffffffef
|
#define GPIO_STOP_EN_SFT 4
|
#define GPIO_STOP_EN_HI 4
|
#define GPIO_STOP_EN_SZ 1
|
#define GPIO_STOP_POL_MSK 0x00000020
|
#define GPIO_STOP_POL_I_MSK 0xffffffdf
|
#define GPIO_STOP_POL_SFT 5
|
#define GPIO_STOP_POL_HI 5
|
#define GPIO_STOP_POL_SZ 1
|
#define IQ_LOG_TIMER_MSK 0xffff0000
|
#define IQ_LOG_TIMER_I_MSK 0x0000ffff
|
#define IQ_LOG_TIMER_SFT 16
|
#define IQ_LOG_TIMER_HI 31
|
#define IQ_LOG_TIMER_SZ 16
|
#define IQ_LOG_LEN_MSK 0x0000ffff
|
#define IQ_LOG_LEN_I_MSK 0xffff0000
|
#define IQ_LOG_LEN_SFT 0
|
#define IQ_LOG_LEN_HI 15
|
#define IQ_LOG_LEN_SZ 16
|
#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
|
#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
|
#define IQ_LOG_TAIL_ADR_SFT 0
|
#define IQ_LOG_TAIL_ADR_HI 15
|
#define IQ_LOG_TAIL_ADR_SZ 16
|
#define ALC_LENG_MSK 0x0003ffff
|
#define ALC_LENG_I_MSK 0xfffc0000
|
#define ALC_LENG_SFT 0
|
#define ALC_LENG_HI 17
|
#define ALC_LENG_SZ 18
|
#define CH0_DYN_PRI_MSK 0x00300000
|
#define CH0_DYN_PRI_I_MSK 0xffcfffff
|
#define CH0_DYN_PRI_SFT 20
|
#define CH0_DYN_PRI_HI 21
|
#define CH0_DYN_PRI_SZ 2
|
#define MCU_PKTID_MSK 0xffffffff
|
#define MCU_PKTID_I_MSK 0x00000000
|
#define MCU_PKTID_SFT 0
|
#define MCU_PKTID_HI 31
|
#define MCU_PKTID_SZ 32
|
#define CH0_STA_PRI_MSK 0x00000003
|
#define CH0_STA_PRI_I_MSK 0xfffffffc
|
#define CH0_STA_PRI_SFT 0
|
#define CH0_STA_PRI_HI 1
|
#define CH0_STA_PRI_SZ 2
|
#define CH1_STA_PRI_MSK 0x00000030
|
#define CH1_STA_PRI_I_MSK 0xffffffcf
|
#define CH1_STA_PRI_SFT 4
|
#define CH1_STA_PRI_HI 5
|
#define CH1_STA_PRI_SZ 2
|
#define CH2_STA_PRI_MSK 0x00000300
|
#define CH2_STA_PRI_I_MSK 0xfffffcff
|
#define CH2_STA_PRI_SFT 8
|
#define CH2_STA_PRI_HI 9
|
#define CH2_STA_PRI_SZ 2
|
#define CH3_STA_PRI_MSK 0x00003000
|
#define CH3_STA_PRI_I_MSK 0xffffcfff
|
#define CH3_STA_PRI_SFT 12
|
#define CH3_STA_PRI_HI 13
|
#define CH3_STA_PRI_SZ 2
|
#define ID_TB0_MSK 0xffffffff
|
#define ID_TB0_I_MSK 0x00000000
|
#define ID_TB0_SFT 0
|
#define ID_TB0_HI 31
|
#define ID_TB0_SZ 32
|
#define ID_TB1_MSK 0xffffffff
|
#define ID_TB1_I_MSK 0x00000000
|
#define ID_TB1_SFT 0
|
#define ID_TB1_HI 31
|
#define ID_TB1_SZ 32
|
#define ID_MNG_HALT_MSK 0x00000010
|
#define ID_MNG_HALT_I_MSK 0xffffffef
|
#define ID_MNG_HALT_SFT 4
|
#define ID_MNG_HALT_HI 4
|
#define ID_MNG_HALT_SZ 1
|
#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
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#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
|
#define ID_MNG_ERR_HALT_EN_SFT 5
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#define ID_MNG_ERR_HALT_EN_HI 5
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#define ID_MNG_ERR_HALT_EN_SZ 1
|
#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
|
#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
|
#define ID_EXCEPT_FLG_CLR_SFT 6
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#define ID_EXCEPT_FLG_CLR_HI 6
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#define ID_EXCEPT_FLG_CLR_SZ 1
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#define ID_EXCEPT_FLG_MSK 0x00000080
|
#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
|
#define ID_EXCEPT_FLG_SFT 7
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#define ID_EXCEPT_FLG_HI 7
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#define ID_EXCEPT_FLG_SZ 1
|
#define ID_FULL_MSK 0x00000001
|
#define ID_FULL_I_MSK 0xfffffffe
|
#define ID_FULL_SFT 0
|
#define ID_FULL_HI 0
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#define ID_FULL_SZ 1
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#define ID_MNG_BUSY_MSK 0x00000002
|
#define ID_MNG_BUSY_I_MSK 0xfffffffd
|
#define ID_MNG_BUSY_SFT 1
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#define ID_MNG_BUSY_HI 1
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#define ID_MNG_BUSY_SZ 1
|
#define REQ_LOCK_MSK 0x00000004
|
#define REQ_LOCK_I_MSK 0xfffffffb
|
#define REQ_LOCK_SFT 2
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#define REQ_LOCK_HI 2
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#define REQ_LOCK_SZ 1
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#define CH0_REQ_LOCK_MSK 0x00000010
|
#define CH0_REQ_LOCK_I_MSK 0xffffffef
|
#define CH0_REQ_LOCK_SFT 4
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#define CH0_REQ_LOCK_HI 4
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#define CH0_REQ_LOCK_SZ 1
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#define CH1_REQ_LOCK_MSK 0x00000020
|
#define CH1_REQ_LOCK_I_MSK 0xffffffdf
|
#define CH1_REQ_LOCK_SFT 5
|
#define CH1_REQ_LOCK_HI 5
|
#define CH1_REQ_LOCK_SZ 1
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#define CH2_REQ_LOCK_MSK 0x00000040
|
#define CH2_REQ_LOCK_I_MSK 0xffffffbf
|
#define CH2_REQ_LOCK_SFT 6
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#define CH2_REQ_LOCK_HI 6
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#define CH2_REQ_LOCK_SZ 1
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#define CH3_REQ_LOCK_MSK 0x00000080
|
#define CH3_REQ_LOCK_I_MSK 0xffffff7f
|
#define CH3_REQ_LOCK_SFT 7
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#define CH3_REQ_LOCK_HI 7
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#define CH3_REQ_LOCK_SZ 1
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#define REQ_LOCK_INT_EN_MSK 0x00000100
|
#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
|
#define REQ_LOCK_INT_EN_SFT 8
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#define REQ_LOCK_INT_EN_HI 8
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#define REQ_LOCK_INT_EN_SZ 1
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#define REQ_LOCK_INT_MSK 0x00000200
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#define REQ_LOCK_INT_I_MSK 0xfffffdff
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#define REQ_LOCK_INT_SFT 9
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#define REQ_LOCK_INT_HI 9
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#define REQ_LOCK_INT_SZ 1
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#define MCU_ALC_READY_MSK 0x00000001
|
#define MCU_ALC_READY_I_MSK 0xfffffffe
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#define MCU_ALC_READY_SFT 0
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#define MCU_ALC_READY_HI 0
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#define MCU_ALC_READY_SZ 1
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#define ALC_FAIL_MSK 0x00000002
|
#define ALC_FAIL_I_MSK 0xfffffffd
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#define ALC_FAIL_SFT 1
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#define ALC_FAIL_HI 1
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#define ALC_FAIL_SZ 1
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#define ALC_BUSY_MSK 0x00000004
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#define ALC_BUSY_I_MSK 0xfffffffb
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#define ALC_BUSY_SFT 2
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#define ALC_BUSY_HI 2
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#define ALC_BUSY_SZ 1
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#define CH0_NVLD_MSK 0x00000010
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#define CH0_NVLD_I_MSK 0xffffffef
|
#define CH0_NVLD_SFT 4
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#define CH0_NVLD_HI 4
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#define CH0_NVLD_SZ 1
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#define CH1_NVLD_MSK 0x00000020
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#define CH1_NVLD_I_MSK 0xffffffdf
|
#define CH1_NVLD_SFT 5
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#define CH1_NVLD_HI 5
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#define CH1_NVLD_SZ 1
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#define CH2_NVLD_MSK 0x00000040
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#define CH2_NVLD_I_MSK 0xffffffbf
|
#define CH2_NVLD_SFT 6
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#define CH2_NVLD_HI 6
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#define CH2_NVLD_SZ 1
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#define CH3_NVLD_MSK 0x00000080
|
#define CH3_NVLD_I_MSK 0xffffff7f
|
#define CH3_NVLD_SFT 7
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#define CH3_NVLD_HI 7
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#define CH3_NVLD_SZ 1
|
#define ALC_INT_ID_MSK 0x00007f00
|
#define ALC_INT_ID_I_MSK 0xffff80ff
|
#define ALC_INT_ID_SFT 8
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#define ALC_INT_ID_HI 14
|
#define ALC_INT_ID_SZ 7
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#define ALC_TIMEOUT_MSK 0x03ff0000
|
#define ALC_TIMEOUT_I_MSK 0xfc00ffff
|
#define ALC_TIMEOUT_SFT 16
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#define ALC_TIMEOUT_HI 25
|
#define ALC_TIMEOUT_SZ 10
|
#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
|
#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
|
#define ALC_TIMEOUT_INT_EN_SFT 30
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#define ALC_TIMEOUT_INT_EN_HI 30
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#define ALC_TIMEOUT_INT_EN_SZ 1
|
#define ALC_TIMEOUT_INT_MSK 0x80000000
|
#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
|
#define ALC_TIMEOUT_INT_SFT 31
|
#define ALC_TIMEOUT_INT_HI 31
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#define ALC_TIMEOUT_INT_SZ 1
|
#define TX_ID_COUNT_MSK 0x000000ff
|
#define TX_ID_COUNT_I_MSK 0xffffff00
|
#define TX_ID_COUNT_SFT 0
|
#define TX_ID_COUNT_HI 7
|
#define TX_ID_COUNT_SZ 8
|
#define RX_ID_COUNT_MSK 0x0000ff00
|
#define RX_ID_COUNT_I_MSK 0xffff00ff
|
#define RX_ID_COUNT_SFT 8
|
#define RX_ID_COUNT_HI 15
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#define RX_ID_COUNT_SZ 8
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#define TX_ID_THOLD_MSK 0x000000ff
|
#define TX_ID_THOLD_I_MSK 0xffffff00
|
#define TX_ID_THOLD_SFT 0
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#define TX_ID_THOLD_HI 7
|
#define TX_ID_THOLD_SZ 8
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#define RX_ID_THOLD_MSK 0x0000ff00
|
#define RX_ID_THOLD_I_MSK 0xffff00ff
|
#define RX_ID_THOLD_SFT 8
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#define RX_ID_THOLD_HI 15
|
#define RX_ID_THOLD_SZ 8
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#define ID_THOLD_RX_INT_MSK 0x00010000
|
#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
|
#define ID_THOLD_RX_INT_SFT 16
|
#define ID_THOLD_RX_INT_HI 16
|
#define ID_THOLD_RX_INT_SZ 1
|
#define RX_INT_CH_MSK 0x000e0000
|
#define RX_INT_CH_I_MSK 0xfff1ffff
|
#define RX_INT_CH_SFT 17
|
#define RX_INT_CH_HI 19
|
#define RX_INT_CH_SZ 3
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#define ID_THOLD_TX_INT_MSK 0x00100000
|
#define ID_THOLD_TX_INT_I_MSK 0xffefffff
|
#define ID_THOLD_TX_INT_SFT 20
|
#define ID_THOLD_TX_INT_HI 20
|
#define ID_THOLD_TX_INT_SZ 1
|
#define TX_INT_CH_MSK 0x00e00000
|
#define TX_INT_CH_I_MSK 0xff1fffff
|
#define TX_INT_CH_SFT 21
|
#define TX_INT_CH_HI 23
|
#define TX_INT_CH_SZ 3
|
#define ID_THOLD_INT_EN_MSK 0x01000000
|
#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
|
#define ID_THOLD_INT_EN_SFT 24
|
#define ID_THOLD_INT_EN_HI 24
|
#define ID_THOLD_INT_EN_SZ 1
|
#define TX_ID_TB0_MSK 0xffffffff
|
#define TX_ID_TB0_I_MSK 0x00000000
|
#define TX_ID_TB0_SFT 0
|
#define TX_ID_TB0_HI 31
|
#define TX_ID_TB0_SZ 32
|
#define TX_ID_TB1_MSK 0xffffffff
|
#define TX_ID_TB1_I_MSK 0x00000000
|
#define TX_ID_TB1_SFT 0
|
#define TX_ID_TB1_HI 31
|
#define TX_ID_TB1_SZ 32
|
#define RX_ID_TB0_MSK 0xffffffff
|
#define RX_ID_TB0_I_MSK 0x00000000
|
#define RX_ID_TB0_SFT 0
|
#define RX_ID_TB0_HI 31
|
#define RX_ID_TB0_SZ 32
|
#define RX_ID_TB1_MSK 0xffffffff
|
#define RX_ID_TB1_I_MSK 0x00000000
|
#define RX_ID_TB1_SFT 0
|
#define RX_ID_TB1_HI 31
|
#define RX_ID_TB1_SZ 32
|
#define DOUBLE_RLS_INT_EN_MSK 0x00000001
|
#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
|
#define DOUBLE_RLS_INT_EN_SFT 0
|
#define DOUBLE_RLS_INT_EN_HI 0
|
#define DOUBLE_RLS_INT_EN_SZ 1
|
#define ID_DOUBLE_RLS_INT_MSK 0x00000002
|
#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
|
#define ID_DOUBLE_RLS_INT_SFT 1
|
#define ID_DOUBLE_RLS_INT_HI 1
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#define ID_DOUBLE_RLS_INT_SZ 1
|
#define DOUBLE_RLS_ID_MSK 0x00007f00
|
#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
|
#define DOUBLE_RLS_ID_SFT 8
|
#define DOUBLE_RLS_ID_HI 14
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#define DOUBLE_RLS_ID_SZ 7
|
#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
|
#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
|
#define ID_LEN_THOLD_INT_EN_SFT 0
|
#define ID_LEN_THOLD_INT_EN_HI 0
|
#define ID_LEN_THOLD_INT_EN_SZ 1
|
#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
|
#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
|
#define ALL_ID_LEN_THOLD_INT_SFT 1
|
#define ALL_ID_LEN_THOLD_INT_HI 1
|
#define ALL_ID_LEN_THOLD_INT_SZ 1
|
#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
|
#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
|
#define TX_ID_LEN_THOLD_INT_SFT 2
|
#define TX_ID_LEN_THOLD_INT_HI 2
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#define TX_ID_LEN_THOLD_INT_SZ 1
|
#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
|
#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
|
#define RX_ID_LEN_THOLD_INT_SFT 3
|
#define RX_ID_LEN_THOLD_INT_HI 3
|
#define RX_ID_LEN_THOLD_INT_SZ 1
|
#define ID_TX_LEN_THOLD_MSK 0x00001ff0
|
#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
|
#define ID_TX_LEN_THOLD_SFT 4
|
#define ID_TX_LEN_THOLD_HI 12
|
#define ID_TX_LEN_THOLD_SZ 9
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#define ID_RX_LEN_THOLD_MSK 0x003fe000
|
#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
|
#define ID_RX_LEN_THOLD_SFT 13
|
#define ID_RX_LEN_THOLD_HI 21
|
#define ID_RX_LEN_THOLD_SZ 9
|
#define ID_LEN_THOLD_MSK 0x7fc00000
|
#define ID_LEN_THOLD_I_MSK 0x803fffff
|
#define ID_LEN_THOLD_SFT 22
|
#define ID_LEN_THOLD_HI 30
|
#define ID_LEN_THOLD_SZ 9
|
#define ALL_ID_ALC_LEN_MSK 0x000001ff
|
#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
|
#define ALL_ID_ALC_LEN_SFT 0
|
#define ALL_ID_ALC_LEN_HI 8
|
#define ALL_ID_ALC_LEN_SZ 9
|
#define TX_ID_ALC_LEN_MSK 0x0003fe00
|
#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
|
#define TX_ID_ALC_LEN_SFT 9
|
#define TX_ID_ALC_LEN_HI 17
|
#define TX_ID_ALC_LEN_SZ 9
|
#define RX_ID_ALC_LEN_MSK 0x07fc0000
|
#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
|
#define RX_ID_ALC_LEN_SFT 18
|
#define RX_ID_ALC_LEN_HI 26
|
#define RX_ID_ALC_LEN_SZ 9
|
#define CH_ARB_EN_MSK 0x00000001
|
#define CH_ARB_EN_I_MSK 0xfffffffe
|
#define CH_ARB_EN_SFT 0
|
#define CH_ARB_EN_HI 0
|
#define CH_ARB_EN_SZ 1
|
#define CH_PRI1_MSK 0x00000030
|
#define CH_PRI1_I_MSK 0xffffffcf
|
#define CH_PRI1_SFT 4
|
#define CH_PRI1_HI 5
|
#define CH_PRI1_SZ 2
|
#define CH_PRI2_MSK 0x00000300
|
#define CH_PRI2_I_MSK 0xfffffcff
|
#define CH_PRI2_SFT 8
|
#define CH_PRI2_HI 9
|
#define CH_PRI2_SZ 2
|
#define CH_PRI3_MSK 0x00003000
|
#define CH_PRI3_I_MSK 0xffffcfff
|
#define CH_PRI3_SFT 12
|
#define CH_PRI3_HI 13
|
#define CH_PRI3_SZ 2
|
#define CH_PRI4_MSK 0x00030000
|
#define CH_PRI4_I_MSK 0xfffcffff
|
#define CH_PRI4_SFT 16
|
#define CH_PRI4_HI 17
|
#define CH_PRI4_SZ 2
|
#define TX_ID_REMAIN_MSK 0x0000007f
|
#define TX_ID_REMAIN_I_MSK 0xffffff80
|
#define TX_ID_REMAIN_SFT 0
|
#define TX_ID_REMAIN_HI 6
|
#define TX_ID_REMAIN_SZ 7
|
#define TX_PAGE_REMAIN_MSK 0x0001ff00
|
#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
|
#define TX_PAGE_REMAIN_SFT 8
|
#define TX_PAGE_REMAIN_HI 16
|
#define TX_PAGE_REMAIN_SZ 9
|
#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
|
#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
|
#define ID_PAGE_MAX_SIZE_SFT 0
|
#define ID_PAGE_MAX_SIZE_HI 8
|
#define ID_PAGE_MAX_SIZE_SZ 9
|
#define TX_PAGE_LIMIT_MSK 0x000001ff
|
#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
|
#define TX_PAGE_LIMIT_SFT 0
|
#define TX_PAGE_LIMIT_HI 8
|
#define TX_PAGE_LIMIT_SZ 9
|
#define TX_COUNT_LIMIT_MSK 0x00ff0000
|
#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
|
#define TX_COUNT_LIMIT_SFT 16
|
#define TX_COUNT_LIMIT_HI 23
|
#define TX_COUNT_LIMIT_SZ 8
|
#define TX_LIMIT_INT_MSK 0x40000000
|
#define TX_LIMIT_INT_I_MSK 0xbfffffff
|
#define TX_LIMIT_INT_SFT 30
|
#define TX_LIMIT_INT_HI 30
|
#define TX_LIMIT_INT_SZ 1
|
#define TX_LIMIT_INT_EN_MSK 0x80000000
|
#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
|
#define TX_LIMIT_INT_EN_SFT 31
|
#define TX_LIMIT_INT_EN_HI 31
|
#define TX_LIMIT_INT_EN_SZ 1
|
#define TX_PAGE_USE_7_0_MSK 0x000000ff
|
#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
|
#define TX_PAGE_USE_7_0_SFT 0
|
#define TX_PAGE_USE_7_0_HI 7
|
#define TX_PAGE_USE_7_0_SZ 8
|
#define TX_ID_USE_5_0_MSK 0x00003f00
|
#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
|
#define TX_ID_USE_5_0_SFT 8
|
#define TX_ID_USE_5_0_HI 13
|
#define TX_ID_USE_5_0_SZ 6
|
#define EDCA0_FFO_CNT_MSK 0x0003c000
|
#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
|
#define EDCA0_FFO_CNT_SFT 14
|
#define EDCA0_FFO_CNT_HI 17
|
#define EDCA0_FFO_CNT_SZ 4
|
#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
|
#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
|
#define EDCA1_FFO_CNT_3_0_SFT 18
|
#define EDCA1_FFO_CNT_3_0_HI 21
|
#define EDCA1_FFO_CNT_3_0_SZ 4
|
#define EDCA2_FFO_CNT_MSK 0x07c00000
|
#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
|
#define EDCA2_FFO_CNT_SFT 22
|
#define EDCA2_FFO_CNT_HI 26
|
#define EDCA2_FFO_CNT_SZ 5
|
#define EDCA3_FFO_CNT_MSK 0xf8000000
|
#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
|
#define EDCA3_FFO_CNT_SFT 27
|
#define EDCA3_FFO_CNT_HI 31
|
#define EDCA3_FFO_CNT_SZ 5
|
#define ID_TB2_MSK 0xffffffff
|
#define ID_TB2_I_MSK 0x00000000
|
#define ID_TB2_SFT 0
|
#define ID_TB2_HI 31
|
#define ID_TB2_SZ 32
|
#define ID_TB3_MSK 0xffffffff
|
#define ID_TB3_I_MSK 0x00000000
|
#define ID_TB3_SFT 0
|
#define ID_TB3_HI 31
|
#define ID_TB3_SZ 32
|
#define TX_ID_TB2_MSK 0xffffffff
|
#define TX_ID_TB2_I_MSK 0x00000000
|
#define TX_ID_TB2_SFT 0
|
#define TX_ID_TB2_HI 31
|
#define TX_ID_TB2_SZ 32
|
#define TX_ID_TB3_MSK 0xffffffff
|
#define TX_ID_TB3_I_MSK 0x00000000
|
#define TX_ID_TB3_SFT 0
|
#define TX_ID_TB3_HI 31
|
#define TX_ID_TB3_SZ 32
|
#define RX_ID_TB2_MSK 0xffffffff
|
#define RX_ID_TB2_I_MSK 0x00000000
|
#define RX_ID_TB2_SFT 0
|
#define RX_ID_TB2_HI 31
|
#define RX_ID_TB2_SZ 32
|
#define RX_ID_TB3_MSK 0xffffffff
|
#define RX_ID_TB3_I_MSK 0x00000000
|
#define RX_ID_TB3_SFT 0
|
#define RX_ID_TB3_HI 31
|
#define RX_ID_TB3_SZ 32
|
#define TX_PAGE_USE2_MSK 0x000001ff
|
#define TX_PAGE_USE2_I_MSK 0xfffffe00
|
#define TX_PAGE_USE2_SFT 0
|
#define TX_PAGE_USE2_HI 8
|
#define TX_PAGE_USE2_SZ 9
|
#define TX_ID_USE2_MSK 0x0001fe00
|
#define TX_ID_USE2_I_MSK 0xfffe01ff
|
#define TX_ID_USE2_SFT 9
|
#define TX_ID_USE2_HI 16
|
#define TX_ID_USE2_SZ 8
|
#define EDCA4_FFO_CNT_MSK 0x001e0000
|
#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
|
#define EDCA4_FFO_CNT_SFT 17
|
#define EDCA4_FFO_CNT_HI 20
|
#define EDCA4_FFO_CNT_SZ 4
|
#define TX_PAGE_USE3_MSK 0x000001ff
|
#define TX_PAGE_USE3_I_MSK 0xfffffe00
|
#define TX_PAGE_USE3_SFT 0
|
#define TX_PAGE_USE3_HI 8
|
#define TX_PAGE_USE3_SZ 9
|
#define TX_ID_USE3_MSK 0x0001fe00
|
#define TX_ID_USE3_I_MSK 0xfffe01ff
|
#define TX_ID_USE3_SFT 9
|
#define TX_ID_USE3_HI 16
|
#define TX_ID_USE3_SZ 8
|
#define EDCA1_FFO_CNT2_MSK 0x03e00000
|
#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
|
#define EDCA1_FFO_CNT2_SFT 21
|
#define EDCA1_FFO_CNT2_HI 25
|
#define EDCA1_FFO_CNT2_SZ 5
|
#define EDCA4_FFO_CNT2_MSK 0x3c000000
|
#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
|
#define EDCA4_FFO_CNT2_SFT 26
|
#define EDCA4_FFO_CNT2_HI 29
|
#define EDCA4_FFO_CNT2_SZ 4
|
#define TX_PAGE_USE4_MSK 0x000001ff
|
#define TX_PAGE_USE4_I_MSK 0xfffffe00
|
#define TX_PAGE_USE4_SFT 0
|
#define TX_PAGE_USE4_HI 8
|
#define TX_PAGE_USE4_SZ 9
|
#define TX_ID_USE4_MSK 0x0001fe00
|
#define TX_ID_USE4_I_MSK 0xfffe01ff
|
#define TX_ID_USE4_SFT 9
|
#define TX_ID_USE4_HI 16
|
#define TX_ID_USE4_SZ 8
|
#define EDCA2_FFO_CNT2_MSK 0x003e0000
|
#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
|
#define EDCA2_FFO_CNT2_SFT 17
|
#define EDCA2_FFO_CNT2_HI 21
|
#define EDCA2_FFO_CNT2_SZ 5
|
#define EDCA3_FFO_CNT2_MSK 0x07c00000
|
#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
|
#define EDCA3_FFO_CNT2_SFT 22
|
#define EDCA3_FFO_CNT2_HI 26
|
#define EDCA3_FFO_CNT2_SZ 5
|
#define TX_ID_IFO_LEN_MSK 0x000001ff
|
#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
|
#define TX_ID_IFO_LEN_SFT 0
|
#define TX_ID_IFO_LEN_HI 8
|
#define TX_ID_IFO_LEN_SZ 9
|
#define RX_ID_IFO_LEN_MSK 0x01ff0000
|
#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
|
#define RX_ID_IFO_LEN_SFT 16
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#define RX_ID_IFO_LEN_HI 24
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#define RX_ID_IFO_LEN_SZ 9
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#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
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#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
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#define MAX_ALL_ALC_ID_CNT_SFT 0
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#define MAX_ALL_ALC_ID_CNT_HI 7
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#define MAX_ALL_ALC_ID_CNT_SZ 8
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#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
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#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
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#define MAX_TX_ALC_ID_CNT_SFT 8
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#define MAX_TX_ALC_ID_CNT_HI 15
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#define MAX_TX_ALC_ID_CNT_SZ 8
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#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
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#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
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#define MAX_RX_ALC_ID_CNT_SFT 16
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#define MAX_RX_ALC_ID_CNT_HI 23
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#define MAX_RX_ALC_ID_CNT_SZ 8
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#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
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#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
|
#define MAX_ALL_ID_ALC_LEN_SFT 0
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#define MAX_ALL_ID_ALC_LEN_HI 8
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#define MAX_ALL_ID_ALC_LEN_SZ 9
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#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
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#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
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#define MAX_TX_ID_ALC_LEN_SFT 9
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#define MAX_TX_ID_ALC_LEN_HI 17
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#define MAX_TX_ID_ALC_LEN_SZ 9
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#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
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#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
|
#define MAX_RX_ID_ALC_LEN_SFT 18
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#define MAX_RX_ID_ALC_LEN_HI 26
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#define MAX_RX_ID_ALC_LEN_SZ 9
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#define RG_PMDLBK_MSK 0x00000001
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#define RG_PMDLBK_I_MSK 0xfffffffe
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#define RG_PMDLBK_SFT 0
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#define RG_PMDLBK_HI 0
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#define RG_PMDLBK_SZ 1
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#define RG_RDYACK_SEL_MSK 0x00000006
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#define RG_RDYACK_SEL_I_MSK 0xfffffff9
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#define RG_RDYACK_SEL_SFT 1
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#define RG_RDYACK_SEL_HI 2
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#define RG_RDYACK_SEL_SZ 2
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#define RG_ADEDGE_SEL_MSK 0x00000008
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#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
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#define RG_ADEDGE_SEL_SFT 3
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#define RG_ADEDGE_SEL_HI 3
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#define RG_ADEDGE_SEL_SZ 1
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#define RG_SIGN_SWAP_MSK 0x00000010
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#define RG_SIGN_SWAP_I_MSK 0xffffffef
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#define RG_SIGN_SWAP_SFT 4
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#define RG_SIGN_SWAP_HI 4
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#define RG_SIGN_SWAP_SZ 1
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#define RG_IQ_SWAP_MSK 0x00000020
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#define RG_IQ_SWAP_I_MSK 0xffffffdf
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#define RG_IQ_SWAP_SFT 5
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#define RG_IQ_SWAP_HI 5
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#define RG_IQ_SWAP_SZ 1
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#define RG_Q_INV_MSK 0x00000040
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#define RG_Q_INV_I_MSK 0xffffffbf
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#define RG_Q_INV_SFT 6
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#define RG_Q_INV_HI 6
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#define RG_Q_INV_SZ 1
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#define RG_I_INV_MSK 0x00000080
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#define RG_I_INV_I_MSK 0xffffff7f
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#define RG_I_INV_SFT 7
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#define RG_I_INV_HI 7
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#define RG_I_INV_SZ 1
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#define RG_BYPASS_ACI_MSK 0x00000100
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#define RG_BYPASS_ACI_I_MSK 0xfffffeff
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#define RG_BYPASS_ACI_SFT 8
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#define RG_BYPASS_ACI_HI 8
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#define RG_BYPASS_ACI_SZ 1
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#define RG_LBK_ANA_PATH_MSK 0x00000200
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#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
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#define RG_LBK_ANA_PATH_SFT 9
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#define RG_LBK_ANA_PATH_HI 9
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#define RG_LBK_ANA_PATH_SZ 1
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#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
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#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
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#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
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#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
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#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
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#define RG_SPECTRUM_BW_MSK 0x00003000
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#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
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#define RG_SPECTRUM_BW_SFT 12
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#define RG_SPECTRUM_BW_HI 13
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#define RG_SPECTRUM_BW_SZ 2
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#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
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#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
|
#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
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#define RG_SPECTRUM_FREQ_MANUAL_HI 14
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#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
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#define RG_SPECTRUM_EN_MSK 0x00008000
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#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
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#define RG_SPECTRUM_EN_SFT 15
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#define RG_SPECTRUM_EN_HI 15
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#define RG_SPECTRUM_EN_SZ 1
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#define RG_TXPWRLVL_SET_MSK 0x00ff0000
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#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
|
#define RG_TXPWRLVL_SET_SFT 16
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#define RG_TXPWRLVL_SET_HI 23
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#define RG_TXPWRLVL_SET_SZ 8
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#define RG_TXPWRLVL_SEL_MSK 0x01000000
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#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
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#define RG_TXPWRLVL_SEL_SFT 24
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#define RG_TXPWRLVL_SEL_HI 24
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#define RG_TXPWRLVL_SEL_SZ 1
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#define RG_RF_BB_CLK_SEL_MSK 0x80000000
|
#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
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#define RG_RF_BB_CLK_SEL_SFT 31
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#define RG_RF_BB_CLK_SEL_HI 31
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#define RG_RF_BB_CLK_SEL_SZ 1
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#define RG_PHY_MD_EN_MSK 0x00000001
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#define RG_PHY_MD_EN_I_MSK 0xfffffffe
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#define RG_PHY_MD_EN_SFT 0
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#define RG_PHY_MD_EN_HI 0
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#define RG_PHY_MD_EN_SZ 1
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#define RG_PHYRX_MD_EN_MSK 0x00000002
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#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
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#define RG_PHYRX_MD_EN_SFT 1
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#define RG_PHYRX_MD_EN_HI 1
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#define RG_PHYRX_MD_EN_SZ 1
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#define RG_PHYTX_MD_EN_MSK 0x00000004
|
#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
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#define RG_PHYTX_MD_EN_SFT 2
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#define RG_PHYTX_MD_EN_HI 2
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#define RG_PHYTX_MD_EN_SZ 1
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#define RG_PHY11GN_MD_EN_MSK 0x00000008
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#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
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#define RG_PHY11GN_MD_EN_SFT 3
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#define RG_PHY11GN_MD_EN_HI 3
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#define RG_PHY11GN_MD_EN_SZ 1
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#define RG_PHY11B_MD_EN_MSK 0x00000010
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#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
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#define RG_PHY11B_MD_EN_SFT 4
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#define RG_PHY11B_MD_EN_HI 4
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#define RG_PHY11B_MD_EN_SZ 1
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#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
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#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
|
#define RG_PHYRXFIFO_MD_EN_SFT 5
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#define RG_PHYRXFIFO_MD_EN_HI 5
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#define RG_PHYRXFIFO_MD_EN_SZ 1
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#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
|
#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
|
#define RG_PHYTXFIFO_MD_EN_SFT 6
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#define RG_PHYTXFIFO_MD_EN_HI 6
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#define RG_PHYTXFIFO_MD_EN_SZ 1
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#define RG_PHY11BGN_MD_EN_MSK 0x00000100
|
#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
|
#define RG_PHY11BGN_MD_EN_SFT 8
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#define RG_PHY11BGN_MD_EN_HI 8
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#define RG_PHY11BGN_MD_EN_SZ 1
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#define RG_FORCE_11GN_EN_MSK 0x00001000
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#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
|
#define RG_FORCE_11GN_EN_SFT 12
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#define RG_FORCE_11GN_EN_HI 12
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#define RG_FORCE_11GN_EN_SZ 1
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#define RG_FORCE_11B_EN_MSK 0x00002000
|
#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
|
#define RG_FORCE_11B_EN_SFT 13
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#define RG_FORCE_11B_EN_HI 13
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#define RG_FORCE_11B_EN_SZ 1
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#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
|
#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
|
#define RG_FFT_MEM_CLK_EN_RX_SFT 14
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#define RG_FFT_MEM_CLK_EN_RX_HI 14
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#define RG_FFT_MEM_CLK_EN_RX_SZ 1
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#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
|
#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
|
#define RG_FFT_MEM_CLK_EN_TX_SFT 15
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#define RG_FFT_MEM_CLK_EN_TX_HI 15
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#define RG_FFT_MEM_CLK_EN_TX_SZ 1
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#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
|
#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
|
#define RG_PHY_IQ_TRIG_SEL_SFT 16
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#define RG_PHY_IQ_TRIG_SEL_HI 19
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#define RG_PHY_IQ_TRIG_SEL_SZ 4
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#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
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#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
|
#define RG_SPECTRUM_FREQ_SFT 20
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#define RG_SPECTRUM_FREQ_HI 29
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#define RG_SPECTRUM_FREQ_SZ 10
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#define SVN_VERSION_MSK 0xffffffff
|
#define SVN_VERSION_I_MSK 0x00000000
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#define SVN_VERSION_SFT 0
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#define SVN_VERSION_HI 31
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#define SVN_VERSION_SZ 32
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#define RG_LENGTH_MSK 0x0000ffff
|
#define RG_LENGTH_I_MSK 0xffff0000
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#define RG_LENGTH_SFT 0
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#define RG_LENGTH_HI 15
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#define RG_LENGTH_SZ 16
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#define RG_PKT_MODE_MSK 0x00070000
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#define RG_PKT_MODE_I_MSK 0xfff8ffff
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#define RG_PKT_MODE_SFT 16
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#define RG_PKT_MODE_HI 18
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#define RG_PKT_MODE_SZ 3
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#define RG_CH_BW_MSK 0x00380000
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#define RG_CH_BW_I_MSK 0xffc7ffff
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#define RG_CH_BW_SFT 19
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#define RG_CH_BW_HI 21
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#define RG_CH_BW_SZ 3
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#define RG_PRM_MSK 0x00400000
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#define RG_PRM_I_MSK 0xffbfffff
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#define RG_PRM_SFT 22
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#define RG_PRM_HI 22
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#define RG_PRM_SZ 1
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#define RG_SHORTGI_MSK 0x00800000
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#define RG_SHORTGI_I_MSK 0xff7fffff
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#define RG_SHORTGI_SFT 23
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#define RG_SHORTGI_HI 23
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#define RG_SHORTGI_SZ 1
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#define RG_RATE_MSK 0x7f000000
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#define RG_RATE_I_MSK 0x80ffffff
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#define RG_RATE_SFT 24
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#define RG_RATE_HI 30
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#define RG_RATE_SZ 7
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#define RG_L_LENGTH_MSK 0x00000fff
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#define RG_L_LENGTH_I_MSK 0xfffff000
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#define RG_L_LENGTH_SFT 0
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#define RG_L_LENGTH_HI 11
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#define RG_L_LENGTH_SZ 12
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#define RG_L_RATE_MSK 0x00007000
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#define RG_L_RATE_I_MSK 0xffff8fff
|
#define RG_L_RATE_SFT 12
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#define RG_L_RATE_HI 14
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#define RG_L_RATE_SZ 3
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#define RG_SERVICE_MSK 0xffff0000
|
#define RG_SERVICE_I_MSK 0x0000ffff
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#define RG_SERVICE_SFT 16
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#define RG_SERVICE_HI 31
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#define RG_SERVICE_SZ 16
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#define RG_SMOOTHING_MSK 0x00000001
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#define RG_SMOOTHING_I_MSK 0xfffffffe
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#define RG_SMOOTHING_SFT 0
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#define RG_SMOOTHING_HI 0
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#define RG_SMOOTHING_SZ 1
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#define RG_NO_SOUND_MSK 0x00000002
|
#define RG_NO_SOUND_I_MSK 0xfffffffd
|
#define RG_NO_SOUND_SFT 1
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#define RG_NO_SOUND_HI 1
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#define RG_NO_SOUND_SZ 1
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#define RG_AGGREGATE_MSK 0x00000004
|
#define RG_AGGREGATE_I_MSK 0xfffffffb
|
#define RG_AGGREGATE_SFT 2
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#define RG_AGGREGATE_HI 2
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#define RG_AGGREGATE_SZ 1
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#define RG_STBC_MSK 0x00000018
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#define RG_STBC_I_MSK 0xffffffe7
|
#define RG_STBC_SFT 3
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#define RG_STBC_HI 4
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#define RG_STBC_SZ 2
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#define RG_FEC_MSK 0x00000020
|
#define RG_FEC_I_MSK 0xffffffdf
|
#define RG_FEC_SFT 5
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#define RG_FEC_HI 5
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#define RG_FEC_SZ 1
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#define RG_N_ESS_MSK 0x000000c0
|
#define RG_N_ESS_I_MSK 0xffffff3f
|
#define RG_N_ESS_SFT 6
|
#define RG_N_ESS_HI 7
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#define RG_N_ESS_SZ 2
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#define RG_TXPWRLVL_MSK 0x0000ff00
|
#define RG_TXPWRLVL_I_MSK 0xffff00ff
|
#define RG_TXPWRLVL_SFT 8
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#define RG_TXPWRLVL_HI 15
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#define RG_TXPWRLVL_SZ 8
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#define RG_TX_START_MSK 0x00000001
|
#define RG_TX_START_I_MSK 0xfffffffe
|
#define RG_TX_START_SFT 0
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#define RG_TX_START_HI 0
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#define RG_TX_START_SZ 1
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#define RG_IFS_TIME_MSK 0x000000fc
|
#define RG_IFS_TIME_I_MSK 0xffffff03
|
#define RG_IFS_TIME_SFT 2
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#define RG_IFS_TIME_HI 7
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#define RG_IFS_TIME_SZ 6
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#define RG_CONTINUOUS_DATA_MSK 0x00000100
|
#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
|
#define RG_CONTINUOUS_DATA_SFT 8
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#define RG_CONTINUOUS_DATA_HI 8
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#define RG_CONTINUOUS_DATA_SZ 1
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#define RG_DATA_SEL_MSK 0x00000600
|
#define RG_DATA_SEL_I_MSK 0xfffff9ff
|
#define RG_DATA_SEL_SFT 9
|
#define RG_DATA_SEL_HI 10
|
#define RG_DATA_SEL_SZ 2
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#define RG_TX_D_MSK 0x00ff0000
|
#define RG_TX_D_I_MSK 0xff00ffff
|
#define RG_TX_D_SFT 16
|
#define RG_TX_D_HI 23
|
#define RG_TX_D_SZ 8
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#define RG_TX_CNT_TARGET_MSK 0xffffffff
|
#define RG_TX_CNT_TARGET_I_MSK 0x00000000
|
#define RG_TX_CNT_TARGET_SFT 0
|
#define RG_TX_CNT_TARGET_HI 31
|
#define RG_TX_CNT_TARGET_SZ 32
|
#define RG_FFT_IFFT_MODE_MSK 0x000000c0
|
#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
|
#define RG_FFT_IFFT_MODE_SFT 6
|
#define RG_FFT_IFFT_MODE_HI 7
|
#define RG_FFT_IFFT_MODE_SZ 2
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#define RG_DAC_DBG_MODE_MSK 0x00000100
|
#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
|
#define RG_DAC_DBG_MODE_SFT 8
|
#define RG_DAC_DBG_MODE_HI 8
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#define RG_DAC_DBG_MODE_SZ 1
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#define RG_DAC_SGN_SWAP_MSK 0x00000200
|
#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
|
#define RG_DAC_SGN_SWAP_SFT 9
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#define RG_DAC_SGN_SWAP_HI 9
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#define RG_DAC_SGN_SWAP_SZ 1
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#define RG_TXD_SEL_MSK 0x00000c00
|
#define RG_TXD_SEL_I_MSK 0xfffff3ff
|
#define RG_TXD_SEL_SFT 10
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#define RG_TXD_SEL_HI 11
|
#define RG_TXD_SEL_SZ 2
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#define RG_UP8X_MSK 0x00ff0000
|
#define RG_UP8X_I_MSK 0xff00ffff
|
#define RG_UP8X_SFT 16
|
#define RG_UP8X_HI 23
|
#define RG_UP8X_SZ 8
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#define RG_IQ_DC_BYP_MSK 0x01000000
|
#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
|
#define RG_IQ_DC_BYP_SFT 24
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#define RG_IQ_DC_BYP_HI 24
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#define RG_IQ_DC_BYP_SZ 1
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#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
|
#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
|
#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
|
#define RG_IQ_DC_LEAKY_FACTOR_HI 29
|
#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
|
#define RG_DAC_DCEN_MSK 0x00000001
|
#define RG_DAC_DCEN_I_MSK 0xfffffffe
|
#define RG_DAC_DCEN_SFT 0
|
#define RG_DAC_DCEN_HI 0
|
#define RG_DAC_DCEN_SZ 1
|
#define RG_DAC_DCQ_MSK 0x00003ff0
|
#define RG_DAC_DCQ_I_MSK 0xffffc00f
|
#define RG_DAC_DCQ_SFT 4
|
#define RG_DAC_DCQ_HI 13
|
#define RG_DAC_DCQ_SZ 10
|
#define RG_DAC_DCI_MSK 0x03ff0000
|
#define RG_DAC_DCI_I_MSK 0xfc00ffff
|
#define RG_DAC_DCI_SFT 16
|
#define RG_DAC_DCI_HI 25
|
#define RG_DAC_DCI_SZ 10
|
#define RG_PGA_REFDB_SAT_MSK 0x0000007f
|
#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
|
#define RG_PGA_REFDB_SAT_SFT 0
|
#define RG_PGA_REFDB_SAT_HI 6
|
#define RG_PGA_REFDB_SAT_SZ 7
|
#define RG_PGA_REFDB_TOP_MSK 0x00007f00
|
#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
|
#define RG_PGA_REFDB_TOP_SFT 8
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#define RG_PGA_REFDB_TOP_HI 14
|
#define RG_PGA_REFDB_TOP_SZ 7
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#define RG_PGA_REF_UND_MSK 0x03ff0000
|
#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
|
#define RG_PGA_REF_UND_SFT 16
|
#define RG_PGA_REF_UND_HI 25
|
#define RG_PGA_REF_UND_SZ 10
|
#define RG_RF_REF_SAT_MSK 0xf0000000
|
#define RG_RF_REF_SAT_I_MSK 0x0fffffff
|
#define RG_RF_REF_SAT_SFT 28
|
#define RG_RF_REF_SAT_HI 31
|
#define RG_RF_REF_SAT_SZ 4
|
#define RG_PGAGC_SET_MSK 0x0000000f
|
#define RG_PGAGC_SET_I_MSK 0xfffffff0
|
#define RG_PGAGC_SET_SFT 0
|
#define RG_PGAGC_SET_HI 3
|
#define RG_PGAGC_SET_SZ 4
|
#define RG_PGAGC_OW_MSK 0x00000010
|
#define RG_PGAGC_OW_I_MSK 0xffffffef
|
#define RG_PGAGC_OW_SFT 4
|
#define RG_PGAGC_OW_HI 4
|
#define RG_PGAGC_OW_SZ 1
|
#define RG_RFGC_SET_MSK 0x00000060
|
#define RG_RFGC_SET_I_MSK 0xffffff9f
|
#define RG_RFGC_SET_SFT 5
|
#define RG_RFGC_SET_HI 6
|
#define RG_RFGC_SET_SZ 2
|
#define RG_RFGC_OW_MSK 0x00000080
|
#define RG_RFGC_OW_I_MSK 0xffffff7f
|
#define RG_RFGC_OW_SFT 7
|
#define RG_RFGC_OW_HI 7
|
#define RG_RFGC_OW_SZ 1
|
#define RG_WAIT_T_RXAGC_MSK 0x00003f00
|
#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
|
#define RG_WAIT_T_RXAGC_SFT 8
|
#define RG_WAIT_T_RXAGC_HI 13
|
#define RG_WAIT_T_RXAGC_SZ 6
|
#define RG_RXAGC_SET_MSK 0x00004000
|
#define RG_RXAGC_SET_I_MSK 0xffffbfff
|
#define RG_RXAGC_SET_SFT 14
|
#define RG_RXAGC_SET_HI 14
|
#define RG_RXAGC_SET_SZ 1
|
#define RG_RXAGC_OW_MSK 0x00008000
|
#define RG_RXAGC_OW_I_MSK 0xffff7fff
|
#define RG_RXAGC_OW_SFT 15
|
#define RG_RXAGC_OW_HI 15
|
#define RG_RXAGC_OW_SZ 1
|
#define RG_WAIT_T_FINAL_MSK 0x003f0000
|
#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
|
#define RG_WAIT_T_FINAL_SFT 16
|
#define RG_WAIT_T_FINAL_HI 21
|
#define RG_WAIT_T_FINAL_SZ 6
|
#define RG_WAIT_T_MSK 0x3f000000
|
#define RG_WAIT_T_I_MSK 0xc0ffffff
|
#define RG_WAIT_T_SFT 24
|
#define RG_WAIT_T_HI 29
|
#define RG_WAIT_T_SZ 6
|
#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
|
#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
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#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
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#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
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#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
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#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
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#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
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#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
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#define RG_LG_PGA_UND_PGA_GAIN_HI 7
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#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
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#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
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#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
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#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
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#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
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#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
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#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
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#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
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#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
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#define RG_LG_RF_SAT_PGA_GAIN_HI 15
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#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
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#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
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#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
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#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
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#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
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#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
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#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
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#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
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#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
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#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
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#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
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#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
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#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
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#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
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#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
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#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
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#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
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#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
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#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
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#define RG_HG_RF_SAT_PGA_GAIN_HI 31
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#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
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#define RG_MG_PGA_JB_TH_MSK 0x0000000f
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#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
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#define RG_MG_PGA_JB_TH_SFT 0
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#define RG_MG_PGA_JB_TH_HI 3
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#define RG_MG_PGA_JB_TH_SZ 4
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#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
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#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
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#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
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#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
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#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
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#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
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#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
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#define RG_WR_RFGC_INIT_SET_SFT 21
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#define RG_WR_RFGC_INIT_SET_HI 22
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#define RG_WR_RFGC_INIT_SET_SZ 2
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#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
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#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
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#define RG_WR_RFGC_INIT_EN_SFT 23
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#define RG_WR_RFGC_INIT_EN_HI 23
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#define RG_WR_RFGC_INIT_EN_SZ 1
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#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
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#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
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#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
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#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
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#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
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#define RG_AGC_THRESHOLD_MSK 0x00003fff
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#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
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#define RG_AGC_THRESHOLD_SFT 0
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#define RG_AGC_THRESHOLD_HI 13
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#define RG_AGC_THRESHOLD_SZ 14
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#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
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#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
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#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
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#define RG_ACI_POINT_CNT_LMT_11B_HI 22
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#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
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#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
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#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
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#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
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#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
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#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
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#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
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#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
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#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
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#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
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#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
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#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
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#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
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#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
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#define RG_WR_ACI_GAIN_SEL_11B_HI 15
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#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
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#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
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#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
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#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
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#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
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#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
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#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
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#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
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#define RG_WR_ACI_GAIN_OW_11B_SFT 31
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#define RG_WR_ACI_GAIN_OW_11B_HI 31
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#define RG_WR_ACI_GAIN_OW_11B_SZ 1
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#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
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#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
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#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
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#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
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#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
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#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
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#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
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#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
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#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
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#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
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#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
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#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
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#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
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#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
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#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
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#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
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#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
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#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
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#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
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#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
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#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
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#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
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#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
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#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
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#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
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#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
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#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
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#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
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#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
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#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
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#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
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#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
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#define RG_ACI_GAIN_OW_11GN_SFT 31
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#define RG_ACI_GAIN_OW_11GN_HI 31
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#define RG_ACI_GAIN_OW_11GN_SZ 1
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#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
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#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
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#define RO_CCA_PWR_MA_11GN_SFT 0
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#define RO_CCA_PWR_MA_11GN_HI 6
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#define RO_CCA_PWR_MA_11GN_SZ 7
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#define RO_ED_STATE_MSK 0x00008000
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#define RO_ED_STATE_I_MSK 0xffff7fff
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#define RO_ED_STATE_SFT 15
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#define RO_ED_STATE_HI 15
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#define RO_ED_STATE_SZ 1
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#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
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#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
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#define RO_CCA_PWR_MA_11B_SFT 16
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#define RO_CCA_PWR_MA_11B_HI 22
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#define RO_CCA_PWR_MA_11B_SZ 7
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#define RO_PGA_PWR_FF1_MSK 0x00003fff
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#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
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#define RO_PGA_PWR_FF1_SFT 0
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#define RO_PGA_PWR_FF1_HI 13
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#define RO_PGA_PWR_FF1_SZ 14
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#define RO_RF_PWR_FF1_MSK 0x000f0000
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#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
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#define RO_RF_PWR_FF1_SFT 16
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#define RO_RF_PWR_FF1_HI 19
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#define RO_RF_PWR_FF1_SZ 4
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#define RO_PGAGC_FF1_MSK 0x0f000000
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#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
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#define RO_PGAGC_FF1_SFT 24
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#define RO_PGAGC_FF1_HI 27
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#define RO_PGAGC_FF1_SZ 4
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#define RO_RFGC_FF1_MSK 0x30000000
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#define RO_RFGC_FF1_I_MSK 0xcfffffff
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#define RO_RFGC_FF1_SFT 28
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#define RO_RFGC_FF1_HI 29
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#define RO_RFGC_FF1_SZ 2
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#define RO_PGA_PWR_FF2_MSK 0x00003fff
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#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
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#define RO_PGA_PWR_FF2_SFT 0
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#define RO_PGA_PWR_FF2_HI 13
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#define RO_PGA_PWR_FF2_SZ 14
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#define RO_RF_PWR_FF2_MSK 0x000f0000
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#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
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#define RO_RF_PWR_FF2_SFT 16
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#define RO_RF_PWR_FF2_HI 19
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#define RO_RF_PWR_FF2_SZ 4
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#define RO_PGAGC_FF2_MSK 0x0f000000
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#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
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#define RO_PGAGC_FF2_SFT 24
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#define RO_PGAGC_FF2_HI 27
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#define RO_PGAGC_FF2_SZ 4
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#define RO_RFGC_FF2_MSK 0x30000000
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#define RO_RFGC_FF2_I_MSK 0xcfffffff
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#define RO_RFGC_FF2_SFT 28
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#define RO_RFGC_FF2_HI 29
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#define RO_RFGC_FF2_SZ 2
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#define RO_PGA_PWR_FF3_MSK 0x00003fff
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#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
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#define RO_PGA_PWR_FF3_SFT 0
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#define RO_PGA_PWR_FF3_HI 13
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#define RO_PGA_PWR_FF3_SZ 14
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#define RO_RF_PWR_FF3_MSK 0x000f0000
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#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
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#define RO_RF_PWR_FF3_SFT 16
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#define RO_RF_PWR_FF3_HI 19
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#define RO_RF_PWR_FF3_SZ 4
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#define RO_PGAGC_FF3_MSK 0x0f000000
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#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
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#define RO_PGAGC_FF3_SFT 24
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#define RO_PGAGC_FF3_HI 27
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#define RO_PGAGC_FF3_SZ 4
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#define RO_RFGC_FF3_MSK 0x30000000
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#define RO_RFGC_FF3_I_MSK 0xcfffffff
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#define RO_RFGC_FF3_SFT 28
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#define RO_RFGC_FF3_HI 29
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#define RO_RFGC_FF3_SZ 2
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#define RG_TX_DES_RATE_MSK 0x0000001f
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#define RG_TX_DES_RATE_I_MSK 0xffffffe0
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#define RG_TX_DES_RATE_SFT 0
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#define RG_TX_DES_RATE_HI 4
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#define RG_TX_DES_RATE_SZ 5
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#define RG_TX_DES_MODE_MSK 0x00001f00
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#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
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#define RG_TX_DES_MODE_SFT 8
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#define RG_TX_DES_MODE_HI 12
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#define RG_TX_DES_MODE_SZ 5
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#define RG_TX_DES_LEN_LO_MSK 0x001f0000
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#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
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#define RG_TX_DES_LEN_LO_SFT 16
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#define RG_TX_DES_LEN_LO_HI 20
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#define RG_TX_DES_LEN_LO_SZ 5
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#define RG_TX_DES_LEN_UP_MSK 0x1f000000
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#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
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#define RG_TX_DES_LEN_UP_SFT 24
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#define RG_TX_DES_LEN_UP_HI 28
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#define RG_TX_DES_LEN_UP_SZ 5
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#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
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#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
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#define RG_TX_DES_SRVC_UP_SFT 0
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#define RG_TX_DES_SRVC_UP_HI 4
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#define RG_TX_DES_SRVC_UP_SZ 5
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#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
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#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
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#define RG_TX_DES_L_LEN_LO_SFT 8
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#define RG_TX_DES_L_LEN_LO_HI 12
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#define RG_TX_DES_L_LEN_LO_SZ 5
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#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
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#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
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#define RG_TX_DES_L_LEN_UP_SFT 16
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#define RG_TX_DES_L_LEN_UP_HI 20
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#define RG_TX_DES_L_LEN_UP_SZ 5
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#define RG_TX_DES_TYPE_MSK 0x1f000000
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#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
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#define RG_TX_DES_TYPE_SFT 24
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#define RG_TX_DES_TYPE_HI 28
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#define RG_TX_DES_TYPE_SZ 5
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#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
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#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
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#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
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#define RG_TX_DES_L_LEN_UP_COMB_HI 0
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#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
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#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
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#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
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#define RG_TX_DES_TYPE_COMB_SFT 4
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#define RG_TX_DES_TYPE_COMB_HI 4
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#define RG_TX_DES_TYPE_COMB_SZ 1
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#define RG_TX_DES_RATE_COMB_MSK 0x00000100
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#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
|
#define RG_TX_DES_RATE_COMB_SFT 8
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#define RG_TX_DES_RATE_COMB_HI 8
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#define RG_TX_DES_RATE_COMB_SZ 1
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#define RG_TX_DES_MODE_COMB_MSK 0x00001000
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#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
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#define RG_TX_DES_MODE_COMB_SFT 12
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#define RG_TX_DES_MODE_COMB_HI 12
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#define RG_TX_DES_MODE_COMB_SZ 1
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#define RG_TX_DES_PWRLVL_MSK 0x001f0000
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#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
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#define RG_TX_DES_PWRLVL_SFT 16
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#define RG_TX_DES_PWRLVL_HI 20
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#define RG_TX_DES_PWRLVL_SZ 5
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#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
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#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
|
#define RG_TX_DES_SRVC_LO_SFT 24
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#define RG_TX_DES_SRVC_LO_HI 28
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#define RG_TX_DES_SRVC_LO_SZ 5
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#define RG_RX_DES_RATE_MSK 0x0000003f
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#define RG_RX_DES_RATE_I_MSK 0xffffffc0
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#define RG_RX_DES_RATE_SFT 0
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#define RG_RX_DES_RATE_HI 5
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#define RG_RX_DES_RATE_SZ 6
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#define RG_RX_DES_MODE_MSK 0x00003f00
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#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
|
#define RG_RX_DES_MODE_SFT 8
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#define RG_RX_DES_MODE_HI 13
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#define RG_RX_DES_MODE_SZ 6
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#define RG_RX_DES_LEN_LO_MSK 0x003f0000
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#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
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#define RG_RX_DES_LEN_LO_SFT 16
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#define RG_RX_DES_LEN_LO_HI 21
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#define RG_RX_DES_LEN_LO_SZ 6
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#define RG_RX_DES_LEN_UP_MSK 0x3f000000
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#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
|
#define RG_RX_DES_LEN_UP_SFT 24
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#define RG_RX_DES_LEN_UP_HI 29
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#define RG_RX_DES_LEN_UP_SZ 6
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#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
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#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
|
#define RG_RX_DES_SRVC_UP_SFT 0
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#define RG_RX_DES_SRVC_UP_HI 5
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#define RG_RX_DES_SRVC_UP_SZ 6
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#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
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#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
|
#define RG_RX_DES_L_LEN_LO_SFT 8
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#define RG_RX_DES_L_LEN_LO_HI 13
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#define RG_RX_DES_L_LEN_LO_SZ 6
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#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
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#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
|
#define RG_RX_DES_L_LEN_UP_SFT 16
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#define RG_RX_DES_L_LEN_UP_HI 21
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#define RG_RX_DES_L_LEN_UP_SZ 6
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#define RG_RX_DES_TYPE_MSK 0x3f000000
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#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
|
#define RG_RX_DES_TYPE_SFT 24
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#define RG_RX_DES_TYPE_HI 29
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#define RG_RX_DES_TYPE_SZ 6
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#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
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#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
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#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
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#define RG_RX_DES_L_LEN_UP_COMB_HI 0
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#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
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#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
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#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
|
#define RG_RX_DES_TYPE_COMB_SFT 4
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#define RG_RX_DES_TYPE_COMB_HI 4
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#define RG_RX_DES_TYPE_COMB_SZ 1
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#define RG_RX_DES_RATE_COMB_MSK 0x00000100
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#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
|
#define RG_RX_DES_RATE_COMB_SFT 8
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#define RG_RX_DES_RATE_COMB_HI 8
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#define RG_RX_DES_RATE_COMB_SZ 1
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#define RG_RX_DES_MODE_COMB_MSK 0x00001000
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#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
|
#define RG_RX_DES_MODE_COMB_SFT 12
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#define RG_RX_DES_MODE_COMB_HI 12
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#define RG_RX_DES_MODE_COMB_SZ 1
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#define RG_RX_DES_SNR_MSK 0x000f0000
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#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
|
#define RG_RX_DES_SNR_SFT 16
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#define RG_RX_DES_SNR_HI 19
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#define RG_RX_DES_SNR_SZ 4
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#define RG_RX_DES_RCPI_MSK 0x00f00000
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#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
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#define RG_RX_DES_RCPI_SFT 20
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#define RG_RX_DES_RCPI_HI 23
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#define RG_RX_DES_RCPI_SZ 4
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#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
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#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
|
#define RG_RX_DES_SRVC_LO_SFT 24
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#define RG_RX_DES_SRVC_LO_HI 29
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#define RG_RX_DES_SRVC_LO_SZ 6
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#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
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#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
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#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
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#define RO_TX_DES_EXCP_RATE_CNT_HI 7
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#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
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#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
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#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
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#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
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#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
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#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
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#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
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#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
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#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
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#define RO_TX_DES_EXCP_MODE_CNT_HI 23
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#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
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#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
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#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
|
#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
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#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
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#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
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#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
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#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
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#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
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#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
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#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
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#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
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#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
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#define RG_TX_DES_EXCP_CLR_SFT 31
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#define RG_TX_DES_EXCP_CLR_HI 31
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#define RG_TX_DES_EXCP_CLR_SZ 1
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#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
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#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
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#define RG_TX_DES_ACK_WIDTH_SFT 0
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#define RG_TX_DES_ACK_WIDTH_HI 0
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#define RG_TX_DES_ACK_WIDTH_SZ 1
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#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
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#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
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#define RG_TX_DES_ACK_PRD_SFT 1
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#define RG_TX_DES_ACK_PRD_HI 3
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#define RG_TX_DES_ACK_PRD_SZ 3
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#define RG_RX_DES_SNR_GN_MSK 0x003f0000
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#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
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#define RG_RX_DES_SNR_GN_SFT 16
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#define RG_RX_DES_SNR_GN_HI 21
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#define RG_RX_DES_SNR_GN_SZ 6
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#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
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#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
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#define RG_RX_DES_RCPI_GN_SFT 24
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#define RG_RX_DES_RCPI_GN_HI 29
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#define RG_RX_DES_RCPI_GN_SZ 6
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#define RG_TST_TBUS_SEL_MSK 0x0000000f
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#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
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#define RG_TST_TBUS_SEL_SFT 0
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#define RG_TST_TBUS_SEL_HI 3
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#define RG_TST_TBUS_SEL_SZ 4
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#define RG_RSSI_OFFSET_MSK 0x00ff0000
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#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
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#define RG_RSSI_OFFSET_SFT 16
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#define RG_RSSI_OFFSET_HI 23
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#define RG_RSSI_OFFSET_SZ 8
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#define RG_RSSI_INV_MSK 0x01000000
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#define RG_RSSI_INV_I_MSK 0xfeffffff
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#define RG_RSSI_INV_SFT 24
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#define RG_RSSI_INV_HI 24
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#define RG_RSSI_INV_SZ 1
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#define RG_TST_ADC_ON_MSK 0x40000000
|
#define RG_TST_ADC_ON_I_MSK 0xbfffffff
|
#define RG_TST_ADC_ON_SFT 30
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#define RG_TST_ADC_ON_HI 30
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#define RG_TST_ADC_ON_SZ 1
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#define RG_TST_EXT_GAIN_MSK 0x80000000
|
#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
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#define RG_TST_EXT_GAIN_SFT 31
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#define RG_TST_EXT_GAIN_HI 31
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#define RG_TST_EXT_GAIN_SZ 1
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#define RG_DAC_Q_SET_MSK 0x000003ff
|
#define RG_DAC_Q_SET_I_MSK 0xfffffc00
|
#define RG_DAC_Q_SET_SFT 0
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#define RG_DAC_Q_SET_HI 9
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#define RG_DAC_Q_SET_SZ 10
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#define RG_DAC_I_SET_MSK 0x003ff000
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#define RG_DAC_I_SET_I_MSK 0xffc00fff
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#define RG_DAC_I_SET_SFT 12
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#define RG_DAC_I_SET_HI 21
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#define RG_DAC_I_SET_SZ 10
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#define RG_DAC_EN_MAN_MSK 0x10000000
|
#define RG_DAC_EN_MAN_I_MSK 0xefffffff
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#define RG_DAC_EN_MAN_SFT 28
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#define RG_DAC_EN_MAN_HI 28
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#define RG_DAC_EN_MAN_SZ 1
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#define RG_IQC_FFT_EN_MSK 0x20000000
|
#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
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#define RG_IQC_FFT_EN_SFT 29
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#define RG_IQC_FFT_EN_HI 29
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#define RG_IQC_FFT_EN_SZ 1
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#define RG_DAC_MAN_Q_EN_MSK 0x40000000
|
#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
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#define RG_DAC_MAN_Q_EN_SFT 30
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#define RG_DAC_MAN_Q_EN_HI 30
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#define RG_DAC_MAN_Q_EN_SZ 1
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#define RG_DAC_MAN_I_EN_MSK 0x80000000
|
#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
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#define RG_DAC_MAN_I_EN_SFT 31
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#define RG_DAC_MAN_I_EN_HI 31
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#define RG_DAC_MAN_I_EN_SZ 1
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#define RO_MRX_EN_CNT_MSK 0x0000ffff
|
#define RO_MRX_EN_CNT_I_MSK 0xffff0000
|
#define RO_MRX_EN_CNT_SFT 0
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#define RO_MRX_EN_CNT_HI 15
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#define RO_MRX_EN_CNT_SZ 16
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#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
|
#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
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#define RG_MRX_EN_CNT_RST_N_SFT 31
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#define RG_MRX_EN_CNT_RST_N_HI 31
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#define RG_MRX_EN_CNT_RST_N_SZ 1
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#define RG_PA_RISE_TIME_MSK 0x000000ff
|
#define RG_PA_RISE_TIME_I_MSK 0xffffff00
|
#define RG_PA_RISE_TIME_SFT 0
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#define RG_PA_RISE_TIME_HI 7
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#define RG_PA_RISE_TIME_SZ 8
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#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
|
#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
|
#define RG_RFTX_RISE_TIME_SFT 8
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#define RG_RFTX_RISE_TIME_HI 15
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#define RG_RFTX_RISE_TIME_SZ 8
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#define RG_DAC_RISE_TIME_MSK 0x00ff0000
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#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
|
#define RG_DAC_RISE_TIME_SFT 16
|
#define RG_DAC_RISE_TIME_HI 23
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#define RG_DAC_RISE_TIME_SZ 8
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#define RG_SW_RISE_TIME_MSK 0xff000000
|
#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
|
#define RG_SW_RISE_TIME_SFT 24
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#define RG_SW_RISE_TIME_HI 31
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#define RG_SW_RISE_TIME_SZ 8
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#define RG_PA_FALL_TIME_MSK 0x000000ff
|
#define RG_PA_FALL_TIME_I_MSK 0xffffff00
|
#define RG_PA_FALL_TIME_SFT 0
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#define RG_PA_FALL_TIME_HI 7
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#define RG_PA_FALL_TIME_SZ 8
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#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
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#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
|
#define RG_RFTX_FALL_TIME_SFT 8
|
#define RG_RFTX_FALL_TIME_HI 15
|
#define RG_RFTX_FALL_TIME_SZ 8
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#define RG_DAC_FALL_TIME_MSK 0x00ff0000
|
#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
|
#define RG_DAC_FALL_TIME_SFT 16
|
#define RG_DAC_FALL_TIME_HI 23
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#define RG_DAC_FALL_TIME_SZ 8
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#define RG_SW_FALL_TIME_MSK 0xff000000
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#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
|
#define RG_SW_FALL_TIME_SFT 24
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#define RG_SW_FALL_TIME_HI 31
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#define RG_SW_FALL_TIME_SZ 8
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#define RG_ANT_SW_0_MSK 0x00000007
|
#define RG_ANT_SW_0_I_MSK 0xfffffff8
|
#define RG_ANT_SW_0_SFT 0
|
#define RG_ANT_SW_0_HI 2
|
#define RG_ANT_SW_0_SZ 3
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#define RG_ANT_SW_1_MSK 0x00000038
|
#define RG_ANT_SW_1_I_MSK 0xffffffc7
|
#define RG_ANT_SW_1_SFT 3
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#define RG_ANT_SW_1_HI 5
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#define RG_ANT_SW_1_SZ 3
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#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
|
#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
|
#define RG_MTX_LEN_LOWER_TH_0_SFT 0
|
#define RG_MTX_LEN_LOWER_TH_0_HI 12
|
#define RG_MTX_LEN_LOWER_TH_0_SZ 13
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#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
|
#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
|
#define RG_MTX_LEN_UPPER_TH_0_SFT 16
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#define RG_MTX_LEN_UPPER_TH_0_HI 28
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#define RG_MTX_LEN_UPPER_TH_0_SZ 13
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#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
|
#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
|
#define RG_MTX_LEN_CNT_EN_0_SFT 31
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#define RG_MTX_LEN_CNT_EN_0_HI 31
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#define RG_MTX_LEN_CNT_EN_0_SZ 1
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#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
|
#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
|
#define RG_MTX_LEN_LOWER_TH_1_SFT 0
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#define RG_MTX_LEN_LOWER_TH_1_HI 12
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#define RG_MTX_LEN_LOWER_TH_1_SZ 13
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#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
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#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
|
#define RG_MTX_LEN_UPPER_TH_1_SFT 16
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#define RG_MTX_LEN_UPPER_TH_1_HI 28
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#define RG_MTX_LEN_UPPER_TH_1_SZ 13
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#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
|
#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
|
#define RG_MTX_LEN_CNT_EN_1_SFT 31
|
#define RG_MTX_LEN_CNT_EN_1_HI 31
|
#define RG_MTX_LEN_CNT_EN_1_SZ 1
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#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
|
#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
|
#define RG_MRX_LEN_LOWER_TH_0_SFT 0
|
#define RG_MRX_LEN_LOWER_TH_0_HI 12
|
#define RG_MRX_LEN_LOWER_TH_0_SZ 13
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#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
|
#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
|
#define RG_MRX_LEN_UPPER_TH_0_SFT 16
|
#define RG_MRX_LEN_UPPER_TH_0_HI 28
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#define RG_MRX_LEN_UPPER_TH_0_SZ 13
|
#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
|
#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
|
#define RG_MRX_LEN_CNT_EN_0_SFT 31
|
#define RG_MRX_LEN_CNT_EN_0_HI 31
|
#define RG_MRX_LEN_CNT_EN_0_SZ 1
|
#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
|
#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
|
#define RG_MRX_LEN_LOWER_TH_1_SFT 0
|
#define RG_MRX_LEN_LOWER_TH_1_HI 12
|
#define RG_MRX_LEN_LOWER_TH_1_SZ 13
|
#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
|
#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
|
#define RG_MRX_LEN_UPPER_TH_1_SFT 16
|
#define RG_MRX_LEN_UPPER_TH_1_HI 28
|
#define RG_MRX_LEN_UPPER_TH_1_SZ 13
|
#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
|
#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
|
#define RG_MRX_LEN_CNT_EN_1_SFT 31
|
#define RG_MRX_LEN_CNT_EN_1_HI 31
|
#define RG_MRX_LEN_CNT_EN_1_SZ 1
|
#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
|
#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
|
#define RO_MTX_LEN_CNT_1_SFT 0
|
#define RO_MTX_LEN_CNT_1_HI 15
|
#define RO_MTX_LEN_CNT_1_SZ 16
|
#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
|
#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
|
#define RO_MTX_LEN_CNT_0_SFT 16
|
#define RO_MTX_LEN_CNT_0_HI 31
|
#define RO_MTX_LEN_CNT_0_SZ 16
|
#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
|
#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
|
#define RO_MRX_LEN_CNT_1_SFT 0
|
#define RO_MRX_LEN_CNT_1_HI 15
|
#define RO_MRX_LEN_CNT_1_SZ 16
|
#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
|
#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
|
#define RO_MRX_LEN_CNT_0_SFT 16
|
#define RO_MRX_LEN_CNT_0_HI 31
|
#define RO_MRX_LEN_CNT_0_SZ 16
|
#define RG_MODE_REG_IN_16_MSK 0x0000ffff
|
#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
|
#define RG_MODE_REG_IN_16_SFT 0
|
#define RG_MODE_REG_IN_16_HI 15
|
#define RG_MODE_REG_IN_16_SZ 16
|
#define RG_PARALLEL_DR_16_MSK 0x00100000
|
#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
|
#define RG_PARALLEL_DR_16_SFT 20
|
#define RG_PARALLEL_DR_16_HI 20
|
#define RG_PARALLEL_DR_16_SZ 1
|
#define RG_MBRUN_16_MSK 0x01000000
|
#define RG_MBRUN_16_I_MSK 0xfeffffff
|
#define RG_MBRUN_16_SFT 24
|
#define RG_MBRUN_16_HI 24
|
#define RG_MBRUN_16_SZ 1
|
#define RG_SHIFT_DR_16_MSK 0x10000000
|
#define RG_SHIFT_DR_16_I_MSK 0xefffffff
|
#define RG_SHIFT_DR_16_SFT 28
|
#define RG_SHIFT_DR_16_HI 28
|
#define RG_SHIFT_DR_16_SZ 1
|
#define RG_MODE_REG_SI_16_MSK 0x20000000
|
#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
|
#define RG_MODE_REG_SI_16_SFT 29
|
#define RG_MODE_REG_SI_16_HI 29
|
#define RG_MODE_REG_SI_16_SZ 1
|
#define RG_SIMULATION_MODE_16_MSK 0x40000000
|
#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
|
#define RG_SIMULATION_MODE_16_SFT 30
|
#define RG_SIMULATION_MODE_16_HI 30
|
#define RG_SIMULATION_MODE_16_SZ 1
|
#define RG_DBIST_MODE_16_MSK 0x80000000
|
#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
|
#define RG_DBIST_MODE_16_SFT 31
|
#define RG_DBIST_MODE_16_HI 31
|
#define RG_DBIST_MODE_16_SZ 1
|
#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
|
#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
|
#define RO_MODE_REG_OUT_16_SFT 0
|
#define RO_MODE_REG_OUT_16_HI 15
|
#define RO_MODE_REG_OUT_16_SZ 16
|
#define RO_MODE_REG_SO_16_MSK 0x01000000
|
#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
|
#define RO_MODE_REG_SO_16_SFT 24
|
#define RO_MODE_REG_SO_16_HI 24
|
#define RO_MODE_REG_SO_16_SZ 1
|
#define RO_MONITOR_BUS_16_MSK 0x0007ffff
|
#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
|
#define RO_MONITOR_BUS_16_SFT 0
|
#define RO_MONITOR_BUS_16_HI 18
|
#define RO_MONITOR_BUS_16_SZ 19
|
#define RG_MRX_TYPE_1_MSK 0x000000ff
|
#define RG_MRX_TYPE_1_I_MSK 0xffffff00
|
#define RG_MRX_TYPE_1_SFT 0
|
#define RG_MRX_TYPE_1_HI 7
|
#define RG_MRX_TYPE_1_SZ 8
|
#define RG_MRX_TYPE_0_MSK 0x0000ff00
|
#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
|
#define RG_MRX_TYPE_0_SFT 8
|
#define RG_MRX_TYPE_0_HI 15
|
#define RG_MRX_TYPE_0_SZ 8
|
#define RG_MTX_TYPE_1_MSK 0x00ff0000
|
#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
|
#define RG_MTX_TYPE_1_SFT 16
|
#define RG_MTX_TYPE_1_HI 23
|
#define RG_MTX_TYPE_1_SZ 8
|
#define RG_MTX_TYPE_0_MSK 0xff000000
|
#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
|
#define RG_MTX_TYPE_0_SFT 24
|
#define RG_MTX_TYPE_0_HI 31
|
#define RG_MTX_TYPE_0_SZ 8
|
#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
|
#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
|
#define RO_MTX_TYPE_CNT_1_SFT 0
|
#define RO_MTX_TYPE_CNT_1_HI 15
|
#define RO_MTX_TYPE_CNT_1_SZ 16
|
#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
|
#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
|
#define RO_MTX_TYPE_CNT_0_SFT 16
|
#define RO_MTX_TYPE_CNT_0_HI 31
|
#define RO_MTX_TYPE_CNT_0_SZ 16
|
#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
|
#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
|
#define RO_MRX_TYPE_CNT_1_SFT 0
|
#define RO_MRX_TYPE_CNT_1_HI 15
|
#define RO_MRX_TYPE_CNT_1_SZ 16
|
#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
|
#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
|
#define RO_MRX_TYPE_CNT_0_SFT 16
|
#define RO_MRX_TYPE_CNT_0_HI 31
|
#define RO_MRX_TYPE_CNT_0_SZ 16
|
#define RG_HB_COEF0_MSK 0x00000fff
|
#define RG_HB_COEF0_I_MSK 0xfffff000
|
#define RG_HB_COEF0_SFT 0
|
#define RG_HB_COEF0_HI 11
|
#define RG_HB_COEF0_SZ 12
|
#define RG_HB_COEF1_MSK 0x0fff0000
|
#define RG_HB_COEF1_I_MSK 0xf000ffff
|
#define RG_HB_COEF1_SFT 16
|
#define RG_HB_COEF1_HI 27
|
#define RG_HB_COEF1_SZ 12
|
#define RG_HB_COEF2_MSK 0x00000fff
|
#define RG_HB_COEF2_I_MSK 0xfffff000
|
#define RG_HB_COEF2_SFT 0
|
#define RG_HB_COEF2_HI 11
|
#define RG_HB_COEF2_SZ 12
|
#define RG_HB_COEF3_MSK 0x0fff0000
|
#define RG_HB_COEF3_I_MSK 0xf000ffff
|
#define RG_HB_COEF3_SFT 16
|
#define RG_HB_COEF3_HI 27
|
#define RG_HB_COEF3_SZ 12
|
#define RG_HB_COEF4_MSK 0x00000fff
|
#define RG_HB_COEF4_I_MSK 0xfffff000
|
#define RG_HB_COEF4_SFT 0
|
#define RG_HB_COEF4_HI 11
|
#define RG_HB_COEF4_SZ 12
|
#define RO_TBUS_O_MSK 0x000fffff
|
#define RO_TBUS_O_I_MSK 0xfff00000
|
#define RO_TBUS_O_SFT 0
|
#define RO_TBUS_O_HI 19
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#define RO_TBUS_O_SZ 20
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#define RG_LPF4_00_MSK 0x00001fff
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#define RG_LPF4_00_I_MSK 0xffffe000
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#define RG_LPF4_00_SFT 0
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#define RG_LPF4_00_HI 12
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#define RG_LPF4_00_SZ 13
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#define RG_LPF4_01_MSK 0x00001fff
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#define RG_LPF4_01_I_MSK 0xffffe000
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#define RG_LPF4_01_SFT 0
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#define RG_LPF4_01_HI 12
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#define RG_LPF4_01_SZ 13
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#define RG_LPF4_02_MSK 0x00001fff
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#define RG_LPF4_02_I_MSK 0xffffe000
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#define RG_LPF4_02_SFT 0
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#define RG_LPF4_02_HI 12
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#define RG_LPF4_02_SZ 13
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#define RG_LPF4_03_MSK 0x00001fff
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#define RG_LPF4_03_I_MSK 0xffffe000
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#define RG_LPF4_03_SFT 0
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#define RG_LPF4_03_HI 12
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#define RG_LPF4_03_SZ 13
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#define RG_LPF4_04_MSK 0x00001fff
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#define RG_LPF4_04_I_MSK 0xffffe000
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#define RG_LPF4_04_SFT 0
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#define RG_LPF4_04_HI 12
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#define RG_LPF4_04_SZ 13
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#define RG_LPF4_05_MSK 0x00001fff
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#define RG_LPF4_05_I_MSK 0xffffe000
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#define RG_LPF4_05_SFT 0
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#define RG_LPF4_05_HI 12
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#define RG_LPF4_05_SZ 13
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#define RG_LPF4_06_MSK 0x00001fff
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#define RG_LPF4_06_I_MSK 0xffffe000
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#define RG_LPF4_06_SFT 0
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#define RG_LPF4_06_HI 12
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#define RG_LPF4_06_SZ 13
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#define RG_LPF4_07_MSK 0x00001fff
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#define RG_LPF4_07_I_MSK 0xffffe000
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#define RG_LPF4_07_SFT 0
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#define RG_LPF4_07_HI 12
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#define RG_LPF4_07_SZ 13
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#define RG_LPF4_08_MSK 0x00001fff
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#define RG_LPF4_08_I_MSK 0xffffe000
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#define RG_LPF4_08_SFT 0
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#define RG_LPF4_08_HI 12
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#define RG_LPF4_08_SZ 13
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#define RG_LPF4_09_MSK 0x00001fff
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#define RG_LPF4_09_I_MSK 0xffffe000
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#define RG_LPF4_09_SFT 0
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#define RG_LPF4_09_HI 12
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#define RG_LPF4_09_SZ 13
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#define RG_LPF4_10_MSK 0x00001fff
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#define RG_LPF4_10_I_MSK 0xffffe000
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#define RG_LPF4_10_SFT 0
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#define RG_LPF4_10_HI 12
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#define RG_LPF4_10_SZ 13
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#define RG_LPF4_11_MSK 0x00001fff
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#define RG_LPF4_11_I_MSK 0xffffe000
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#define RG_LPF4_11_SFT 0
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#define RG_LPF4_11_HI 12
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#define RG_LPF4_11_SZ 13
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#define RG_LPF4_12_MSK 0x00001fff
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#define RG_LPF4_12_I_MSK 0xffffe000
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#define RG_LPF4_12_SFT 0
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#define RG_LPF4_12_HI 12
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#define RG_LPF4_12_SZ 13
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#define RG_LPF4_13_MSK 0x00001fff
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#define RG_LPF4_13_I_MSK 0xffffe000
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#define RG_LPF4_13_SFT 0
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#define RG_LPF4_13_HI 12
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#define RG_LPF4_13_SZ 13
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#define RG_LPF4_14_MSK 0x00001fff
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#define RG_LPF4_14_I_MSK 0xffffe000
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#define RG_LPF4_14_SFT 0
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#define RG_LPF4_14_HI 12
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#define RG_LPF4_14_SZ 13
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#define RG_LPF4_15_MSK 0x00001fff
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#define RG_LPF4_15_I_MSK 0xffffe000
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#define RG_LPF4_15_SFT 0
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#define RG_LPF4_15_HI 12
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#define RG_LPF4_15_SZ 13
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#define RG_LPF4_16_MSK 0x00001fff
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#define RG_LPF4_16_I_MSK 0xffffe000
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#define RG_LPF4_16_SFT 0
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#define RG_LPF4_16_HI 12
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#define RG_LPF4_16_SZ 13
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#define RG_LPF4_17_MSK 0x00001fff
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#define RG_LPF4_17_I_MSK 0xffffe000
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#define RG_LPF4_17_SFT 0
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#define RG_LPF4_17_HI 12
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#define RG_LPF4_17_SZ 13
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#define RG_LPF4_18_MSK 0x00001fff
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#define RG_LPF4_18_I_MSK 0xffffe000
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#define RG_LPF4_18_SFT 0
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#define RG_LPF4_18_HI 12
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#define RG_LPF4_18_SZ 13
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#define RG_LPF4_19_MSK 0x00001fff
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#define RG_LPF4_19_I_MSK 0xffffe000
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#define RG_LPF4_19_SFT 0
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#define RG_LPF4_19_HI 12
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#define RG_LPF4_19_SZ 13
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#define RG_LPF4_20_MSK 0x00001fff
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#define RG_LPF4_20_I_MSK 0xffffe000
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#define RG_LPF4_20_SFT 0
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#define RG_LPF4_20_HI 12
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#define RG_LPF4_20_SZ 13
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#define RG_LPF4_21_MSK 0x00001fff
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#define RG_LPF4_21_I_MSK 0xffffe000
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#define RG_LPF4_21_SFT 0
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#define RG_LPF4_21_HI 12
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#define RG_LPF4_21_SZ 13
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#define RG_LPF4_22_MSK 0x00001fff
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#define RG_LPF4_22_I_MSK 0xffffe000
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#define RG_LPF4_22_SFT 0
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#define RG_LPF4_22_HI 12
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#define RG_LPF4_22_SZ 13
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#define RG_LPF4_23_MSK 0x00001fff
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#define RG_LPF4_23_I_MSK 0xffffe000
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#define RG_LPF4_23_SFT 0
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#define RG_LPF4_23_HI 12
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#define RG_LPF4_23_SZ 13
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#define RG_LPF4_24_MSK 0x00001fff
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#define RG_LPF4_24_I_MSK 0xffffe000
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#define RG_LPF4_24_SFT 0
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#define RG_LPF4_24_HI 12
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#define RG_LPF4_24_SZ 13
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#define RG_LPF4_25_MSK 0x00001fff
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#define RG_LPF4_25_I_MSK 0xffffe000
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#define RG_LPF4_25_SFT 0
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#define RG_LPF4_25_HI 12
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#define RG_LPF4_25_SZ 13
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#define RG_LPF4_26_MSK 0x00001fff
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#define RG_LPF4_26_I_MSK 0xffffe000
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#define RG_LPF4_26_SFT 0
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#define RG_LPF4_26_HI 12
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#define RG_LPF4_26_SZ 13
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#define RG_LPF4_27_MSK 0x00001fff
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#define RG_LPF4_27_I_MSK 0xffffe000
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#define RG_LPF4_27_SFT 0
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#define RG_LPF4_27_HI 12
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#define RG_LPF4_27_SZ 13
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#define RG_LPF4_28_MSK 0x00001fff
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#define RG_LPF4_28_I_MSK 0xffffe000
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#define RG_LPF4_28_SFT 0
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#define RG_LPF4_28_HI 12
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#define RG_LPF4_28_SZ 13
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#define RG_LPF4_29_MSK 0x00001fff
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#define RG_LPF4_29_I_MSK 0xffffe000
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#define RG_LPF4_29_SFT 0
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#define RG_LPF4_29_HI 12
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#define RG_LPF4_29_SZ 13
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#define RG_LPF4_30_MSK 0x00001fff
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#define RG_LPF4_30_I_MSK 0xffffe000
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#define RG_LPF4_30_SFT 0
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#define RG_LPF4_30_HI 12
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#define RG_LPF4_30_SZ 13
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#define RG_LPF4_31_MSK 0x00001fff
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#define RG_LPF4_31_I_MSK 0xffffe000
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#define RG_LPF4_31_SFT 0
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#define RG_LPF4_31_HI 12
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#define RG_LPF4_31_SZ 13
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#define RG_LPF4_32_MSK 0x00001fff
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#define RG_LPF4_32_I_MSK 0xffffe000
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#define RG_LPF4_32_SFT 0
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#define RG_LPF4_32_HI 12
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#define RG_LPF4_32_SZ 13
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#define RG_LPF4_33_MSK 0x00001fff
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#define RG_LPF4_33_I_MSK 0xffffe000
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#define RG_LPF4_33_SFT 0
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#define RG_LPF4_33_HI 12
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#define RG_LPF4_33_SZ 13
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#define RG_LPF4_34_MSK 0x00001fff
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#define RG_LPF4_34_I_MSK 0xffffe000
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#define RG_LPF4_34_SFT 0
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#define RG_LPF4_34_HI 12
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#define RG_LPF4_34_SZ 13
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#define RG_LPF4_35_MSK 0x00001fff
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#define RG_LPF4_35_I_MSK 0xffffe000
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#define RG_LPF4_35_SFT 0
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#define RG_LPF4_35_HI 12
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#define RG_LPF4_35_SZ 13
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#define RG_LPF4_36_MSK 0x00001fff
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#define RG_LPF4_36_I_MSK 0xffffe000
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#define RG_LPF4_36_SFT 0
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#define RG_LPF4_36_HI 12
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#define RG_LPF4_36_SZ 13
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#define RG_LPF4_37_MSK 0x00001fff
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#define RG_LPF4_37_I_MSK 0xffffe000
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#define RG_LPF4_37_SFT 0
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#define RG_LPF4_37_HI 12
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#define RG_LPF4_37_SZ 13
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#define RG_LPF4_38_MSK 0x00001fff
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#define RG_LPF4_38_I_MSK 0xffffe000
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#define RG_LPF4_38_SFT 0
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#define RG_LPF4_38_HI 12
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#define RG_LPF4_38_SZ 13
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#define RG_LPF4_39_MSK 0x00001fff
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#define RG_LPF4_39_I_MSK 0xffffe000
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#define RG_LPF4_39_SFT 0
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#define RG_LPF4_39_HI 12
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#define RG_LPF4_39_SZ 13
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#define RG_LPF4_40_MSK 0x00001fff
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#define RG_LPF4_40_I_MSK 0xffffe000
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#define RG_LPF4_40_SFT 0
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#define RG_LPF4_40_HI 12
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#define RG_LPF4_40_SZ 13
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#define RG_BP_SMB_MSK 0x00002000
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#define RG_BP_SMB_I_MSK 0xffffdfff
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#define RG_BP_SMB_SFT 13
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#define RG_BP_SMB_HI 13
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#define RG_BP_SMB_SZ 1
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#define RG_EN_SRVC_MSK 0x00004000
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#define RG_EN_SRVC_I_MSK 0xffffbfff
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#define RG_EN_SRVC_SFT 14
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#define RG_EN_SRVC_HI 14
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#define RG_EN_SRVC_SZ 1
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#define RG_DES_SPD_MSK 0x00030000
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#define RG_DES_SPD_I_MSK 0xfffcffff
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#define RG_DES_SPD_SFT 16
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#define RG_DES_SPD_HI 17
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#define RG_DES_SPD_SZ 2
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#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
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#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
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#define RG_BB_11B_RISE_TIME_SFT 0
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#define RG_BB_11B_RISE_TIME_HI 7
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#define RG_BB_11B_RISE_TIME_SZ 8
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#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
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#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
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#define RG_BB_11B_FALL_TIME_SFT 8
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#define RG_BB_11B_FALL_TIME_HI 15
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#define RG_BB_11B_FALL_TIME_SZ 8
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#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
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#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
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#define RG_WR_TX_EN_CNT_RST_N_SFT 0
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#define RG_WR_TX_EN_CNT_RST_N_HI 0
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#define RG_WR_TX_EN_CNT_RST_N_SZ 1
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#define RO_TX_EN_CNT_MSK 0x0000ffff
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#define RO_TX_EN_CNT_I_MSK 0xffff0000
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#define RO_TX_EN_CNT_SFT 0
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#define RO_TX_EN_CNT_HI 15
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#define RO_TX_EN_CNT_SZ 16
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#define RO_TX_CNT_MSK 0xffffffff
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#define RO_TX_CNT_I_MSK 0x00000000
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#define RO_TX_CNT_SFT 0
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#define RO_TX_CNT_HI 31
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#define RO_TX_CNT_SZ 32
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#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
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#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
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#define RG_POS_DES_11B_L_EXT_SFT 0
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#define RG_POS_DES_11B_L_EXT_HI 3
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#define RG_POS_DES_11B_L_EXT_SZ 4
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#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
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#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
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#define RG_PRE_DES_11B_DLY_SFT 4
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#define RG_PRE_DES_11B_DLY_HI 7
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#define RG_PRE_DES_11B_DLY_SZ 4
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#define RG_CNT_CCA_LMT_MSK 0x000f0000
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#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
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#define RG_CNT_CCA_LMT_SFT 16
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#define RG_CNT_CCA_LMT_HI 19
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#define RG_CNT_CCA_LMT_SZ 4
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#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
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#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
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#define RG_BYPASS_DESCRAMBLER_SFT 29
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#define RG_BYPASS_DESCRAMBLER_HI 29
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#define RG_BYPASS_DESCRAMBLER_SZ 1
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#define RG_BYPASS_AGC_MSK 0x80000000
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#define RG_BYPASS_AGC_I_MSK 0x7fffffff
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#define RG_BYPASS_AGC_SFT 31
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#define RG_BYPASS_AGC_HI 31
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#define RG_BYPASS_AGC_SZ 1
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#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
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#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
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#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
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#define RG_CCA_BIT_CNT_LMT_RX_HI 7
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#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
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#define RG_CCA_SCALE_BF_MSK 0x007f0000
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#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
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#define RG_CCA_SCALE_BF_SFT 16
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#define RG_CCA_SCALE_BF_HI 22
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#define RG_CCA_SCALE_BF_SZ 7
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#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
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#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
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#define RG_PEAK_IDX_CNT_SEL_SFT 28
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#define RG_PEAK_IDX_CNT_SEL_HI 29
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#define RG_PEAK_IDX_CNT_SEL_SZ 2
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#define RG_TR_KI_T2_MSK 0x00000007
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#define RG_TR_KI_T2_I_MSK 0xfffffff8
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#define RG_TR_KI_T2_SFT 0
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#define RG_TR_KI_T2_HI 2
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#define RG_TR_KI_T2_SZ 3
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#define RG_TR_KP_T2_MSK 0x00000070
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#define RG_TR_KP_T2_I_MSK 0xffffff8f
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#define RG_TR_KP_T2_SFT 4
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#define RG_TR_KP_T2_HI 6
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#define RG_TR_KP_T2_SZ 3
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#define RG_TR_KI_T1_MSK 0x00000700
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#define RG_TR_KI_T1_I_MSK 0xfffff8ff
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#define RG_TR_KI_T1_SFT 8
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#define RG_TR_KI_T1_HI 10
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#define RG_TR_KI_T1_SZ 3
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#define RG_TR_KP_T1_MSK 0x00007000
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#define RG_TR_KP_T1_I_MSK 0xffff8fff
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#define RG_TR_KP_T1_SFT 12
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#define RG_TR_KP_T1_HI 14
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#define RG_TR_KP_T1_SZ 3
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#define RG_CR_KI_T1_MSK 0x00070000
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#define RG_CR_KI_T1_I_MSK 0xfff8ffff
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#define RG_CR_KI_T1_SFT 16
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#define RG_CR_KI_T1_HI 18
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#define RG_CR_KI_T1_SZ 3
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#define RG_CR_KP_T1_MSK 0x00700000
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#define RG_CR_KP_T1_I_MSK 0xff8fffff
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#define RG_CR_KP_T1_SFT 20
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#define RG_CR_KP_T1_HI 22
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#define RG_CR_KP_T1_SZ 3
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#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
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#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
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#define RG_CHIP_CNT_SLICER_SFT 0
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#define RG_CHIP_CNT_SLICER_HI 4
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#define RG_CHIP_CNT_SLICER_SZ 5
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#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
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#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
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#define RG_CE_T4_CNT_LMT_SFT 8
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#define RG_CE_T4_CNT_LMT_HI 15
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#define RG_CE_T4_CNT_LMT_SZ 8
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#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
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#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
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#define RG_CE_T3_CNT_LMT_SFT 16
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#define RG_CE_T3_CNT_LMT_HI 23
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#define RG_CE_T3_CNT_LMT_SZ 8
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#define RG_CE_T2_CNT_LMT_MSK 0xff000000
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#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
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#define RG_CE_T2_CNT_LMT_SFT 24
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#define RG_CE_T2_CNT_LMT_HI 31
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#define RG_CE_T2_CNT_LMT_SZ 8
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#define RG_CE_MU_T1_MSK 0x00000007
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#define RG_CE_MU_T1_I_MSK 0xfffffff8
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#define RG_CE_MU_T1_SFT 0
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#define RG_CE_MU_T1_HI 2
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#define RG_CE_MU_T1_SZ 3
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#define RG_CE_DLY_SEL_MSK 0x003f0000
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#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
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#define RG_CE_DLY_SEL_SFT 16
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#define RG_CE_DLY_SEL_HI 21
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#define RG_CE_DLY_SEL_SZ 6
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#define RG_CE_MU_T8_MSK 0x00000007
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#define RG_CE_MU_T8_I_MSK 0xfffffff8
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#define RG_CE_MU_T8_SFT 0
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#define RG_CE_MU_T8_HI 2
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#define RG_CE_MU_T8_SZ 3
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#define RG_CE_MU_T7_MSK 0x00000070
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#define RG_CE_MU_T7_I_MSK 0xffffff8f
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#define RG_CE_MU_T7_SFT 4
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#define RG_CE_MU_T7_HI 6
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#define RG_CE_MU_T7_SZ 3
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#define RG_CE_MU_T6_MSK 0x00000700
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#define RG_CE_MU_T6_I_MSK 0xfffff8ff
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#define RG_CE_MU_T6_SFT 8
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#define RG_CE_MU_T6_HI 10
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#define RG_CE_MU_T6_SZ 3
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#define RG_CE_MU_T5_MSK 0x00007000
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#define RG_CE_MU_T5_I_MSK 0xffff8fff
|
#define RG_CE_MU_T5_SFT 12
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#define RG_CE_MU_T5_HI 14
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#define RG_CE_MU_T5_SZ 3
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#define RG_CE_MU_T4_MSK 0x00070000
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#define RG_CE_MU_T4_I_MSK 0xfff8ffff
|
#define RG_CE_MU_T4_SFT 16
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#define RG_CE_MU_T4_HI 18
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#define RG_CE_MU_T4_SZ 3
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#define RG_CE_MU_T3_MSK 0x00700000
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#define RG_CE_MU_T3_I_MSK 0xff8fffff
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#define RG_CE_MU_T3_SFT 20
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#define RG_CE_MU_T3_HI 22
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#define RG_CE_MU_T3_SZ 3
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#define RG_CE_MU_T2_MSK 0x07000000
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#define RG_CE_MU_T2_I_MSK 0xf8ffffff
|
#define RG_CE_MU_T2_SFT 24
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#define RG_CE_MU_T2_HI 26
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#define RG_CE_MU_T2_SZ 3
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#define RG_EQ_MU_FB_T2_MSK 0x0000000f
|
#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
|
#define RG_EQ_MU_FB_T2_SFT 0
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#define RG_EQ_MU_FB_T2_HI 3
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#define RG_EQ_MU_FB_T2_SZ 4
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#define RG_EQ_MU_FF_T2_MSK 0x000000f0
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#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
|
#define RG_EQ_MU_FF_T2_SFT 4
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#define RG_EQ_MU_FF_T2_HI 7
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#define RG_EQ_MU_FF_T2_SZ 4
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#define RG_EQ_MU_FB_T1_MSK 0x000f0000
|
#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
|
#define RG_EQ_MU_FB_T1_SFT 16
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#define RG_EQ_MU_FB_T1_HI 19
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#define RG_EQ_MU_FB_T1_SZ 4
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#define RG_EQ_MU_FF_T1_MSK 0x00f00000
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#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
|
#define RG_EQ_MU_FF_T1_SFT 20
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#define RG_EQ_MU_FF_T1_HI 23
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#define RG_EQ_MU_FF_T1_SZ 4
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#define RG_EQ_MU_FB_T4_MSK 0x0000000f
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#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
|
#define RG_EQ_MU_FB_T4_SFT 0
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#define RG_EQ_MU_FB_T4_HI 3
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#define RG_EQ_MU_FB_T4_SZ 4
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#define RG_EQ_MU_FF_T4_MSK 0x000000f0
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#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
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#define RG_EQ_MU_FF_T4_SFT 4
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#define RG_EQ_MU_FF_T4_HI 7
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#define RG_EQ_MU_FF_T4_SZ 4
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#define RG_EQ_MU_FB_T3_MSK 0x000f0000
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#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
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#define RG_EQ_MU_FB_T3_SFT 16
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#define RG_EQ_MU_FB_T3_HI 19
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#define RG_EQ_MU_FB_T3_SZ 4
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#define RG_EQ_MU_FF_T3_MSK 0x00f00000
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#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
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#define RG_EQ_MU_FF_T3_SFT 20
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#define RG_EQ_MU_FF_T3_HI 23
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#define RG_EQ_MU_FF_T3_SZ 4
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#define RG_EQ_KI_T2_MSK 0x00000700
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#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
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#define RG_EQ_KI_T2_SFT 8
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#define RG_EQ_KI_T2_HI 10
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#define RG_EQ_KI_T2_SZ 3
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#define RG_EQ_KP_T2_MSK 0x00007000
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#define RG_EQ_KP_T2_I_MSK 0xffff8fff
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#define RG_EQ_KP_T2_SFT 12
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#define RG_EQ_KP_T2_HI 14
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#define RG_EQ_KP_T2_SZ 3
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#define RG_EQ_KI_T1_MSK 0x00070000
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#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
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#define RG_EQ_KI_T1_SFT 16
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#define RG_EQ_KI_T1_HI 18
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#define RG_EQ_KI_T1_SZ 3
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#define RG_EQ_KP_T1_MSK 0x00700000
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#define RG_EQ_KP_T1_I_MSK 0xff8fffff
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#define RG_EQ_KP_T1_SFT 20
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#define RG_EQ_KP_T1_HI 22
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#define RG_EQ_KP_T1_SZ 3
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#define RG_TR_LPF_RATE_MSK 0x003fffff
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#define RG_TR_LPF_RATE_I_MSK 0xffc00000
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#define RG_TR_LPF_RATE_SFT 0
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#define RG_TR_LPF_RATE_HI 21
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#define RG_TR_LPF_RATE_SZ 22
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#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
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#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
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#define RG_CE_BIT_CNT_LMT_SFT 0
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#define RG_CE_BIT_CNT_LMT_HI 6
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#define RG_CE_BIT_CNT_LMT_SZ 7
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#define RG_CE_CH_MAIN_SET_MSK 0x00000080
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#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
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#define RG_CE_CH_MAIN_SET_SFT 7
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#define RG_CE_CH_MAIN_SET_HI 7
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#define RG_CE_CH_MAIN_SET_SZ 1
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#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
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#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
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#define RG_TC_BIT_CNT_LMT_SFT 8
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#define RG_TC_BIT_CNT_LMT_HI 14
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#define RG_TC_BIT_CNT_LMT_SZ 7
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#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
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#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
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#define RG_CR_BIT_CNT_LMT_SFT 16
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#define RG_CR_BIT_CNT_LMT_HI 22
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#define RG_CR_BIT_CNT_LMT_SZ 7
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#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
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#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
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#define RG_TR_BIT_CNT_LMT_SFT 24
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#define RG_TR_BIT_CNT_LMT_HI 30
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#define RG_TR_BIT_CNT_LMT_SZ 7
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#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
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#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
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#define RG_EQ_MAIN_TAP_MAN_SFT 0
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#define RG_EQ_MAIN_TAP_MAN_HI 0
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#define RG_EQ_MAIN_TAP_MAN_SZ 1
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#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
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#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
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#define RG_EQ_MAIN_TAP_COEF_SFT 16
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#define RG_EQ_MAIN_TAP_COEF_HI 26
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#define RG_EQ_MAIN_TAP_COEF_SZ 11
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#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
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#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
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#define RG_PWRON_DLY_TH_11B_SFT 0
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#define RG_PWRON_DLY_TH_11B_HI 7
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#define RG_PWRON_DLY_TH_11B_SZ 8
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#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
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#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
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#define RG_SFD_BIT_CNT_LMT_SFT 16
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#define RG_SFD_BIT_CNT_LMT_HI 23
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#define RG_SFD_BIT_CNT_LMT_SZ 8
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#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
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#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
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#define RG_CCA_PWR_TH_RX_SFT 0
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#define RG_CCA_PWR_TH_RX_HI 14
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#define RG_CCA_PWR_TH_RX_SZ 15
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#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
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#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
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#define RG_CCA_PWR_CNT_TH_SFT 16
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#define RG_CCA_PWR_CNT_TH_HI 20
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#define RG_CCA_PWR_CNT_TH_SZ 5
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#define B_FREQ_OS_MSK 0x000007ff
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#define B_FREQ_OS_I_MSK 0xfffff800
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#define B_FREQ_OS_SFT 0
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#define B_FREQ_OS_HI 10
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#define B_FREQ_OS_SZ 11
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#define B_SNR_MSK 0x0000007f
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#define B_SNR_I_MSK 0xffffff80
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#define B_SNR_SFT 0
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#define B_SNR_HI 6
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#define B_SNR_SZ 7
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#define B_RCPI_MSK 0x007f0000
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#define B_RCPI_I_MSK 0xff80ffff
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#define B_RCPI_SFT 16
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#define B_RCPI_HI 22
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#define B_RCPI_SZ 7
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#define CRC_CNT_MSK 0x0000ffff
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#define CRC_CNT_I_MSK 0xffff0000
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#define CRC_CNT_SFT 0
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#define CRC_CNT_HI 15
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#define CRC_CNT_SZ 16
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#define SFD_CNT_MSK 0xffff0000
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#define SFD_CNT_I_MSK 0x0000ffff
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#define SFD_CNT_SFT 16
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#define SFD_CNT_HI 31
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#define SFD_CNT_SZ 16
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#define B_PACKET_ERR_CNT_MSK 0x0000ffff
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#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
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#define B_PACKET_ERR_CNT_SFT 0
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#define B_PACKET_ERR_CNT_HI 15
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#define B_PACKET_ERR_CNT_SZ 16
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#define PACKET_ERR_MSK 0x00010000
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#define PACKET_ERR_I_MSK 0xfffeffff
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#define PACKET_ERR_SFT 16
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#define PACKET_ERR_HI 16
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#define PACKET_ERR_SZ 1
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#define B_PACKET_CNT_MSK 0x0000ffff
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#define B_PACKET_CNT_I_MSK 0xffff0000
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#define B_PACKET_CNT_SFT 0
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#define B_PACKET_CNT_HI 15
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#define B_PACKET_CNT_SZ 16
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#define B_CCA_CNT_MSK 0xffff0000
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#define B_CCA_CNT_I_MSK 0x0000ffff
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#define B_CCA_CNT_SFT 16
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#define B_CCA_CNT_HI 31
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#define B_CCA_CNT_SZ 16
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#define B_LENGTH_FIELD_MSK 0x0000ffff
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#define B_LENGTH_FIELD_I_MSK 0xffff0000
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#define B_LENGTH_FIELD_SFT 0
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#define B_LENGTH_FIELD_HI 15
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#define B_LENGTH_FIELD_SZ 16
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#define SFD_FIELD_MSK 0xffff0000
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#define SFD_FIELD_I_MSK 0x0000ffff
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#define SFD_FIELD_SFT 16
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#define SFD_FIELD_HI 31
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#define SFD_FIELD_SZ 16
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#define SIGNAL_FIELD_MSK 0x000000ff
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#define SIGNAL_FIELD_I_MSK 0xffffff00
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#define SIGNAL_FIELD_SFT 0
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#define SIGNAL_FIELD_HI 7
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#define SIGNAL_FIELD_SZ 8
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#define B_SERVICE_FIELD_MSK 0x0000ff00
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#define B_SERVICE_FIELD_I_MSK 0xffff00ff
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#define B_SERVICE_FIELD_SFT 8
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#define B_SERVICE_FIELD_HI 15
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#define B_SERVICE_FIELD_SZ 8
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#define CRC_CORRECT_MSK 0x00010000
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#define CRC_CORRECT_I_MSK 0xfffeffff
|
#define CRC_CORRECT_SFT 16
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#define CRC_CORRECT_HI 16
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#define CRC_CORRECT_SZ 1
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#define DEBUG_SEL_MSK 0x0000000f
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#define DEBUG_SEL_I_MSK 0xfffffff0
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#define DEBUG_SEL_SFT 0
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#define DEBUG_SEL_HI 3
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#define DEBUG_SEL_SZ 4
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#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
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#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
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#define RG_PACKET_STAT_EN_11B_SFT 20
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#define RG_PACKET_STAT_EN_11B_HI 20
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#define RG_PACKET_STAT_EN_11B_SZ 1
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#define RG_BIT_REVERSE_MSK 0x00200000
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#define RG_BIT_REVERSE_I_MSK 0xffdfffff
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#define RG_BIT_REVERSE_SFT 21
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#define RG_BIT_REVERSE_HI 21
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#define RG_BIT_REVERSE_SZ 1
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#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
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#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
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#define RX_PHY_11B_SOFT_RST_N_SFT 0
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#define RX_PHY_11B_SOFT_RST_N_HI 0
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#define RX_PHY_11B_SOFT_RST_N_SZ 1
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#define RG_CE_BYPASS_TAP_MSK 0x000000f0
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#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
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#define RG_CE_BYPASS_TAP_SFT 4
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#define RG_CE_BYPASS_TAP_HI 7
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#define RG_CE_BYPASS_TAP_SZ 4
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#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
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#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
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#define RG_EQ_BYPASS_FBW_TAP_SFT 8
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#define RG_EQ_BYPASS_FBW_TAP_HI 11
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#define RG_EQ_BYPASS_FBW_TAP_SZ 4
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#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
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#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
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#define RG_BB_11GN_RISE_TIME_SFT 0
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#define RG_BB_11GN_RISE_TIME_HI 7
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#define RG_BB_11GN_RISE_TIME_SZ 8
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#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
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#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
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#define RG_BB_11GN_FALL_TIME_SFT 8
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#define RG_BB_11GN_FALL_TIME_HI 15
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#define RG_BB_11GN_FALL_TIME_SZ 8
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#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
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#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
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#define RG_HTCARR52_FFT_SCALE_SFT 0
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#define RG_HTCARR52_FFT_SCALE_HI 9
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#define RG_HTCARR52_FFT_SCALE_SZ 10
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#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
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#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
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#define RG_HTCARR56_FFT_SCALE_SFT 12
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#define RG_HTCARR56_FFT_SCALE_HI 21
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#define RG_HTCARR56_FFT_SCALE_SZ 10
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#define RG_PACKET_STAT_EN_MSK 0x00800000
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#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
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#define RG_PACKET_STAT_EN_SFT 23
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#define RG_PACKET_STAT_EN_HI 23
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#define RG_PACKET_STAT_EN_SZ 1
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#define RG_SMB_DEF_MSK 0x7f000000
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#define RG_SMB_DEF_I_MSK 0x80ffffff
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#define RG_SMB_DEF_SFT 24
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#define RG_SMB_DEF_HI 30
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#define RG_SMB_DEF_SZ 7
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#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
|
#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
|
#define RG_CONTINUOUS_DATA_11GN_SFT 31
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#define RG_CONTINUOUS_DATA_11GN_HI 31
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#define RG_CONTINUOUS_DATA_11GN_SZ 1
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#define RO_TX_CNT_R_MSK 0xffffffff
|
#define RO_TX_CNT_R_I_MSK 0x00000000
|
#define RO_TX_CNT_R_SFT 0
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#define RO_TX_CNT_R_HI 31
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#define RO_TX_CNT_R_SZ 32
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#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
|
#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
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#define RO_PACKET_ERR_CNT_SFT 0
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#define RO_PACKET_ERR_CNT_HI 15
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#define RO_PACKET_ERR_CNT_SZ 16
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#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
|
#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
|
#define RG_POS_DES_11GN_L_EXT_SFT 0
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#define RG_POS_DES_11GN_L_EXT_HI 3
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#define RG_POS_DES_11GN_L_EXT_SZ 4
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#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
|
#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
|
#define RG_PRE_DES_11GN_DLY_SFT 4
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#define RG_PRE_DES_11GN_DLY_HI 7
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#define RG_PRE_DES_11GN_DLY_SZ 4
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#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
|
#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
|
#define RG_TR_LPF_KI_G_T1_SFT 0
|
#define RG_TR_LPF_KI_G_T1_HI 3
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#define RG_TR_LPF_KI_G_T1_SZ 4
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#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
|
#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
|
#define RG_TR_LPF_KP_G_T1_SFT 4
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#define RG_TR_LPF_KP_G_T1_HI 7
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#define RG_TR_LPF_KP_G_T1_SZ 4
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#define RG_TR_CNT_T1_MSK 0x0000ff00
|
#define RG_TR_CNT_T1_I_MSK 0xffff00ff
|
#define RG_TR_CNT_T1_SFT 8
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#define RG_TR_CNT_T1_HI 15
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#define RG_TR_CNT_T1_SZ 8
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#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
|
#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
|
#define RG_TR_LPF_KI_G_T0_SFT 16
|
#define RG_TR_LPF_KI_G_T0_HI 19
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#define RG_TR_LPF_KI_G_T0_SZ 4
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#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
|
#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
|
#define RG_TR_LPF_KP_G_T0_SFT 20
|
#define RG_TR_LPF_KP_G_T0_HI 23
|
#define RG_TR_LPF_KP_G_T0_SZ 4
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#define RG_TR_CNT_T0_MSK 0xff000000
|
#define RG_TR_CNT_T0_I_MSK 0x00ffffff
|
#define RG_TR_CNT_T0_SFT 24
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#define RG_TR_CNT_T0_HI 31
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#define RG_TR_CNT_T0_SZ 8
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#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
|
#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
|
#define RG_TR_LPF_KI_G_T2_SFT 0
|
#define RG_TR_LPF_KI_G_T2_HI 3
|
#define RG_TR_LPF_KI_G_T2_SZ 4
|
#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
|
#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
|
#define RG_TR_LPF_KP_G_T2_SFT 4
|
#define RG_TR_LPF_KP_G_T2_HI 7
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#define RG_TR_LPF_KP_G_T2_SZ 4
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#define RG_TR_CNT_T2_MSK 0x0000ff00
|
#define RG_TR_CNT_T2_I_MSK 0xffff00ff
|
#define RG_TR_CNT_T2_SFT 8
|
#define RG_TR_CNT_T2_HI 15
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#define RG_TR_CNT_T2_SZ 8
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#define RG_TR_LPF_KI_G_MSK 0x0000000f
|
#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
|
#define RG_TR_LPF_KI_G_SFT 0
|
#define RG_TR_LPF_KI_G_HI 3
|
#define RG_TR_LPF_KI_G_SZ 4
|
#define RG_TR_LPF_KP_G_MSK 0x000000f0
|
#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
|
#define RG_TR_LPF_KP_G_SFT 4
|
#define RG_TR_LPF_KP_G_HI 7
|
#define RG_TR_LPF_KP_G_SZ 4
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#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
|
#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
|
#define RG_TR_LPF_RATE_G_SFT 8
|
#define RG_TR_LPF_RATE_G_HI 29
|
#define RG_TR_LPF_RATE_G_SZ 22
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#define RG_CR_LPF_KI_G_MSK 0x00000007
|
#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
|
#define RG_CR_LPF_KI_G_SFT 0
|
#define RG_CR_LPF_KI_G_HI 2
|
#define RG_CR_LPF_KI_G_SZ 3
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#define RG_SYM_BOUND_CNT_MSK 0x00007f00
|
#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
|
#define RG_SYM_BOUND_CNT_SFT 8
|
#define RG_SYM_BOUND_CNT_HI 14
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#define RG_SYM_BOUND_CNT_SZ 7
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#define RG_XSCOR32_RATIO_MSK 0x007f0000
|
#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
|
#define RG_XSCOR32_RATIO_SFT 16
|
#define RG_XSCOR32_RATIO_HI 22
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#define RG_XSCOR32_RATIO_SZ 7
|
#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
|
#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
|
#define RG_ATCOR64_CNT_LMT_SFT 24
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#define RG_ATCOR64_CNT_LMT_HI 30
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#define RG_ATCOR64_CNT_LMT_SZ 7
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#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
|
#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
|
#define RG_ATCOR16_CNT_LMT2_SFT 8
|
#define RG_ATCOR16_CNT_LMT2_HI 14
|
#define RG_ATCOR16_CNT_LMT2_SZ 7
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#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
|
#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
|
#define RG_ATCOR16_CNT_LMT1_SFT 16
|
#define RG_ATCOR16_CNT_LMT1_HI 22
|
#define RG_ATCOR16_CNT_LMT1_SZ 7
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#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
|
#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
|
#define RG_ATCOR16_RATIO_SB_SFT 24
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#define RG_ATCOR16_RATIO_SB_HI 30
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#define RG_ATCOR16_RATIO_SB_SZ 7
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#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
|
#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
|
#define RG_XSCOR64_CNT_LMT2_SFT 16
|
#define RG_XSCOR64_CNT_LMT2_HI 22
|
#define RG_XSCOR64_CNT_LMT2_SZ 7
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#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
|
#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
|
#define RG_XSCOR64_CNT_LMT1_SFT 24
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#define RG_XSCOR64_CNT_LMT1_HI 30
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#define RG_XSCOR64_CNT_LMT1_SZ 7
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#define RG_RX_FFT_SCALE_MSK 0x000003ff
|
#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
|
#define RG_RX_FFT_SCALE_SFT 0
|
#define RG_RX_FFT_SCALE_HI 9
|
#define RG_RX_FFT_SCALE_SZ 10
|
#define RG_VITERBI_AB_SWAP_MSK 0x00010000
|
#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
|
#define RG_VITERBI_AB_SWAP_SFT 16
|
#define RG_VITERBI_AB_SWAP_HI 16
|
#define RG_VITERBI_AB_SWAP_SZ 1
|
#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
|
#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
|
#define RG_ATCOR16_CNT_TH_SFT 24
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#define RG_ATCOR16_CNT_TH_HI 27
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#define RG_ATCOR16_CNT_TH_SZ 4
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#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
|
#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
|
#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
|
#define RG_NORMSQUARE_LOW_SNR_7_HI 7
|
#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
|
#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
|
#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
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#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
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#define RG_NORMSQUARE_LOW_SNR_6_HI 15
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#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
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#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
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#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
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#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
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#define RG_NORMSQUARE_LOW_SNR_5_HI 23
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#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
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#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
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#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
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#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
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#define RG_NORMSQUARE_LOW_SNR_4_HI 31
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#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
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#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
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#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
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#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
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#define RG_NORMSQUARE_LOW_SNR_8_HI 31
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#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
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#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
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#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
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#define RG_NORMSQUARE_SNR_3_SFT 0
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#define RG_NORMSQUARE_SNR_3_HI 7
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#define RG_NORMSQUARE_SNR_3_SZ 8
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#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
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#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
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#define RG_NORMSQUARE_SNR_2_SFT 8
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#define RG_NORMSQUARE_SNR_2_HI 15
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#define RG_NORMSQUARE_SNR_2_SZ 8
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#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
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#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
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#define RG_NORMSQUARE_SNR_1_SFT 16
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#define RG_NORMSQUARE_SNR_1_HI 23
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#define RG_NORMSQUARE_SNR_1_SZ 8
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#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
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#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
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#define RG_NORMSQUARE_SNR_0_SFT 24
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#define RG_NORMSQUARE_SNR_0_HI 31
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#define RG_NORMSQUARE_SNR_0_SZ 8
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#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
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#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
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#define RG_NORMSQUARE_SNR_7_SFT 0
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#define RG_NORMSQUARE_SNR_7_HI 7
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#define RG_NORMSQUARE_SNR_7_SZ 8
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#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
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#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
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#define RG_NORMSQUARE_SNR_6_SFT 8
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#define RG_NORMSQUARE_SNR_6_HI 15
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#define RG_NORMSQUARE_SNR_6_SZ 8
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#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
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#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
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#define RG_NORMSQUARE_SNR_5_SFT 16
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#define RG_NORMSQUARE_SNR_5_HI 23
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#define RG_NORMSQUARE_SNR_5_SZ 8
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#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
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#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
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#define RG_NORMSQUARE_SNR_4_SFT 24
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#define RG_NORMSQUARE_SNR_4_HI 31
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#define RG_NORMSQUARE_SNR_4_SZ 8
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#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
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#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
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#define RG_NORMSQUARE_SNR_8_SFT 24
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#define RG_NORMSQUARE_SNR_8_HI 31
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#define RG_NORMSQUARE_SNR_8_SZ 8
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#define RG_SNR_TH_64QAM_MSK 0x0000007f
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#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
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#define RG_SNR_TH_64QAM_SFT 0
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#define RG_SNR_TH_64QAM_HI 6
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#define RG_SNR_TH_64QAM_SZ 7
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#define RG_SNR_TH_16QAM_MSK 0x00007f00
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#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
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#define RG_SNR_TH_16QAM_SFT 8
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#define RG_SNR_TH_16QAM_HI 14
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#define RG_SNR_TH_16QAM_SZ 7
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#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
|
#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
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#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
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#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
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#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
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#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
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#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
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#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
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#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
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#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
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#define RG_SYM_BOUND_METHOD_MSK 0x00030000
|
#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
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#define RG_SYM_BOUND_METHOD_SFT 16
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#define RG_SYM_BOUND_METHOD_HI 17
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#define RG_SYM_BOUND_METHOD_SZ 2
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#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
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#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
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#define RG_PWRON_DLY_TH_11GN_SFT 0
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#define RG_PWRON_DLY_TH_11GN_HI 7
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#define RG_PWRON_DLY_TH_11GN_SZ 8
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#define RG_SB_START_CNT_MSK 0x00007f00
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#define RG_SB_START_CNT_I_MSK 0xffff80ff
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#define RG_SB_START_CNT_SFT 8
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#define RG_SB_START_CNT_HI 14
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#define RG_SB_START_CNT_SZ 7
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#define RG_POW16_CNT_TH_MSK 0x000000f0
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#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
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#define RG_POW16_CNT_TH_SFT 4
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#define RG_POW16_CNT_TH_HI 7
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#define RG_POW16_CNT_TH_SZ 4
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#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
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#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
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#define RG_POW16_SHORT_CNT_LMT_SFT 8
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#define RG_POW16_SHORT_CNT_LMT_HI 10
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#define RG_POW16_SHORT_CNT_LMT_SZ 3
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#define RG_POW16_TH_L_MSK 0x7f000000
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#define RG_POW16_TH_L_I_MSK 0x80ffffff
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#define RG_POW16_TH_L_SFT 24
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#define RG_POW16_TH_L_HI 30
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#define RG_POW16_TH_L_SZ 7
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#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
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#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
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#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
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#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
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#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
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#define RG_XSCOR16_RATIO_MSK 0x00007f00
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#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
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#define RG_XSCOR16_RATIO_SFT 8
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#define RG_XSCOR16_RATIO_HI 14
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#define RG_XSCOR16_RATIO_SZ 7
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#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
|
#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
|
#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
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#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
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#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
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#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
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#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
|
#define RG_ATCOR16_RATIO_CCD_SFT 24
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#define RG_ATCOR16_RATIO_CCD_HI 30
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#define RG_ATCOR16_RATIO_CCD_SZ 7
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#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
|
#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
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#define RG_ATCOR64_ACC_LMT_SFT 0
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#define RG_ATCOR64_ACC_LMT_HI 6
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#define RG_ATCOR64_ACC_LMT_SZ 7
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#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
|
#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
|
#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
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#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
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#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
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#define RG_VITERBI_TB_BITS_MSK 0xff000000
|
#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
|
#define RG_VITERBI_TB_BITS_SFT 24
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#define RG_VITERBI_TB_BITS_HI 31
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#define RG_VITERBI_TB_BITS_SZ 8
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#define RG_CR_CNT_UPDATE_MSK 0x000000ff
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#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
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#define RG_CR_CNT_UPDATE_SFT 0
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#define RG_CR_CNT_UPDATE_HI 7
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#define RG_CR_CNT_UPDATE_SZ 8
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#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
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#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
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#define RG_TR_CNT_UPDATE_SFT 16
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#define RG_TR_CNT_UPDATE_HI 23
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#define RG_TR_CNT_UPDATE_SZ 8
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#define RG_BYPASS_CPE_MA_MSK 0x00000010
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#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
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#define RG_BYPASS_CPE_MA_SFT 4
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#define RG_BYPASS_CPE_MA_HI 4
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#define RG_BYPASS_CPE_MA_SZ 1
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#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
|
#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
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#define RG_PILOT_BNDRY_SHIFT_SFT 8
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#define RG_PILOT_BNDRY_SHIFT_HI 10
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#define RG_PILOT_BNDRY_SHIFT_SZ 3
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#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
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#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
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#define RG_EQ_SHORT_GI_SHIFT_SFT 12
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#define RG_EQ_SHORT_GI_SHIFT_HI 14
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#define RG_EQ_SHORT_GI_SHIFT_SZ 3
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#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
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#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
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#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
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#define RG_FFT_WDW_SHORT_SHIFT_HI 18
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#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
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#define RG_CHSMTH_COEF_MSK 0x00030000
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#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
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#define RG_CHSMTH_COEF_SFT 16
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#define RG_CHSMTH_COEF_HI 17
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#define RG_CHSMTH_COEF_SZ 2
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#define RG_CHSMTH_EN_MSK 0x00040000
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#define RG_CHSMTH_EN_I_MSK 0xfffbffff
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#define RG_CHSMTH_EN_SFT 18
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#define RG_CHSMTH_EN_HI 18
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#define RG_CHSMTH_EN_SZ 1
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#define RG_CHEST_DD_FACTOR_MSK 0x07000000
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#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
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#define RG_CHEST_DD_FACTOR_SFT 24
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#define RG_CHEST_DD_FACTOR_HI 26
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#define RG_CHEST_DD_FACTOR_SZ 3
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#define RG_CH_UPDATE_MSK 0x80000000
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#define RG_CH_UPDATE_I_MSK 0x7fffffff
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#define RG_CH_UPDATE_SFT 31
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#define RG_CH_UPDATE_HI 31
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#define RG_CH_UPDATE_SZ 1
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#define RG_FMT_DET_MM_TH_MSK 0x000000ff
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#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
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#define RG_FMT_DET_MM_TH_SFT 0
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#define RG_FMT_DET_MM_TH_HI 7
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#define RG_FMT_DET_MM_TH_SZ 8
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#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
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#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
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#define RG_FMT_DET_GF_TH_SFT 8
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#define RG_FMT_DET_GF_TH_HI 15
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#define RG_FMT_DET_GF_TH_SZ 8
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#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
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#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
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#define RG_DO_NOT_CHECK_L_RATE_SFT 25
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#define RG_DO_NOT_CHECK_L_RATE_HI 25
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#define RG_DO_NOT_CHECK_L_RATE_SZ 1
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#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
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#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
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#define RG_FMT_DET_LENGTH_TH_SFT 0
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#define RG_FMT_DET_LENGTH_TH_HI 15
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#define RG_FMT_DET_LENGTH_TH_SZ 16
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#define RG_L_LENGTH_MAX_MSK 0xffff0000
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#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
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#define RG_L_LENGTH_MAX_SFT 16
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#define RG_L_LENGTH_MAX_HI 31
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#define RG_L_LENGTH_MAX_SZ 16
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#define RG_TX_TIME_EXT_MSK 0x000000ff
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#define RG_TX_TIME_EXT_I_MSK 0xffffff00
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#define RG_TX_TIME_EXT_SFT 0
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#define RG_TX_TIME_EXT_HI 7
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#define RG_TX_TIME_EXT_SZ 8
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#define RG_MAC_DES_SPACE_MSK 0x00f00000
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#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
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#define RG_MAC_DES_SPACE_SFT 20
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#define RG_MAC_DES_SPACE_HI 23
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#define RG_MAC_DES_SPACE_SZ 4
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#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
|
#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
|
#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
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#define RG_TR_LPF_STBC_GF_KI_G_HI 3
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#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
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#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
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#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
|
#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
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#define RG_TR_LPF_STBC_GF_KP_G_HI 7
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#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
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#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
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#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
|
#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
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#define RG_TR_LPF_STBC_MF_KI_G_HI 11
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#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
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#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
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#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
|
#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
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#define RG_TR_LPF_STBC_MF_KP_G_HI 15
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#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
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#define RG_MODE_REG_IN_80_MSK 0x0001ffff
|
#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
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#define RG_MODE_REG_IN_80_SFT 0
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#define RG_MODE_REG_IN_80_HI 16
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#define RG_MODE_REG_IN_80_SZ 17
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#define RG_PARALLEL_DR_80_MSK 0x00100000
|
#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
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#define RG_PARALLEL_DR_80_SFT 20
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#define RG_PARALLEL_DR_80_HI 20
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#define RG_PARALLEL_DR_80_SZ 1
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#define RG_MBRUN_80_MSK 0x01000000
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#define RG_MBRUN_80_I_MSK 0xfeffffff
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#define RG_MBRUN_80_SFT 24
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#define RG_MBRUN_80_HI 24
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#define RG_MBRUN_80_SZ 1
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#define RG_SHIFT_DR_80_MSK 0x10000000
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#define RG_SHIFT_DR_80_I_MSK 0xefffffff
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#define RG_SHIFT_DR_80_SFT 28
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#define RG_SHIFT_DR_80_HI 28
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#define RG_SHIFT_DR_80_SZ 1
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#define RG_MODE_REG_SI_80_MSK 0x20000000
|
#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
|
#define RG_MODE_REG_SI_80_SFT 29
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#define RG_MODE_REG_SI_80_HI 29
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#define RG_MODE_REG_SI_80_SZ 1
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#define RG_SIMULATION_MODE_80_MSK 0x40000000
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#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
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#define RG_SIMULATION_MODE_80_SFT 30
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#define RG_SIMULATION_MODE_80_HI 30
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#define RG_SIMULATION_MODE_80_SZ 1
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#define RG_DBIST_MODE_80_MSK 0x80000000
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#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
|
#define RG_DBIST_MODE_80_SFT 31
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#define RG_DBIST_MODE_80_HI 31
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#define RG_DBIST_MODE_80_SZ 1
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#define RG_MODE_REG_IN_64_MSK 0x0000ffff
|
#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
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#define RG_MODE_REG_IN_64_SFT 0
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#define RG_MODE_REG_IN_64_HI 15
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#define RG_MODE_REG_IN_64_SZ 16
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#define RG_PARALLEL_DR_64_MSK 0x00100000
|
#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
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#define RG_PARALLEL_DR_64_SFT 20
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#define RG_PARALLEL_DR_64_HI 20
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#define RG_PARALLEL_DR_64_SZ 1
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#define RG_MBRUN_64_MSK 0x01000000
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#define RG_MBRUN_64_I_MSK 0xfeffffff
|
#define RG_MBRUN_64_SFT 24
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#define RG_MBRUN_64_HI 24
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#define RG_MBRUN_64_SZ 1
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#define RG_SHIFT_DR_64_MSK 0x10000000
|
#define RG_SHIFT_DR_64_I_MSK 0xefffffff
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#define RG_SHIFT_DR_64_SFT 28
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#define RG_SHIFT_DR_64_HI 28
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#define RG_SHIFT_DR_64_SZ 1
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#define RG_MODE_REG_SI_64_MSK 0x20000000
|
#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
|
#define RG_MODE_REG_SI_64_SFT 29
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#define RG_MODE_REG_SI_64_HI 29
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#define RG_MODE_REG_SI_64_SZ 1
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#define RG_SIMULATION_MODE_64_MSK 0x40000000
|
#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
|
#define RG_SIMULATION_MODE_64_SFT 30
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#define RG_SIMULATION_MODE_64_HI 30
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#define RG_SIMULATION_MODE_64_SZ 1
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#define RG_DBIST_MODE_64_MSK 0x80000000
|
#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
|
#define RG_DBIST_MODE_64_SFT 31
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#define RG_DBIST_MODE_64_HI 31
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#define RG_DBIST_MODE_64_SZ 1
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#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
|
#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
|
#define RO_MODE_REG_OUT_80_SFT 0
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#define RO_MODE_REG_OUT_80_HI 16
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#define RO_MODE_REG_OUT_80_SZ 17
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#define RO_MODE_REG_SO_80_MSK 0x01000000
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#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
|
#define RO_MODE_REG_SO_80_SFT 24
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#define RO_MODE_REG_SO_80_HI 24
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#define RO_MODE_REG_SO_80_SZ 1
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#define RO_MONITOR_BUS_80_MSK 0x003fffff
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#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
|
#define RO_MONITOR_BUS_80_SFT 0
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#define RO_MONITOR_BUS_80_HI 21
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#define RO_MONITOR_BUS_80_SZ 22
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#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
|
#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
|
#define RO_MODE_REG_OUT_64_SFT 0
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#define RO_MODE_REG_OUT_64_HI 15
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#define RO_MODE_REG_OUT_64_SZ 16
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#define RO_MODE_REG_SO_64_MSK 0x01000000
|
#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
|
#define RO_MODE_REG_SO_64_SFT 24
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#define RO_MODE_REG_SO_64_HI 24
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#define RO_MODE_REG_SO_64_SZ 1
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#define RO_MONITOR_BUS_64_MSK 0x0007ffff
|
#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
|
#define RO_MONITOR_BUS_64_SFT 0
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#define RO_MONITOR_BUS_64_HI 18
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#define RO_MONITOR_BUS_64_SZ 19
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#define RO_SPECTRUM_DATA_MSK 0xffffffff
|
#define RO_SPECTRUM_DATA_I_MSK 0x00000000
|
#define RO_SPECTRUM_DATA_SFT 0
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#define RO_SPECTRUM_DATA_HI 31
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#define RO_SPECTRUM_DATA_SZ 32
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#define GN_SNR_MSK 0x0000007f
|
#define GN_SNR_I_MSK 0xffffff80
|
#define GN_SNR_SFT 0
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#define GN_SNR_HI 6
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#define GN_SNR_SZ 7
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#define GN_NOISE_PWR_MSK 0x00007f00
|
#define GN_NOISE_PWR_I_MSK 0xffff80ff
|
#define GN_NOISE_PWR_SFT 8
|
#define GN_NOISE_PWR_HI 14
|
#define GN_NOISE_PWR_SZ 7
|
#define GN_RCPI_MSK 0x007f0000
|
#define GN_RCPI_I_MSK 0xff80ffff
|
#define GN_RCPI_SFT 16
|
#define GN_RCPI_HI 22
|
#define GN_RCPI_SZ 7
|
#define GN_SIGNAL_PWR_MSK 0x7f000000
|
#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
|
#define GN_SIGNAL_PWR_SFT 24
|
#define GN_SIGNAL_PWR_HI 30
|
#define GN_SIGNAL_PWR_SZ 7
|
#define RO_FREQ_OS_LTS_MSK 0x00007fff
|
#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
|
#define RO_FREQ_OS_LTS_SFT 0
|
#define RO_FREQ_OS_LTS_HI 14
|
#define RO_FREQ_OS_LTS_SZ 15
|
#define CSTATE_MSK 0x000f0000
|
#define CSTATE_I_MSK 0xfff0ffff
|
#define CSTATE_SFT 16
|
#define CSTATE_HI 19
|
#define CSTATE_SZ 4
|
#define SIGNAL_FIELD0_MSK 0x00ffffff
|
#define SIGNAL_FIELD0_I_MSK 0xff000000
|
#define SIGNAL_FIELD0_SFT 0
|
#define SIGNAL_FIELD0_HI 23
|
#define SIGNAL_FIELD0_SZ 24
|
#define SIGNAL_FIELD1_MSK 0x00ffffff
|
#define SIGNAL_FIELD1_I_MSK 0xff000000
|
#define SIGNAL_FIELD1_SFT 0
|
#define SIGNAL_FIELD1_HI 23
|
#define SIGNAL_FIELD1_SZ 24
|
#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
|
#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
|
#define GN_PACKET_ERR_CNT_SFT 0
|
#define GN_PACKET_ERR_CNT_HI 15
|
#define GN_PACKET_ERR_CNT_SZ 16
|
#define GN_PACKET_CNT_MSK 0x0000ffff
|
#define GN_PACKET_CNT_I_MSK 0xffff0000
|
#define GN_PACKET_CNT_SFT 0
|
#define GN_PACKET_CNT_HI 15
|
#define GN_PACKET_CNT_SZ 16
|
#define GN_CCA_CNT_MSK 0xffff0000
|
#define GN_CCA_CNT_I_MSK 0x0000ffff
|
#define GN_CCA_CNT_SFT 16
|
#define GN_CCA_CNT_HI 31
|
#define GN_CCA_CNT_SZ 16
|
#define GN_LENGTH_FIELD_MSK 0x0000ffff
|
#define GN_LENGTH_FIELD_I_MSK 0xffff0000
|
#define GN_LENGTH_FIELD_SFT 0
|
#define GN_LENGTH_FIELD_HI 15
|
#define GN_LENGTH_FIELD_SZ 16
|
#define GN_SERVICE_FIELD_MSK 0xffff0000
|
#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
|
#define GN_SERVICE_FIELD_SFT 16
|
#define GN_SERVICE_FIELD_HI 31
|
#define GN_SERVICE_FIELD_SZ 16
|
#define RO_HT_MCS_40M_MSK 0x0000007f
|
#define RO_HT_MCS_40M_I_MSK 0xffffff80
|
#define RO_HT_MCS_40M_SFT 0
|
#define RO_HT_MCS_40M_HI 6
|
#define RO_HT_MCS_40M_SZ 7
|
#define RO_L_RATE_40M_MSK 0x00003f00
|
#define RO_L_RATE_40M_I_MSK 0xffffc0ff
|
#define RO_L_RATE_40M_SFT 8
|
#define RO_L_RATE_40M_HI 13
|
#define RO_L_RATE_40M_SZ 6
|
#define RG_DAGC_CNT_TH_MSK 0x00000003
|
#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
|
#define RG_DAGC_CNT_TH_SFT 0
|
#define RG_DAGC_CNT_TH_HI 1
|
#define RG_DAGC_CNT_TH_SZ 2
|
#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
|
#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
|
#define RG_PACKET_STAT_EN_11GN_SFT 20
|
#define RG_PACKET_STAT_EN_11GN_HI 20
|
#define RG_PACKET_STAT_EN_11GN_SZ 1
|
#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
|
#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
|
#define RX_PHY_11GN_SOFT_RST_N_SFT 0
|
#define RX_PHY_11GN_SOFT_RST_N_HI 0
|
#define RX_PHY_11GN_SOFT_RST_N_SZ 1
|
#define RG_RIFS_EN_MSK 0x00000002
|
#define RG_RIFS_EN_I_MSK 0xfffffffd
|
#define RG_RIFS_EN_SFT 1
|
#define RG_RIFS_EN_HI 1
|
#define RG_RIFS_EN_SZ 1
|
#define RG_STBC_EN_MSK 0x00000004
|
#define RG_STBC_EN_I_MSK 0xfffffffb
|
#define RG_STBC_EN_SFT 2
|
#define RG_STBC_EN_HI 2
|
#define RG_STBC_EN_SZ 1
|
#define RG_COR_SEL_MSK 0x00000008
|
#define RG_COR_SEL_I_MSK 0xfffffff7
|
#define RG_COR_SEL_SFT 3
|
#define RG_COR_SEL_HI 3
|
#define RG_COR_SEL_SZ 1
|
#define RG_INI_PHASE_MSK 0x00000030
|
#define RG_INI_PHASE_I_MSK 0xffffffcf
|
#define RG_INI_PHASE_SFT 4
|
#define RG_INI_PHASE_HI 5
|
#define RG_INI_PHASE_SZ 2
|
#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
|
#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
|
#define RG_HT_LTF_SEL_EQ_SFT 6
|
#define RG_HT_LTF_SEL_EQ_HI 6
|
#define RG_HT_LTF_SEL_EQ_SZ 1
|
#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
|
#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
|
#define RG_HT_LTF_SEL_PILOT_SFT 7
|
#define RG_HT_LTF_SEL_PILOT_HI 7
|
#define RG_HT_LTF_SEL_PILOT_SZ 1
|
#define RG_CCA_PWR_SEL_MSK 0x00000200
|
#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
|
#define RG_CCA_PWR_SEL_SFT 9
|
#define RG_CCA_PWR_SEL_HI 9
|
#define RG_CCA_PWR_SEL_SZ 1
|
#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
|
#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
|
#define RG_CCA_XSCOR_PWR_SEL_SFT 10
|
#define RG_CCA_XSCOR_PWR_SEL_HI 10
|
#define RG_CCA_XSCOR_PWR_SEL_SZ 1
|
#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
|
#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
|
#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
|
#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
|
#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
|
#define RG_DEBUG_SEL_MSK 0x0000f000
|
#define RG_DEBUG_SEL_I_MSK 0xffff0fff
|
#define RG_DEBUG_SEL_SFT 12
|
#define RG_DEBUG_SEL_HI 15
|
#define RG_DEBUG_SEL_SZ 4
|
#define RG_POST_CLK_EN_MSK 0x00010000
|
#define RG_POST_CLK_EN_I_MSK 0xfffeffff
|
#define RG_POST_CLK_EN_SFT 16
|
#define RG_POST_CLK_EN_HI 16
|
#define RG_POST_CLK_EN_SZ 1
|
#define IQCAL_RF_TX_EN_MSK 0x00000001
|
#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
|
#define IQCAL_RF_TX_EN_SFT 0
|
#define IQCAL_RF_TX_EN_HI 0
|
#define IQCAL_RF_TX_EN_SZ 1
|
#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
|
#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
|
#define IQCAL_RF_TX_PA_EN_SFT 1
|
#define IQCAL_RF_TX_PA_EN_HI 1
|
#define IQCAL_RF_TX_PA_EN_SZ 1
|
#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
|
#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
|
#define IQCAL_RF_TX_DAC_EN_SFT 2
|
#define IQCAL_RF_TX_DAC_EN_HI 2
|
#define IQCAL_RF_TX_DAC_EN_SZ 1
|
#define IQCAL_RF_RX_AGC_MSK 0x00000008
|
#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
|
#define IQCAL_RF_RX_AGC_SFT 3
|
#define IQCAL_RF_RX_AGC_HI 3
|
#define IQCAL_RF_RX_AGC_SZ 1
|
#define IQCAL_RF_PGAG_MSK 0x00000f00
|
#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
|
#define IQCAL_RF_PGAG_SFT 8
|
#define IQCAL_RF_PGAG_HI 11
|
#define IQCAL_RF_PGAG_SZ 4
|
#define IQCAL_RF_RFG_MSK 0x00003000
|
#define IQCAL_RF_RFG_I_MSK 0xffffcfff
|
#define IQCAL_RF_RFG_SFT 12
|
#define IQCAL_RF_RFG_HI 13
|
#define IQCAL_RF_RFG_SZ 2
|
#define RG_TONEGEN_FREQ_MSK 0x007f0000
|
#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
|
#define RG_TONEGEN_FREQ_SFT 16
|
#define RG_TONEGEN_FREQ_HI 22
|
#define RG_TONEGEN_FREQ_SZ 7
|
#define RG_TONEGEN_EN_MSK 0x00800000
|
#define RG_TONEGEN_EN_I_MSK 0xff7fffff
|
#define RG_TONEGEN_EN_SFT 23
|
#define RG_TONEGEN_EN_HI 23
|
#define RG_TONEGEN_EN_SZ 1
|
#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
|
#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
|
#define RG_TONEGEN_INIT_PH_SFT 24
|
#define RG_TONEGEN_INIT_PH_HI 30
|
#define RG_TONEGEN_INIT_PH_SZ 7
|
#define RG_TONEGEN2_FREQ_MSK 0x0000007f
|
#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
|
#define RG_TONEGEN2_FREQ_SFT 0
|
#define RG_TONEGEN2_FREQ_HI 6
|
#define RG_TONEGEN2_FREQ_SZ 7
|
#define RG_TONEGEN2_EN_MSK 0x00000080
|
#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
|
#define RG_TONEGEN2_EN_SFT 7
|
#define RG_TONEGEN2_EN_HI 7
|
#define RG_TONEGEN2_EN_SZ 1
|
#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
|
#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
|
#define RG_TONEGEN2_SCALE_SFT 8
|
#define RG_TONEGEN2_SCALE_HI 15
|
#define RG_TONEGEN2_SCALE_SZ 8
|
#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
|
#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
|
#define RG_TXIQ_CLP_THD_I_SFT 0
|
#define RG_TXIQ_CLP_THD_I_HI 9
|
#define RG_TXIQ_CLP_THD_I_SZ 10
|
#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
|
#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
|
#define RG_TXIQ_CLP_THD_Q_SFT 16
|
#define RG_TXIQ_CLP_THD_Q_HI 25
|
#define RG_TXIQ_CLP_THD_Q_SZ 10
|
#define RG_TX_I_SCALE_MSK 0x000000ff
|
#define RG_TX_I_SCALE_I_MSK 0xffffff00
|
#define RG_TX_I_SCALE_SFT 0
|
#define RG_TX_I_SCALE_HI 7
|
#define RG_TX_I_SCALE_SZ 8
|
#define RG_TX_Q_SCALE_MSK 0x0000ff00
|
#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
|
#define RG_TX_Q_SCALE_SFT 8
|
#define RG_TX_Q_SCALE_HI 15
|
#define RG_TX_Q_SCALE_SZ 8
|
#define RG_TX_IQ_SWP_MSK 0x00010000
|
#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
|
#define RG_TX_IQ_SWP_SFT 16
|
#define RG_TX_IQ_SWP_HI 16
|
#define RG_TX_IQ_SWP_SZ 1
|
#define RG_TX_SGN_OUT_MSK 0x00020000
|
#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
|
#define RG_TX_SGN_OUT_SFT 17
|
#define RG_TX_SGN_OUT_HI 17
|
#define RG_TX_SGN_OUT_SZ 1
|
#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
|
#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
|
#define RG_TXIQ_EMU_IDX_SFT 18
|
#define RG_TXIQ_EMU_IDX_HI 21
|
#define RG_TXIQ_EMU_IDX_SZ 4
|
#define RG_TX_IQ_SRC_MSK 0x03000000
|
#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
|
#define RG_TX_IQ_SRC_SFT 24
|
#define RG_TX_IQ_SRC_HI 25
|
#define RG_TX_IQ_SRC_SZ 2
|
#define RG_TX_I_DC_MSK 0x000003ff
|
#define RG_TX_I_DC_I_MSK 0xfffffc00
|
#define RG_TX_I_DC_SFT 0
|
#define RG_TX_I_DC_HI 9
|
#define RG_TX_I_DC_SZ 10
|
#define RG_TX_Q_DC_MSK 0x03ff0000
|
#define RG_TX_Q_DC_I_MSK 0xfc00ffff
|
#define RG_TX_Q_DC_SFT 16
|
#define RG_TX_Q_DC_HI 25
|
#define RG_TX_Q_DC_SZ 10
|
#define RG_TX_IQ_THETA_MSK 0x0000001f
|
#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
|
#define RG_TX_IQ_THETA_SFT 0
|
#define RG_TX_IQ_THETA_HI 4
|
#define RG_TX_IQ_THETA_SZ 5
|
#define RG_TX_IQ_ALPHA_MSK 0x00001f00
|
#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
|
#define RG_TX_IQ_ALPHA_SFT 8
|
#define RG_TX_IQ_ALPHA_HI 12
|
#define RG_TX_IQ_ALPHA_SZ 5
|
#define RG_TXIQ_NOSHRINK_MSK 0x00002000
|
#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
|
#define RG_TXIQ_NOSHRINK_SFT 13
|
#define RG_TXIQ_NOSHRINK_HI 13
|
#define RG_TXIQ_NOSHRINK_SZ 1
|
#define RG_TX_I_OFFSET_MSK 0x00ff0000
|
#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
|
#define RG_TX_I_OFFSET_SFT 16
|
#define RG_TX_I_OFFSET_HI 23
|
#define RG_TX_I_OFFSET_SZ 8
|
#define RG_TX_Q_OFFSET_MSK 0xff000000
|
#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
|
#define RG_TX_Q_OFFSET_SFT 24
|
#define RG_TX_Q_OFFSET_HI 31
|
#define RG_TX_Q_OFFSET_SZ 8
|
#define RG_RX_IQ_THETA_MSK 0x0000001f
|
#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
|
#define RG_RX_IQ_THETA_SFT 0
|
#define RG_RX_IQ_THETA_HI 4
|
#define RG_RX_IQ_THETA_SZ 5
|
#define RG_RX_IQ_ALPHA_MSK 0x00001f00
|
#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
|
#define RG_RX_IQ_ALPHA_SFT 8
|
#define RG_RX_IQ_ALPHA_HI 12
|
#define RG_RX_IQ_ALPHA_SZ 5
|
#define RG_RXIQ_NOSHRINK_MSK 0x00002000
|
#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
|
#define RG_RXIQ_NOSHRINK_SFT 13
|
#define RG_RXIQ_NOSHRINK_HI 13
|
#define RG_RXIQ_NOSHRINK_SZ 1
|
#define RG_MA_DPTH_MSK 0x0000000f
|
#define RG_MA_DPTH_I_MSK 0xfffffff0
|
#define RG_MA_DPTH_SFT 0
|
#define RG_MA_DPTH_HI 3
|
#define RG_MA_DPTH_SZ 4
|
#define RG_INTG_PH_MSK 0x000003f0
|
#define RG_INTG_PH_I_MSK 0xfffffc0f
|
#define RG_INTG_PH_SFT 4
|
#define RG_INTG_PH_HI 9
|
#define RG_INTG_PH_SZ 6
|
#define RG_INTG_PRD_MSK 0x00001c00
|
#define RG_INTG_PRD_I_MSK 0xffffe3ff
|
#define RG_INTG_PRD_SFT 10
|
#define RG_INTG_PRD_HI 12
|
#define RG_INTG_PRD_SZ 3
|
#define RG_INTG_MU_MSK 0x00006000
|
#define RG_INTG_MU_I_MSK 0xffff9fff
|
#define RG_INTG_MU_SFT 13
|
#define RG_INTG_MU_HI 14
|
#define RG_INTG_MU_SZ 2
|
#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
|
#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
|
#define RG_IQCAL_SPRM_SELQ_SFT 16
|
#define RG_IQCAL_SPRM_SELQ_HI 16
|
#define RG_IQCAL_SPRM_SELQ_SZ 1
|
#define RG_IQCAL_SPRM_EN_MSK 0x00020000
|
#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
|
#define RG_IQCAL_SPRM_EN_SFT 17
|
#define RG_IQCAL_SPRM_EN_HI 17
|
#define RG_IQCAL_SPRM_EN_SZ 1
|
#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
|
#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
|
#define RG_IQCAL_SPRM_FREQ_SFT 18
|
#define RG_IQCAL_SPRM_FREQ_HI 23
|
#define RG_IQCAL_SPRM_FREQ_SZ 6
|
#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
|
#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
|
#define RG_IQCAL_IQCOL_EN_SFT 24
|
#define RG_IQCAL_IQCOL_EN_HI 24
|
#define RG_IQCAL_IQCOL_EN_SZ 1
|
#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
|
#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
|
#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
|
#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
|
#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
|
#define RG_IQCAL_DC_EN_MSK 0x04000000
|
#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
|
#define RG_IQCAL_DC_EN_SFT 26
|
#define RG_IQCAL_DC_EN_HI 26
|
#define RG_IQCAL_DC_EN_SZ 1
|
#define RG_PHEST_STBY_MSK 0x08000000
|
#define RG_PHEST_STBY_I_MSK 0xf7ffffff
|
#define RG_PHEST_STBY_SFT 27
|
#define RG_PHEST_STBY_HI 27
|
#define RG_PHEST_STBY_SZ 1
|
#define RG_PHEST_EN_MSK 0x10000000
|
#define RG_PHEST_EN_I_MSK 0xefffffff
|
#define RG_PHEST_EN_SFT 28
|
#define RG_PHEST_EN_HI 28
|
#define RG_PHEST_EN_SZ 1
|
#define RG_GP_DIV_EN_MSK 0x20000000
|
#define RG_GP_DIV_EN_I_MSK 0xdfffffff
|
#define RG_GP_DIV_EN_SFT 29
|
#define RG_GP_DIV_EN_HI 29
|
#define RG_GP_DIV_EN_SZ 1
|
#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
|
#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
|
#define RG_DPD_GAIN_EST_EN_SFT 30
|
#define RG_DPD_GAIN_EST_EN_HI 30
|
#define RG_DPD_GAIN_EST_EN_SZ 1
|
#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
|
#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
|
#define RG_IQCAL_MULT_OP0_SFT 0
|
#define RG_IQCAL_MULT_OP0_HI 9
|
#define RG_IQCAL_MULT_OP0_SZ 10
|
#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
|
#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
|
#define RG_IQCAL_MULT_OP1_SFT 16
|
#define RG_IQCAL_MULT_OP1_HI 25
|
#define RG_IQCAL_MULT_OP1_SZ 10
|
#define RO_IQCAL_O_MSK 0x000fffff
|
#define RO_IQCAL_O_I_MSK 0xfff00000
|
#define RO_IQCAL_O_SFT 0
|
#define RO_IQCAL_O_HI 19
|
#define RO_IQCAL_O_SZ 20
|
#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
|
#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
|
#define RO_IQCAL_SPRM_RDY_SFT 20
|
#define RO_IQCAL_SPRM_RDY_HI 20
|
#define RO_IQCAL_SPRM_RDY_SZ 1
|
#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
|
#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
|
#define RO_IQCAL_IQCOL_RDY_SFT 21
|
#define RO_IQCAL_IQCOL_RDY_HI 21
|
#define RO_IQCAL_IQCOL_RDY_SZ 1
|
#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
|
#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
|
#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
|
#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
|
#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
|
#define RO_IQCAL_DC_RDY_MSK 0x00800000
|
#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
|
#define RO_IQCAL_DC_RDY_SFT 23
|
#define RO_IQCAL_DC_RDY_HI 23
|
#define RO_IQCAL_DC_RDY_SZ 1
|
#define RO_IQCAL_MULT_RDY_MSK 0x01000000
|
#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
|
#define RO_IQCAL_MULT_RDY_SFT 24
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#define RO_IQCAL_MULT_RDY_HI 24
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#define RO_IQCAL_MULT_RDY_SZ 1
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#define RO_FFT_ENRG_RDY_MSK 0x02000000
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#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
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#define RO_FFT_ENRG_RDY_SFT 25
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#define RO_FFT_ENRG_RDY_HI 25
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#define RO_FFT_ENRG_RDY_SZ 1
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#define RO_PHEST_RDY_MSK 0x04000000
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#define RO_PHEST_RDY_I_MSK 0xfbffffff
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#define RO_PHEST_RDY_SFT 26
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#define RO_PHEST_RDY_HI 26
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#define RO_PHEST_RDY_SZ 1
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#define RO_GP_DIV_RDY_MSK 0x08000000
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#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
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#define RO_GP_DIV_RDY_SFT 27
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#define RO_GP_DIV_RDY_HI 27
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#define RO_GP_DIV_RDY_SZ 1
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#define RO_GAIN_EST_RDY_MSK 0x10000000
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#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
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#define RO_GAIN_EST_RDY_SFT 28
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#define RO_GAIN_EST_RDY_HI 28
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#define RO_GAIN_EST_RDY_SZ 1
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#define RO_AMP_O_MSK 0x000001ff
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#define RO_AMP_O_I_MSK 0xfffffe00
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#define RO_AMP_O_SFT 0
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#define RO_AMP_O_HI 8
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#define RO_AMP_O_SZ 9
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#define RG_RX_I_SCALE_MSK 0x000000ff
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#define RG_RX_I_SCALE_I_MSK 0xffffff00
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#define RG_RX_I_SCALE_SFT 0
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#define RG_RX_I_SCALE_HI 7
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#define RG_RX_I_SCALE_SZ 8
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#define RG_RX_Q_SCALE_MSK 0x0000ff00
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#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
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#define RG_RX_Q_SCALE_SFT 8
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#define RG_RX_Q_SCALE_HI 15
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#define RG_RX_Q_SCALE_SZ 8
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#define RG_RX_I_OFFSET_MSK 0x00ff0000
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#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
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#define RG_RX_I_OFFSET_SFT 16
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#define RG_RX_I_OFFSET_HI 23
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#define RG_RX_I_OFFSET_SZ 8
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#define RG_RX_Q_OFFSET_MSK 0xff000000
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#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
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#define RG_RX_Q_OFFSET_SFT 24
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#define RG_RX_Q_OFFSET_HI 31
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#define RG_RX_Q_OFFSET_SZ 8
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#define RG_RX_IQ_SWP_MSK 0x00000001
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#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
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#define RG_RX_IQ_SWP_SFT 0
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#define RG_RX_IQ_SWP_HI 0
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#define RG_RX_IQ_SWP_SZ 1
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#define RG_RX_SGN_IN_MSK 0x00000002
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#define RG_RX_SGN_IN_I_MSK 0xfffffffd
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#define RG_RX_SGN_IN_SFT 1
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#define RG_RX_SGN_IN_HI 1
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#define RG_RX_SGN_IN_SZ 1
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#define RG_RX_IQ_SRC_MSK 0x0000000c
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#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
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#define RG_RX_IQ_SRC_SFT 2
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#define RG_RX_IQ_SRC_HI 3
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#define RG_RX_IQ_SRC_SZ 2
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#define RG_ACI_GAIN_MSK 0x00000ff0
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#define RG_ACI_GAIN_I_MSK 0xfffff00f
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#define RG_ACI_GAIN_SFT 4
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#define RG_ACI_GAIN_HI 11
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#define RG_ACI_GAIN_SZ 8
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#define RG_FFT_EN_MSK 0x00001000
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#define RG_FFT_EN_I_MSK 0xffffefff
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#define RG_FFT_EN_SFT 12
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#define RG_FFT_EN_HI 12
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#define RG_FFT_EN_SZ 1
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#define RG_FFT_MOD_MSK 0x00002000
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#define RG_FFT_MOD_I_MSK 0xffffdfff
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#define RG_FFT_MOD_SFT 13
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#define RG_FFT_MOD_HI 13
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#define RG_FFT_MOD_SZ 1
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#define RG_FFT_SCALE_MSK 0x00ffc000
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#define RG_FFT_SCALE_I_MSK 0xff003fff
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#define RG_FFT_SCALE_SFT 14
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#define RG_FFT_SCALE_HI 23
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#define RG_FFT_SCALE_SZ 10
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#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
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#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
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#define RG_FFT_ENRG_FREQ_SFT 24
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#define RG_FFT_ENRG_FREQ_HI 29
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#define RG_FFT_ENRG_FREQ_SZ 6
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#define RG_FPGA_80M_PH_UP_MSK 0x40000000
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#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
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#define RG_FPGA_80M_PH_UP_SFT 30
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#define RG_FPGA_80M_PH_UP_HI 30
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#define RG_FPGA_80M_PH_UP_SZ 1
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#define RG_FPGA_80M_PH_STP_MSK 0x80000000
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#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
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#define RG_FPGA_80M_PH_STP_SFT 31
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#define RG_FPGA_80M_PH_STP_HI 31
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#define RG_FPGA_80M_PH_STP_SZ 1
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#define RG_ADC2LA_SEL_MSK 0x00000001
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#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
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#define RG_ADC2LA_SEL_SFT 0
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#define RG_ADC2LA_SEL_HI 0
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#define RG_ADC2LA_SEL_SZ 1
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#define RG_ADC2LA_CLKPH_MSK 0x00000002
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#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
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#define RG_ADC2LA_CLKPH_SFT 1
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#define RG_ADC2LA_CLKPH_HI 1
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#define RG_ADC2LA_CLKPH_SZ 1
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#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
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#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
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#define RG_RXIQ_EMU_IDX_SFT 0
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#define RG_RXIQ_EMU_IDX_HI 3
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#define RG_RXIQ_EMU_IDX_SZ 4
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#define RG_IQCAL_BP_ACI_MSK 0x00000010
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#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
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#define RG_IQCAL_BP_ACI_SFT 4
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#define RG_IQCAL_BP_ACI_HI 4
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#define RG_IQCAL_BP_ACI_SZ 1
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#define RG_DPD_AM_EN_MSK 0x00000001
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#define RG_DPD_AM_EN_I_MSK 0xfffffffe
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#define RG_DPD_AM_EN_SFT 0
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#define RG_DPD_AM_EN_HI 0
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#define RG_DPD_AM_EN_SZ 1
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#define RG_DPD_PM_EN_MSK 0x00000002
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#define RG_DPD_PM_EN_I_MSK 0xfffffffd
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#define RG_DPD_PM_EN_SFT 1
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#define RG_DPD_PM_EN_HI 1
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#define RG_DPD_PM_EN_SZ 1
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#define RG_DPD_PM_AMSEL_MSK 0x00000004
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#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
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#define RG_DPD_PM_AMSEL_SFT 2
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#define RG_DPD_PM_AMSEL_HI 2
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#define RG_DPD_PM_AMSEL_SZ 1
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#define RG_DPD_020_GAIN_MSK 0x000003ff
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#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_020_GAIN_SFT 0
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#define RG_DPD_020_GAIN_HI 9
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#define RG_DPD_020_GAIN_SZ 10
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#define RG_DPD_040_GAIN_MSK 0x03ff0000
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#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_040_GAIN_SFT 16
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#define RG_DPD_040_GAIN_HI 25
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#define RG_DPD_040_GAIN_SZ 10
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#define RG_DPD_060_GAIN_MSK 0x000003ff
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#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_060_GAIN_SFT 0
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#define RG_DPD_060_GAIN_HI 9
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#define RG_DPD_060_GAIN_SZ 10
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#define RG_DPD_080_GAIN_MSK 0x03ff0000
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#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_080_GAIN_SFT 16
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#define RG_DPD_080_GAIN_HI 25
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#define RG_DPD_080_GAIN_SZ 10
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#define RG_DPD_0A0_GAIN_MSK 0x000003ff
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#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_0A0_GAIN_SFT 0
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#define RG_DPD_0A0_GAIN_HI 9
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#define RG_DPD_0A0_GAIN_SZ 10
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#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
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#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_0C0_GAIN_SFT 16
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#define RG_DPD_0C0_GAIN_HI 25
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#define RG_DPD_0C0_GAIN_SZ 10
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#define RG_DPD_0D0_GAIN_MSK 0x000003ff
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#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_0D0_GAIN_SFT 0
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#define RG_DPD_0D0_GAIN_HI 9
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#define RG_DPD_0D0_GAIN_SZ 10
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#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
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#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_0E0_GAIN_SFT 16
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#define RG_DPD_0E0_GAIN_HI 25
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#define RG_DPD_0E0_GAIN_SZ 10
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#define RG_DPD_0F0_GAIN_MSK 0x000003ff
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#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_0F0_GAIN_SFT 0
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#define RG_DPD_0F0_GAIN_HI 9
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#define RG_DPD_0F0_GAIN_SZ 10
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#define RG_DPD_100_GAIN_MSK 0x03ff0000
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#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_100_GAIN_SFT 16
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#define RG_DPD_100_GAIN_HI 25
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#define RG_DPD_100_GAIN_SZ 10
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#define RG_DPD_110_GAIN_MSK 0x000003ff
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#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_110_GAIN_SFT 0
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#define RG_DPD_110_GAIN_HI 9
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#define RG_DPD_110_GAIN_SZ 10
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#define RG_DPD_120_GAIN_MSK 0x03ff0000
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#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_120_GAIN_SFT 16
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#define RG_DPD_120_GAIN_HI 25
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#define RG_DPD_120_GAIN_SZ 10
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#define RG_DPD_130_GAIN_MSK 0x000003ff
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#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_130_GAIN_SFT 0
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#define RG_DPD_130_GAIN_HI 9
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#define RG_DPD_130_GAIN_SZ 10
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#define RG_DPD_140_GAIN_MSK 0x03ff0000
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#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_140_GAIN_SFT 16
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#define RG_DPD_140_GAIN_HI 25
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#define RG_DPD_140_GAIN_SZ 10
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#define RG_DPD_150_GAIN_MSK 0x000003ff
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#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_150_GAIN_SFT 0
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#define RG_DPD_150_GAIN_HI 9
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#define RG_DPD_150_GAIN_SZ 10
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#define RG_DPD_160_GAIN_MSK 0x03ff0000
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#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_160_GAIN_SFT 16
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#define RG_DPD_160_GAIN_HI 25
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#define RG_DPD_160_GAIN_SZ 10
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#define RG_DPD_170_GAIN_MSK 0x000003ff
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#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_170_GAIN_SFT 0
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#define RG_DPD_170_GAIN_HI 9
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#define RG_DPD_170_GAIN_SZ 10
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#define RG_DPD_180_GAIN_MSK 0x03ff0000
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#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_180_GAIN_SFT 16
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#define RG_DPD_180_GAIN_HI 25
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#define RG_DPD_180_GAIN_SZ 10
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#define RG_DPD_190_GAIN_MSK 0x000003ff
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#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_190_GAIN_SFT 0
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#define RG_DPD_190_GAIN_HI 9
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#define RG_DPD_190_GAIN_SZ 10
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#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
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#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_1A0_GAIN_SFT 16
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#define RG_DPD_1A0_GAIN_HI 25
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#define RG_DPD_1A0_GAIN_SZ 10
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#define RG_DPD_1B0_GAIN_MSK 0x000003ff
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#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_1B0_GAIN_SFT 0
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#define RG_DPD_1B0_GAIN_HI 9
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#define RG_DPD_1B0_GAIN_SZ 10
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#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
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#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_1C0_GAIN_SFT 16
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#define RG_DPD_1C0_GAIN_HI 25
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#define RG_DPD_1C0_GAIN_SZ 10
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#define RG_DPD_1D0_GAIN_MSK 0x000003ff
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#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_1D0_GAIN_SFT 0
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#define RG_DPD_1D0_GAIN_HI 9
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#define RG_DPD_1D0_GAIN_SZ 10
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#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
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#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_1E0_GAIN_SFT 16
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#define RG_DPD_1E0_GAIN_HI 25
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#define RG_DPD_1E0_GAIN_SZ 10
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#define RG_DPD_1F0_GAIN_MSK 0x000003ff
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#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
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#define RG_DPD_1F0_GAIN_SFT 0
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#define RG_DPD_1F0_GAIN_HI 9
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#define RG_DPD_1F0_GAIN_SZ 10
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#define RG_DPD_200_GAIN_MSK 0x03ff0000
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#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
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#define RG_DPD_200_GAIN_SFT 16
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#define RG_DPD_200_GAIN_HI 25
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#define RG_DPD_200_GAIN_SZ 10
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#define RG_DPD_020_PH_MSK 0x00001fff
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#define RG_DPD_020_PH_I_MSK 0xffffe000
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#define RG_DPD_020_PH_SFT 0
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#define RG_DPD_020_PH_HI 12
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#define RG_DPD_020_PH_SZ 13
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#define RG_DPD_040_PH_MSK 0x1fff0000
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#define RG_DPD_040_PH_I_MSK 0xe000ffff
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#define RG_DPD_040_PH_SFT 16
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#define RG_DPD_040_PH_HI 28
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#define RG_DPD_040_PH_SZ 13
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#define RG_DPD_060_PH_MSK 0x00001fff
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#define RG_DPD_060_PH_I_MSK 0xffffe000
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#define RG_DPD_060_PH_SFT 0
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#define RG_DPD_060_PH_HI 12
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#define RG_DPD_060_PH_SZ 13
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#define RG_DPD_080_PH_MSK 0x1fff0000
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#define RG_DPD_080_PH_I_MSK 0xe000ffff
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#define RG_DPD_080_PH_SFT 16
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#define RG_DPD_080_PH_HI 28
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#define RG_DPD_080_PH_SZ 13
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#define RG_DPD_0A0_PH_MSK 0x00001fff
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#define RG_DPD_0A0_PH_I_MSK 0xffffe000
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#define RG_DPD_0A0_PH_SFT 0
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#define RG_DPD_0A0_PH_HI 12
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#define RG_DPD_0A0_PH_SZ 13
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#define RG_DPD_0C0_PH_MSK 0x1fff0000
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#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
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#define RG_DPD_0C0_PH_SFT 16
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#define RG_DPD_0C0_PH_HI 28
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#define RG_DPD_0C0_PH_SZ 13
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#define RG_DPD_0D0_PH_MSK 0x00001fff
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#define RG_DPD_0D0_PH_I_MSK 0xffffe000
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#define RG_DPD_0D0_PH_SFT 0
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#define RG_DPD_0D0_PH_HI 12
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#define RG_DPD_0D0_PH_SZ 13
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#define RG_DPD_0E0_PH_MSK 0x1fff0000
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#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
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#define RG_DPD_0E0_PH_SFT 16
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#define RG_DPD_0E0_PH_HI 28
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#define RG_DPD_0E0_PH_SZ 13
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#define RG_DPD_0F0_PH_MSK 0x00001fff
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#define RG_DPD_0F0_PH_I_MSK 0xffffe000
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#define RG_DPD_0F0_PH_SFT 0
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#define RG_DPD_0F0_PH_HI 12
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#define RG_DPD_0F0_PH_SZ 13
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#define RG_DPD_100_PH_MSK 0x1fff0000
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#define RG_DPD_100_PH_I_MSK 0xe000ffff
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#define RG_DPD_100_PH_SFT 16
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#define RG_DPD_100_PH_HI 28
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#define RG_DPD_100_PH_SZ 13
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#define RG_DPD_110_PH_MSK 0x00001fff
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#define RG_DPD_110_PH_I_MSK 0xffffe000
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#define RG_DPD_110_PH_SFT 0
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#define RG_DPD_110_PH_HI 12
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#define RG_DPD_110_PH_SZ 13
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#define RG_DPD_120_PH_MSK 0x1fff0000
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#define RG_DPD_120_PH_I_MSK 0xe000ffff
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#define RG_DPD_120_PH_SFT 16
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#define RG_DPD_120_PH_HI 28
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#define RG_DPD_120_PH_SZ 13
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#define RG_DPD_130_PH_MSK 0x00001fff
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#define RG_DPD_130_PH_I_MSK 0xffffe000
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#define RG_DPD_130_PH_SFT 0
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#define RG_DPD_130_PH_HI 12
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#define RG_DPD_130_PH_SZ 13
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#define RG_DPD_140_PH_MSK 0x1fff0000
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#define RG_DPD_140_PH_I_MSK 0xe000ffff
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#define RG_DPD_140_PH_SFT 16
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#define RG_DPD_140_PH_HI 28
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#define RG_DPD_140_PH_SZ 13
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#define RG_DPD_150_PH_MSK 0x00001fff
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#define RG_DPD_150_PH_I_MSK 0xffffe000
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#define RG_DPD_150_PH_SFT 0
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#define RG_DPD_150_PH_HI 12
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#define RG_DPD_150_PH_SZ 13
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#define RG_DPD_160_PH_MSK 0x1fff0000
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#define RG_DPD_160_PH_I_MSK 0xe000ffff
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#define RG_DPD_160_PH_SFT 16
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#define RG_DPD_160_PH_HI 28
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#define RG_DPD_160_PH_SZ 13
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#define RG_DPD_170_PH_MSK 0x00001fff
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#define RG_DPD_170_PH_I_MSK 0xffffe000
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#define RG_DPD_170_PH_SFT 0
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#define RG_DPD_170_PH_HI 12
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#define RG_DPD_170_PH_SZ 13
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#define RG_DPD_180_PH_MSK 0x1fff0000
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#define RG_DPD_180_PH_I_MSK 0xe000ffff
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#define RG_DPD_180_PH_SFT 16
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#define RG_DPD_180_PH_HI 28
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#define RG_DPD_180_PH_SZ 13
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#define RG_DPD_190_PH_MSK 0x00001fff
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#define RG_DPD_190_PH_I_MSK 0xffffe000
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#define RG_DPD_190_PH_SFT 0
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#define RG_DPD_190_PH_HI 12
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#define RG_DPD_190_PH_SZ 13
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#define RG_DPD_1A0_PH_MSK 0x1fff0000
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#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
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#define RG_DPD_1A0_PH_SFT 16
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#define RG_DPD_1A0_PH_HI 28
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#define RG_DPD_1A0_PH_SZ 13
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#define RG_DPD_1B0_PH_MSK 0x00001fff
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#define RG_DPD_1B0_PH_I_MSK 0xffffe000
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#define RG_DPD_1B0_PH_SFT 0
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#define RG_DPD_1B0_PH_HI 12
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#define RG_DPD_1B0_PH_SZ 13
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#define RG_DPD_1C0_PH_MSK 0x1fff0000
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#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
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#define RG_DPD_1C0_PH_SFT 16
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#define RG_DPD_1C0_PH_HI 28
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#define RG_DPD_1C0_PH_SZ 13
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#define RG_DPD_1D0_PH_MSK 0x00001fff
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#define RG_DPD_1D0_PH_I_MSK 0xffffe000
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#define RG_DPD_1D0_PH_SFT 0
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#define RG_DPD_1D0_PH_HI 12
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#define RG_DPD_1D0_PH_SZ 13
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#define RG_DPD_1E0_PH_MSK 0x1fff0000
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#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
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#define RG_DPD_1E0_PH_SFT 16
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#define RG_DPD_1E0_PH_HI 28
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#define RG_DPD_1E0_PH_SZ 13
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#define RG_DPD_1F0_PH_MSK 0x00001fff
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#define RG_DPD_1F0_PH_I_MSK 0xffffe000
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#define RG_DPD_1F0_PH_SFT 0
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#define RG_DPD_1F0_PH_HI 12
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#define RG_DPD_1F0_PH_SZ 13
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#define RG_DPD_200_PH_MSK 0x1fff0000
|
#define RG_DPD_200_PH_I_MSK 0xe000ffff
|
#define RG_DPD_200_PH_SFT 16
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#define RG_DPD_200_PH_HI 28
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#define RG_DPD_200_PH_SZ 13
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#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
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#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
|
#define RG_DPD_GAIN_EST_Y0_SFT 0
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#define RG_DPD_GAIN_EST_Y0_HI 8
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#define RG_DPD_GAIN_EST_Y0_SZ 9
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#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
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#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
|
#define RG_DPD_GAIN_EST_Y1_SFT 16
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#define RG_DPD_GAIN_EST_Y1_HI 24
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#define RG_DPD_GAIN_EST_Y1_SZ 9
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#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
|
#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
|
#define RG_DPD_LOOP_GAIN_SFT 0
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#define RG_DPD_LOOP_GAIN_HI 9
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#define RG_DPD_LOOP_GAIN_SZ 10
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#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
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#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
|
#define RG_DPD_GAIN_EST_X0_SFT 0
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#define RG_DPD_GAIN_EST_X0_HI 8
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#define RG_DPD_GAIN_EST_X0_SZ 9
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#define RO_DPD_GAIN_MSK 0x03ff0000
|
#define RO_DPD_GAIN_I_MSK 0xfc00ffff
|
#define RO_DPD_GAIN_SFT 16
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#define RO_DPD_GAIN_HI 25
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#define RO_DPD_GAIN_SZ 10
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#define TX_SCALE_11B_MSK 0x000000ff
|
#define TX_SCALE_11B_I_MSK 0xffffff00
|
#define TX_SCALE_11B_SFT 0
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#define TX_SCALE_11B_HI 7
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#define TX_SCALE_11B_SZ 8
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#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
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#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
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#define TX_SCALE_11B_P0D5_SFT 8
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#define TX_SCALE_11B_P0D5_HI 15
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#define TX_SCALE_11B_P0D5_SZ 8
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#define TX_SCALE_11G_MSK 0x00ff0000
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#define TX_SCALE_11G_I_MSK 0xff00ffff
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#define TX_SCALE_11G_SFT 16
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#define TX_SCALE_11G_HI 23
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#define TX_SCALE_11G_SZ 8
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#define TX_SCALE_11G_P0D5_MSK 0xff000000
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#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
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#define TX_SCALE_11G_P0D5_SFT 24
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#define TX_SCALE_11G_P0D5_HI 31
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#define TX_SCALE_11G_P0D5_SZ 8
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#define RG_EN_MANUAL_MSK 0x00000001
|
#define RG_EN_MANUAL_I_MSK 0xfffffffe
|
#define RG_EN_MANUAL_SFT 0
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#define RG_EN_MANUAL_HI 0
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#define RG_EN_MANUAL_SZ 1
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#define RG_TX_EN_MSK 0x00000002
|
#define RG_TX_EN_I_MSK 0xfffffffd
|
#define RG_TX_EN_SFT 1
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#define RG_TX_EN_HI 1
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#define RG_TX_EN_SZ 1
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#define RG_TX_PA_EN_MSK 0x00000004
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#define RG_TX_PA_EN_I_MSK 0xfffffffb
|
#define RG_TX_PA_EN_SFT 2
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#define RG_TX_PA_EN_HI 2
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#define RG_TX_PA_EN_SZ 1
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#define RG_TX_DAC_EN_MSK 0x00000008
|
#define RG_TX_DAC_EN_I_MSK 0xfffffff7
|
#define RG_TX_DAC_EN_SFT 3
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#define RG_TX_DAC_EN_HI 3
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#define RG_TX_DAC_EN_SZ 1
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#define RG_RX_AGC_MSK 0x00000010
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#define RG_RX_AGC_I_MSK 0xffffffef
|
#define RG_RX_AGC_SFT 4
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#define RG_RX_AGC_HI 4
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#define RG_RX_AGC_SZ 1
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#define RG_RX_GAIN_MANUAL_MSK 0x00000020
|
#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
|
#define RG_RX_GAIN_MANUAL_SFT 5
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#define RG_RX_GAIN_MANUAL_HI 5
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#define RG_RX_GAIN_MANUAL_SZ 1
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#define RG_RFG_MSK 0x000000c0
|
#define RG_RFG_I_MSK 0xffffff3f
|
#define RG_RFG_SFT 6
|
#define RG_RFG_HI 7
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#define RG_RFG_SZ 2
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#define RG_PGAG_MSK 0x00000f00
|
#define RG_PGAG_I_MSK 0xfffff0ff
|
#define RG_PGAG_SFT 8
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#define RG_PGAG_HI 11
|
#define RG_PGAG_SZ 4
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#define RG_MODE_MSK 0x00003000
|
#define RG_MODE_I_MSK 0xffffcfff
|
#define RG_MODE_SFT 12
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#define RG_MODE_HI 13
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#define RG_MODE_SZ 2
|
#define RG_EN_TX_TRSW_MSK 0x00004000
|
#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
|
#define RG_EN_TX_TRSW_SFT 14
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#define RG_EN_TX_TRSW_HI 14
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#define RG_EN_TX_TRSW_SZ 1
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#define RG_EN_SX_MSK 0x00008000
|
#define RG_EN_SX_I_MSK 0xffff7fff
|
#define RG_EN_SX_SFT 15
|
#define RG_EN_SX_HI 15
|
#define RG_EN_SX_SZ 1
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#define RG_EN_RX_LNA_MSK 0x00010000
|
#define RG_EN_RX_LNA_I_MSK 0xfffeffff
|
#define RG_EN_RX_LNA_SFT 16
|
#define RG_EN_RX_LNA_HI 16
|
#define RG_EN_RX_LNA_SZ 1
|
#define RG_EN_RX_MIXER_MSK 0x00020000
|
#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
|
#define RG_EN_RX_MIXER_SFT 17
|
#define RG_EN_RX_MIXER_HI 17
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#define RG_EN_RX_MIXER_SZ 1
|
#define RG_EN_RX_DIV2_MSK 0x00040000
|
#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
|
#define RG_EN_RX_DIV2_SFT 18
|
#define RG_EN_RX_DIV2_HI 18
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#define RG_EN_RX_DIV2_SZ 1
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#define RG_EN_RX_LOBUF_MSK 0x00080000
|
#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
|
#define RG_EN_RX_LOBUF_SFT 19
|
#define RG_EN_RX_LOBUF_HI 19
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#define RG_EN_RX_LOBUF_SZ 1
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#define RG_EN_RX_TZ_MSK 0x00100000
|
#define RG_EN_RX_TZ_I_MSK 0xffefffff
|
#define RG_EN_RX_TZ_SFT 20
|
#define RG_EN_RX_TZ_HI 20
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#define RG_EN_RX_TZ_SZ 1
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#define RG_EN_RX_FILTER_MSK 0x00200000
|
#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
|
#define RG_EN_RX_FILTER_SFT 21
|
#define RG_EN_RX_FILTER_HI 21
|
#define RG_EN_RX_FILTER_SZ 1
|
#define RG_EN_RX_HPF_MSK 0x00400000
|
#define RG_EN_RX_HPF_I_MSK 0xffbfffff
|
#define RG_EN_RX_HPF_SFT 22
|
#define RG_EN_RX_HPF_HI 22
|
#define RG_EN_RX_HPF_SZ 1
|
#define RG_EN_RX_RSSI_MSK 0x00800000
|
#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
|
#define RG_EN_RX_RSSI_SFT 23
|
#define RG_EN_RX_RSSI_HI 23
|
#define RG_EN_RX_RSSI_SZ 1
|
#define RG_EN_ADC_MSK 0x01000000
|
#define RG_EN_ADC_I_MSK 0xfeffffff
|
#define RG_EN_ADC_SFT 24
|
#define RG_EN_ADC_HI 24
|
#define RG_EN_ADC_SZ 1
|
#define RG_EN_TX_MOD_MSK 0x02000000
|
#define RG_EN_TX_MOD_I_MSK 0xfdffffff
|
#define RG_EN_TX_MOD_SFT 25
|
#define RG_EN_TX_MOD_HI 25
|
#define RG_EN_TX_MOD_SZ 1
|
#define RG_EN_TX_DIV2_MSK 0x04000000
|
#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
|
#define RG_EN_TX_DIV2_SFT 26
|
#define RG_EN_TX_DIV2_HI 26
|
#define RG_EN_TX_DIV2_SZ 1
|
#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
|
#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
|
#define RG_EN_TX_DIV2_BUF_SFT 27
|
#define RG_EN_TX_DIV2_BUF_HI 27
|
#define RG_EN_TX_DIV2_BUF_SZ 1
|
#define RG_EN_TX_LOBF_MSK 0x10000000
|
#define RG_EN_TX_LOBF_I_MSK 0xefffffff
|
#define RG_EN_TX_LOBF_SFT 28
|
#define RG_EN_TX_LOBF_HI 28
|
#define RG_EN_TX_LOBF_SZ 1
|
#define RG_EN_RX_LOBF_MSK 0x20000000
|
#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
|
#define RG_EN_RX_LOBF_SFT 29
|
#define RG_EN_RX_LOBF_HI 29
|
#define RG_EN_RX_LOBF_SZ 1
|
#define RG_SEL_DPLL_CLK_MSK 0x40000000
|
#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
|
#define RG_SEL_DPLL_CLK_SFT 30
|
#define RG_SEL_DPLL_CLK_HI 30
|
#define RG_SEL_DPLL_CLK_SZ 1
|
#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
|
#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
|
#define RG_EN_CLK_960MBY13_UART_SFT 31
|
#define RG_EN_CLK_960MBY13_UART_HI 31
|
#define RG_EN_CLK_960MBY13_UART_SZ 1
|
#define RG_EN_TX_DPD_MSK 0x00000001
|
#define RG_EN_TX_DPD_I_MSK 0xfffffffe
|
#define RG_EN_TX_DPD_SFT 0
|
#define RG_EN_TX_DPD_HI 0
|
#define RG_EN_TX_DPD_SZ 1
|
#define RG_EN_TX_TSSI_MSK 0x00000002
|
#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
|
#define RG_EN_TX_TSSI_SFT 1
|
#define RG_EN_TX_TSSI_HI 1
|
#define RG_EN_TX_TSSI_SZ 1
|
#define RG_EN_RX_IQCAL_MSK 0x00000004
|
#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
|
#define RG_EN_RX_IQCAL_SFT 2
|
#define RG_EN_RX_IQCAL_HI 2
|
#define RG_EN_RX_IQCAL_SZ 1
|
#define RG_EN_TX_DAC_CAL_MSK 0x00000008
|
#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
|
#define RG_EN_TX_DAC_CAL_SFT 3
|
#define RG_EN_TX_DAC_CAL_HI 3
|
#define RG_EN_TX_DAC_CAL_SZ 1
|
#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
|
#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
|
#define RG_EN_TX_SELF_MIXER_SFT 4
|
#define RG_EN_TX_SELF_MIXER_HI 4
|
#define RG_EN_TX_SELF_MIXER_SZ 1
|
#define RG_EN_TX_DAC_OUT_MSK 0x00000020
|
#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
|
#define RG_EN_TX_DAC_OUT_SFT 5
|
#define RG_EN_TX_DAC_OUT_HI 5
|
#define RG_EN_TX_DAC_OUT_SZ 1
|
#define RG_EN_LDO_RX_FE_MSK 0x00000040
|
#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
|
#define RG_EN_LDO_RX_FE_SFT 6
|
#define RG_EN_LDO_RX_FE_HI 6
|
#define RG_EN_LDO_RX_FE_SZ 1
|
#define RG_EN_LDO_ABB_MSK 0x00000080
|
#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
|
#define RG_EN_LDO_ABB_SFT 7
|
#define RG_EN_LDO_ABB_HI 7
|
#define RG_EN_LDO_ABB_SZ 1
|
#define RG_EN_LDO_AFE_MSK 0x00000100
|
#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
|
#define RG_EN_LDO_AFE_SFT 8
|
#define RG_EN_LDO_AFE_HI 8
|
#define RG_EN_LDO_AFE_SZ 1
|
#define RG_EN_SX_CHPLDO_MSK 0x00000200
|
#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
|
#define RG_EN_SX_CHPLDO_SFT 9
|
#define RG_EN_SX_CHPLDO_HI 9
|
#define RG_EN_SX_CHPLDO_SZ 1
|
#define RG_EN_SX_LOBFLDO_MSK 0x00000400
|
#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
|
#define RG_EN_SX_LOBFLDO_SFT 10
|
#define RG_EN_SX_LOBFLDO_HI 10
|
#define RG_EN_SX_LOBFLDO_SZ 1
|
#define RG_EN_IREF_RX_MSK 0x00000800
|
#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
|
#define RG_EN_IREF_RX_SFT 11
|
#define RG_EN_IREF_RX_HI 11
|
#define RG_EN_IREF_RX_SZ 1
|
#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
|
#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
|
#define RG_EN_TX_DAC_VOUT_SFT 13
|
#define RG_EN_TX_DAC_VOUT_HI 13
|
#define RG_EN_TX_DAC_VOUT_SZ 1
|
#define RG_EN_SX_LCK_BIN_MSK 0x00004000
|
#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
|
#define RG_EN_SX_LCK_BIN_SFT 14
|
#define RG_EN_SX_LCK_BIN_HI 14
|
#define RG_EN_SX_LCK_BIN_SZ 1
|
#define RG_RTC_CAL_MODE_MSK 0x00010000
|
#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
|
#define RG_RTC_CAL_MODE_SFT 16
|
#define RG_RTC_CAL_MODE_HI 16
|
#define RG_RTC_CAL_MODE_SZ 1
|
#define RG_EN_IQPAD_IOSW_MSK 0x00020000
|
#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
|
#define RG_EN_IQPAD_IOSW_SFT 17
|
#define RG_EN_IQPAD_IOSW_HI 17
|
#define RG_EN_IQPAD_IOSW_SZ 1
|
#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
|
#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
|
#define RG_EN_TESTPAD_IOSW_SFT 18
|
#define RG_EN_TESTPAD_IOSW_HI 18
|
#define RG_EN_TESTPAD_IOSW_SZ 1
|
#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
|
#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
|
#define RG_EN_TRXBF_BYPASS_SFT 19
|
#define RG_EN_TRXBF_BYPASS_HI 19
|
#define RG_EN_TRXBF_BYPASS_SZ 1
|
#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
|
#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
|
#define RG_LDO_LEVEL_RX_FE_SFT 0
|
#define RG_LDO_LEVEL_RX_FE_HI 2
|
#define RG_LDO_LEVEL_RX_FE_SZ 3
|
#define RG_LDO_LEVEL_ABB_MSK 0x00000038
|
#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
|
#define RG_LDO_LEVEL_ABB_SFT 3
|
#define RG_LDO_LEVEL_ABB_HI 5
|
#define RG_LDO_LEVEL_ABB_SZ 3
|
#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
|
#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
|
#define RG_LDO_LEVEL_AFE_SFT 6
|
#define RG_LDO_LEVEL_AFE_HI 8
|
#define RG_LDO_LEVEL_AFE_SZ 3
|
#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
|
#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
|
#define RG_SX_LDO_CHP_LEVEL_SFT 9
|
#define RG_SX_LDO_CHP_LEVEL_HI 11
|
#define RG_SX_LDO_CHP_LEVEL_SZ 3
|
#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
|
#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
|
#define RG_SX_LDO_LOBF_LEVEL_SFT 12
|
#define RG_SX_LDO_LOBF_LEVEL_HI 14
|
#define RG_SX_LDO_LOBF_LEVEL_SZ 3
|
#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
|
#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
|
#define RG_SX_LDO_XOSC_LEVEL_SFT 15
|
#define RG_SX_LDO_XOSC_LEVEL_HI 17
|
#define RG_SX_LDO_XOSC_LEVEL_SZ 3
|
#define RG_DP_LDO_LEVEL_MSK 0x001c0000
|
#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
|
#define RG_DP_LDO_LEVEL_SFT 18
|
#define RG_DP_LDO_LEVEL_HI 20
|
#define RG_DP_LDO_LEVEL_SZ 3
|
#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
|
#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
|
#define RG_SX_LDO_VCO_LEVEL_SFT 21
|
#define RG_SX_LDO_VCO_LEVEL_HI 23
|
#define RG_SX_LDO_VCO_LEVEL_SZ 3
|
#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
|
#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
|
#define RG_TX_LDO_TX_LEVEL_SFT 24
|
#define RG_TX_LDO_TX_LEVEL_HI 26
|
#define RG_TX_LDO_TX_LEVEL_SZ 3
|
#define RG_EN_RX_PADSW_MSK 0x00000001
|
#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
|
#define RG_EN_RX_PADSW_SFT 0
|
#define RG_EN_RX_PADSW_HI 0
|
#define RG_EN_RX_PADSW_SZ 1
|
#define RG_EN_RX_TESTNODE_MSK 0x00000002
|
#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
|
#define RG_EN_RX_TESTNODE_SFT 1
|
#define RG_EN_RX_TESTNODE_HI 1
|
#define RG_EN_RX_TESTNODE_SZ 1
|
#define RG_RX_ABBCFIX_MSK 0x00000004
|
#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
|
#define RG_RX_ABBCFIX_SFT 2
|
#define RG_RX_ABBCFIX_HI 2
|
#define RG_RX_ABBCFIX_SZ 1
|
#define RG_RX_ABBCTUNE_MSK 0x000001f8
|
#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
|
#define RG_RX_ABBCTUNE_SFT 3
|
#define RG_RX_ABBCTUNE_HI 8
|
#define RG_RX_ABBCTUNE_SZ 6
|
#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
|
#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
|
#define RG_RX_ABBOUT_TRI_STATE_SFT 9
|
#define RG_RX_ABBOUT_TRI_STATE_HI 9
|
#define RG_RX_ABBOUT_TRI_STATE_SZ 1
|
#define RG_RX_ABB_N_MODE_MSK 0x00000400
|
#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
|
#define RG_RX_ABB_N_MODE_SFT 10
|
#define RG_RX_ABB_N_MODE_HI 10
|
#define RG_RX_ABB_N_MODE_SZ 1
|
#define RG_RX_EN_LOOPA_MSK 0x00000800
|
#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
|
#define RG_RX_EN_LOOPA_SFT 11
|
#define RG_RX_EN_LOOPA_HI 11
|
#define RG_RX_EN_LOOPA_SZ 1
|
#define RG_RX_FILTERI1ST_MSK 0x00003000
|
#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
|
#define RG_RX_FILTERI1ST_SFT 12
|
#define RG_RX_FILTERI1ST_HI 13
|
#define RG_RX_FILTERI1ST_SZ 2
|
#define RG_RX_FILTERI2ND_MSK 0x0000c000
|
#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
|
#define RG_RX_FILTERI2ND_SFT 14
|
#define RG_RX_FILTERI2ND_HI 15
|
#define RG_RX_FILTERI2ND_SZ 2
|
#define RG_RX_FILTERI3RD_MSK 0x00030000
|
#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
|
#define RG_RX_FILTERI3RD_SFT 16
|
#define RG_RX_FILTERI3RD_HI 17
|
#define RG_RX_FILTERI3RD_SZ 2
|
#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
|
#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
|
#define RG_RX_FILTERI_COURSE_SFT 18
|
#define RG_RX_FILTERI_COURSE_HI 19
|
#define RG_RX_FILTERI_COURSE_SZ 2
|
#define RG_RX_FILTERVCM_MSK 0x00300000
|
#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
|
#define RG_RX_FILTERVCM_SFT 20
|
#define RG_RX_FILTERVCM_HI 21
|
#define RG_RX_FILTERVCM_SZ 2
|
#define RG_RX_HPF3M_MSK 0x00400000
|
#define RG_RX_HPF3M_I_MSK 0xffbfffff
|
#define RG_RX_HPF3M_SFT 22
|
#define RG_RX_HPF3M_HI 22
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#define RG_RX_HPF3M_SZ 1
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#define RG_RX_HPF300K_MSK 0x00800000
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#define RG_RX_HPF300K_I_MSK 0xff7fffff
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#define RG_RX_HPF300K_SFT 23
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#define RG_RX_HPF300K_HI 23
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#define RG_RX_HPF300K_SZ 1
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#define RG_RX_HPFI_MSK 0x03000000
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#define RG_RX_HPFI_I_MSK 0xfcffffff
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#define RG_RX_HPFI_SFT 24
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#define RG_RX_HPFI_HI 25
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#define RG_RX_HPFI_SZ 2
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#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
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#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
|
#define RG_RX_HPF_FINALCORNER_SFT 26
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#define RG_RX_HPF_FINALCORNER_HI 27
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#define RG_RX_HPF_FINALCORNER_SZ 2
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#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
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#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
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#define RG_RX_HPF_SETTLE1_C_SFT 28
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#define RG_RX_HPF_SETTLE1_C_HI 29
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#define RG_RX_HPF_SETTLE1_C_SZ 2
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#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
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#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
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#define RG_RX_HPF_SETTLE1_R_SFT 0
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#define RG_RX_HPF_SETTLE1_R_HI 1
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#define RG_RX_HPF_SETTLE1_R_SZ 2
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#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
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#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
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#define RG_RX_HPF_SETTLE2_C_SFT 2
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#define RG_RX_HPF_SETTLE2_C_HI 3
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#define RG_RX_HPF_SETTLE2_C_SZ 2
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#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
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#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
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#define RG_RX_HPF_SETTLE2_R_SFT 4
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#define RG_RX_HPF_SETTLE2_R_HI 5
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#define RG_RX_HPF_SETTLE2_R_SZ 2
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#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
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#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
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#define RG_RX_HPF_VCMCON2_SFT 6
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#define RG_RX_HPF_VCMCON2_HI 7
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#define RG_RX_HPF_VCMCON2_SZ 2
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#define RG_RX_HPF_VCMCON_MSK 0x00000300
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#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
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#define RG_RX_HPF_VCMCON_SFT 8
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#define RG_RX_HPF_VCMCON_HI 9
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#define RG_RX_HPF_VCMCON_SZ 2
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#define RG_RX_OUTVCM_MSK 0x00000c00
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#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
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#define RG_RX_OUTVCM_SFT 10
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#define RG_RX_OUTVCM_HI 11
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#define RG_RX_OUTVCM_SZ 2
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#define RG_RX_TZI_MSK 0x00003000
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#define RG_RX_TZI_I_MSK 0xffffcfff
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#define RG_RX_TZI_SFT 12
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#define RG_RX_TZI_HI 13
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#define RG_RX_TZI_SZ 2
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#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
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#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
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#define RG_RX_TZ_OUT_TRISTATE_SFT 14
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#define RG_RX_TZ_OUT_TRISTATE_HI 14
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#define RG_RX_TZ_OUT_TRISTATE_SZ 1
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#define RG_RX_TZ_VCM_MSK 0x00018000
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#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
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#define RG_RX_TZ_VCM_SFT 15
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#define RG_RX_TZ_VCM_HI 16
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#define RG_RX_TZ_VCM_SZ 2
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#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
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#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
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#define RG_EN_RX_RSSI_TESTNODE_SFT 17
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#define RG_EN_RX_RSSI_TESTNODE_HI 19
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#define RG_EN_RX_RSSI_TESTNODE_SZ 3
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#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
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#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
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#define RG_RX_ADCRSSI_CLKSEL_SFT 20
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#define RG_RX_ADCRSSI_CLKSEL_HI 20
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#define RG_RX_ADCRSSI_CLKSEL_SZ 1
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#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
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#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
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#define RG_RX_ADCRSSI_VCM_SFT 21
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#define RG_RX_ADCRSSI_VCM_HI 22
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#define RG_RX_ADCRSSI_VCM_SZ 2
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#define RG_RX_REC_LPFCORNER_MSK 0x01800000
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#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
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#define RG_RX_REC_LPFCORNER_SFT 23
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#define RG_RX_REC_LPFCORNER_HI 24
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#define RG_RX_REC_LPFCORNER_SZ 2
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#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
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#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
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#define RG_RSSI_CLOCK_GATING_SFT 25
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#define RG_RSSI_CLOCK_GATING_HI 25
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#define RG_RSSI_CLOCK_GATING_SZ 1
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#define RG_TXPGA_CAPSW_MSK 0x00000003
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#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
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#define RG_TXPGA_CAPSW_SFT 0
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#define RG_TXPGA_CAPSW_HI 1
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#define RG_TXPGA_CAPSW_SZ 2
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#define RG_TXPGA_MAIN_MSK 0x000000fc
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#define RG_TXPGA_MAIN_I_MSK 0xffffff03
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#define RG_TXPGA_MAIN_SFT 2
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#define RG_TXPGA_MAIN_HI 7
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#define RG_TXPGA_MAIN_SZ 6
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#define RG_TXPGA_STEER_MSK 0x00003f00
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#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
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#define RG_TXPGA_STEER_SFT 8
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#define RG_TXPGA_STEER_HI 13
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#define RG_TXPGA_STEER_SZ 6
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#define RG_TXMOD_GMCELL_MSK 0x0000c000
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#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
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#define RG_TXMOD_GMCELL_SFT 14
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#define RG_TXMOD_GMCELL_HI 15
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#define RG_TXMOD_GMCELL_SZ 2
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#define RG_TXLPF_GMCELL_MSK 0x00030000
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#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
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#define RG_TXLPF_GMCELL_SFT 16
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#define RG_TXLPF_GMCELL_HI 17
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#define RG_TXLPF_GMCELL_SZ 2
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#define RG_PACELL_EN_MSK 0x001c0000
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#define RG_PACELL_EN_I_MSK 0xffe3ffff
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#define RG_PACELL_EN_SFT 18
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#define RG_PACELL_EN_HI 20
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#define RG_PACELL_EN_SZ 3
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#define RG_PABIAS_CTRL_MSK 0x01e00000
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#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
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#define RG_PABIAS_CTRL_SFT 21
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#define RG_PABIAS_CTRL_HI 24
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#define RG_PABIAS_CTRL_SZ 4
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#define RG_TX_DIV_VSET_MSK 0x0c000000
|
#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
|
#define RG_TX_DIV_VSET_SFT 26
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#define RG_TX_DIV_VSET_HI 27
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#define RG_TX_DIV_VSET_SZ 2
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#define RG_TX_LOBUF_VSET_MSK 0x30000000
|
#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
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#define RG_TX_LOBUF_VSET_SFT 28
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#define RG_TX_LOBUF_VSET_HI 29
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#define RG_TX_LOBUF_VSET_SZ 2
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#define RG_RX_SQDC_MSK 0x00000007
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#define RG_RX_SQDC_I_MSK 0xfffffff8
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#define RG_RX_SQDC_SFT 0
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#define RG_RX_SQDC_HI 2
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#define RG_RX_SQDC_SZ 3
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#define RG_RX_DIV2_CORE_MSK 0x00000018
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#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
|
#define RG_RX_DIV2_CORE_SFT 3
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#define RG_RX_DIV2_CORE_HI 4
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#define RG_RX_DIV2_CORE_SZ 2
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#define RG_RX_LOBUF_MSK 0x00000060
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#define RG_RX_LOBUF_I_MSK 0xffffff9f
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#define RG_RX_LOBUF_SFT 5
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#define RG_RX_LOBUF_HI 6
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#define RG_RX_LOBUF_SZ 2
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#define RG_TX_DPDGM_BIAS_MSK 0x00000780
|
#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
|
#define RG_TX_DPDGM_BIAS_SFT 7
|
#define RG_TX_DPDGM_BIAS_HI 10
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#define RG_TX_DPDGM_BIAS_SZ 4
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#define RG_TX_DPD_DIV_MSK 0x00007800
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#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
|
#define RG_TX_DPD_DIV_SFT 11
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#define RG_TX_DPD_DIV_HI 14
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#define RG_TX_DPD_DIV_SZ 4
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#define RG_TX_TSSI_BIAS_MSK 0x00038000
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#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
|
#define RG_TX_TSSI_BIAS_SFT 15
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#define RG_TX_TSSI_BIAS_HI 17
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#define RG_TX_TSSI_BIAS_SZ 3
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#define RG_TX_TSSI_DIV_MSK 0x001c0000
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#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
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#define RG_TX_TSSI_DIV_SFT 18
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#define RG_TX_TSSI_DIV_HI 20
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#define RG_TX_TSSI_DIV_SZ 3
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#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
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#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
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#define RG_TX_TSSI_TESTMODE_SFT 21
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#define RG_TX_TSSI_TESTMODE_HI 21
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#define RG_TX_TSSI_TESTMODE_SZ 1
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#define RG_TX_TSSI_TEST_MSK 0x00c00000
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#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
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#define RG_TX_TSSI_TEST_SFT 22
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#define RG_TX_TSSI_TEST_HI 23
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#define RG_TX_TSSI_TEST_SZ 2
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#define RG_PACASCODE_CTRL_MSK 0x07000000
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#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
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#define RG_PACASCODE_CTRL_SFT 24
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#define RG_PACASCODE_CTRL_HI 26
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#define RG_PACASCODE_CTRL_SZ 3
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#define RG_RX_HG_LNA_GC_MSK 0x00000003
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#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
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#define RG_RX_HG_LNA_GC_SFT 0
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#define RG_RX_HG_LNA_GC_HI 1
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#define RG_RX_HG_LNA_GC_SZ 2
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#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
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#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
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#define RG_RX_HG_LNAHGN_BIAS_SFT 2
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#define RG_RX_HG_LNAHGN_BIAS_HI 5
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#define RG_RX_HG_LNAHGN_BIAS_SZ 4
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#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
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#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
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#define RG_RX_HG_LNAHGP_BIAS_SFT 6
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#define RG_RX_HG_LNAHGP_BIAS_HI 9
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#define RG_RX_HG_LNAHGP_BIAS_SZ 4
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#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
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#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
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#define RG_RX_HG_LNALG_BIAS_SFT 10
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#define RG_RX_HG_LNALG_BIAS_HI 13
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#define RG_RX_HG_LNALG_BIAS_SZ 4
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#define RG_RX_HG_TZ_GC_MSK 0x0000c000
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#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
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#define RG_RX_HG_TZ_GC_SFT 14
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#define RG_RX_HG_TZ_GC_HI 15
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#define RG_RX_HG_TZ_GC_SZ 2
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#define RG_RX_HG_TZ_CAP_MSK 0x00070000
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#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
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#define RG_RX_HG_TZ_CAP_SFT 16
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#define RG_RX_HG_TZ_CAP_HI 18
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#define RG_RX_HG_TZ_CAP_SZ 3
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#define RG_RX_MG_LNA_GC_MSK 0x00000003
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#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
|
#define RG_RX_MG_LNA_GC_SFT 0
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#define RG_RX_MG_LNA_GC_HI 1
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#define RG_RX_MG_LNA_GC_SZ 2
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#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
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#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
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#define RG_RX_MG_LNAHGN_BIAS_SFT 2
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#define RG_RX_MG_LNAHGN_BIAS_HI 5
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#define RG_RX_MG_LNAHGN_BIAS_SZ 4
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#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
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#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
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#define RG_RX_MG_LNAHGP_BIAS_SFT 6
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#define RG_RX_MG_LNAHGP_BIAS_HI 9
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#define RG_RX_MG_LNAHGP_BIAS_SZ 4
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#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
|
#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
|
#define RG_RX_MG_LNALG_BIAS_SFT 10
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#define RG_RX_MG_LNALG_BIAS_HI 13
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#define RG_RX_MG_LNALG_BIAS_SZ 4
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#define RG_RX_MG_TZ_GC_MSK 0x0000c000
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#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
|
#define RG_RX_MG_TZ_GC_SFT 14
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#define RG_RX_MG_TZ_GC_HI 15
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#define RG_RX_MG_TZ_GC_SZ 2
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#define RG_RX_MG_TZ_CAP_MSK 0x00070000
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#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
|
#define RG_RX_MG_TZ_CAP_SFT 16
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#define RG_RX_MG_TZ_CAP_HI 18
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#define RG_RX_MG_TZ_CAP_SZ 3
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#define RG_RX_LG_LNA_GC_MSK 0x00000003
|
#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
|
#define RG_RX_LG_LNA_GC_SFT 0
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#define RG_RX_LG_LNA_GC_HI 1
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#define RG_RX_LG_LNA_GC_SZ 2
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#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
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#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
|
#define RG_RX_LG_LNAHGN_BIAS_SFT 2
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#define RG_RX_LG_LNAHGN_BIAS_HI 5
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#define RG_RX_LG_LNAHGN_BIAS_SZ 4
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#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
|
#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
|
#define RG_RX_LG_LNAHGP_BIAS_SFT 6
|
#define RG_RX_LG_LNAHGP_BIAS_HI 9
|
#define RG_RX_LG_LNAHGP_BIAS_SZ 4
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#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
|
#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
|
#define RG_RX_LG_LNALG_BIAS_SFT 10
|
#define RG_RX_LG_LNALG_BIAS_HI 13
|
#define RG_RX_LG_LNALG_BIAS_SZ 4
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#define RG_RX_LG_TZ_GC_MSK 0x0000c000
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#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
|
#define RG_RX_LG_TZ_GC_SFT 14
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#define RG_RX_LG_TZ_GC_HI 15
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#define RG_RX_LG_TZ_GC_SZ 2
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#define RG_RX_LG_TZ_CAP_MSK 0x00070000
|
#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
|
#define RG_RX_LG_TZ_CAP_SFT 16
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#define RG_RX_LG_TZ_CAP_HI 18
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#define RG_RX_LG_TZ_CAP_SZ 3
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#define RG_RX_ULG_LNA_GC_MSK 0x00000003
|
#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
|
#define RG_RX_ULG_LNA_GC_SFT 0
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#define RG_RX_ULG_LNA_GC_HI 1
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#define RG_RX_ULG_LNA_GC_SZ 2
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#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
|
#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
|
#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
|
#define RG_RX_ULG_LNAHGN_BIAS_HI 5
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#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
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#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
|
#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
|
#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
|
#define RG_RX_ULG_LNAHGP_BIAS_HI 9
|
#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
|
#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
|
#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
|
#define RG_RX_ULG_LNALG_BIAS_SFT 10
|
#define RG_RX_ULG_LNALG_BIAS_HI 13
|
#define RG_RX_ULG_LNALG_BIAS_SZ 4
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#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
|
#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
|
#define RG_RX_ULG_TZ_GC_SFT 14
|
#define RG_RX_ULG_TZ_GC_HI 15
|
#define RG_RX_ULG_TZ_GC_SZ 2
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#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
|
#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
|
#define RG_RX_ULG_TZ_CAP_SFT 16
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#define RG_RX_ULG_TZ_CAP_HI 18
|
#define RG_RX_ULG_TZ_CAP_SZ 3
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#define RG_HPF1_FAST_SET_X_MSK 0x00000001
|
#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
|
#define RG_HPF1_FAST_SET_X_SFT 0
|
#define RG_HPF1_FAST_SET_X_HI 0
|
#define RG_HPF1_FAST_SET_X_SZ 1
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#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
|
#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
|
#define RG_HPF1_FAST_SET_Y_SFT 1
|
#define RG_HPF1_FAST_SET_Y_HI 1
|
#define RG_HPF1_FAST_SET_Y_SZ 1
|
#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
|
#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
|
#define RG_HPF1_FAST_SET_Z_SFT 2
|
#define RG_HPF1_FAST_SET_Z_HI 2
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#define RG_HPF1_FAST_SET_Z_SZ 1
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#define RG_HPF_T1A_MSK 0x00000018
|
#define RG_HPF_T1A_I_MSK 0xffffffe7
|
#define RG_HPF_T1A_SFT 3
|
#define RG_HPF_T1A_HI 4
|
#define RG_HPF_T1A_SZ 2
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#define RG_HPF_T1B_MSK 0x00000060
|
#define RG_HPF_T1B_I_MSK 0xffffff9f
|
#define RG_HPF_T1B_SFT 5
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#define RG_HPF_T1B_HI 6
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#define RG_HPF_T1B_SZ 2
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#define RG_HPF_T1C_MSK 0x00000180
|
#define RG_HPF_T1C_I_MSK 0xfffffe7f
|
#define RG_HPF_T1C_SFT 7
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#define RG_HPF_T1C_HI 8
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#define RG_HPF_T1C_SZ 2
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#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
|
#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
|
#define RG_RX_LNA_TRI_SEL_SFT 9
|
#define RG_RX_LNA_TRI_SEL_HI 10
|
#define RG_RX_LNA_TRI_SEL_SZ 2
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#define RG_RX_LNA_SETTLE_MSK 0x00001800
|
#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
|
#define RG_RX_LNA_SETTLE_SFT 11
|
#define RG_RX_LNA_SETTLE_HI 12
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#define RG_RX_LNA_SETTLE_SZ 2
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#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
|
#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
|
#define RG_TXGAIN_PHYCTRL_SFT 13
|
#define RG_TXGAIN_PHYCTRL_HI 13
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#define RG_TXGAIN_PHYCTRL_SZ 1
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#define RG_TX_GAIN_MSK 0x003fc000
|
#define RG_TX_GAIN_I_MSK 0xffc03fff
|
#define RG_TX_GAIN_SFT 14
|
#define RG_TX_GAIN_HI 21
|
#define RG_TX_GAIN_SZ 8
|
#define RG_TXGAIN_MANUAL_MSK 0x00400000
|
#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
|
#define RG_TXGAIN_MANUAL_SFT 22
|
#define RG_TXGAIN_MANUAL_HI 22
|
#define RG_TXGAIN_MANUAL_SZ 1
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#define RG_TX_GAIN_OFFSET_MSK 0x07800000
|
#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
|
#define RG_TX_GAIN_OFFSET_SFT 23
|
#define RG_TX_GAIN_OFFSET_HI 26
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#define RG_TX_GAIN_OFFSET_SZ 4
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#define RG_ADC_CLKSEL_MSK 0x00000001
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#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
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#define RG_ADC_CLKSEL_SFT 0
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#define RG_ADC_CLKSEL_HI 0
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#define RG_ADC_CLKSEL_SZ 1
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#define RG_ADC_DIBIAS_MSK 0x00000006
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#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
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#define RG_ADC_DIBIAS_SFT 1
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#define RG_ADC_DIBIAS_HI 2
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#define RG_ADC_DIBIAS_SZ 2
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#define RG_ADC_DIVR_MSK 0x00000008
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#define RG_ADC_DIVR_I_MSK 0xfffffff7
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#define RG_ADC_DIVR_SFT 3
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#define RG_ADC_DIVR_HI 3
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#define RG_ADC_DIVR_SZ 1
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#define RG_ADC_DVCMI_MSK 0x00000030
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#define RG_ADC_DVCMI_I_MSK 0xffffffcf
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#define RG_ADC_DVCMI_SFT 4
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#define RG_ADC_DVCMI_HI 5
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#define RG_ADC_DVCMI_SZ 2
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#define RG_ADC_SAMSEL_MSK 0x000003c0
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#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
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#define RG_ADC_SAMSEL_SFT 6
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#define RG_ADC_SAMSEL_HI 9
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#define RG_ADC_SAMSEL_SZ 4
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#define RG_ADC_STNBY_MSK 0x00000400
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#define RG_ADC_STNBY_I_MSK 0xfffffbff
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#define RG_ADC_STNBY_SFT 10
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#define RG_ADC_STNBY_HI 10
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#define RG_ADC_STNBY_SZ 1
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#define RG_ADC_TESTMODE_MSK 0x00000800
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#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
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#define RG_ADC_TESTMODE_SFT 11
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#define RG_ADC_TESTMODE_HI 11
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#define RG_ADC_TESTMODE_SZ 1
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#define RG_ADC_TSEL_MSK 0x0000f000
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#define RG_ADC_TSEL_I_MSK 0xffff0fff
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#define RG_ADC_TSEL_SFT 12
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#define RG_ADC_TSEL_HI 15
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#define RG_ADC_TSEL_SZ 4
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#define RG_ADC_VRSEL_MSK 0x00030000
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#define RG_ADC_VRSEL_I_MSK 0xfffcffff
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#define RG_ADC_VRSEL_SFT 16
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#define RG_ADC_VRSEL_HI 17
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#define RG_ADC_VRSEL_SZ 2
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#define RG_DICMP_MSK 0x000c0000
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#define RG_DICMP_I_MSK 0xfff3ffff
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#define RG_DICMP_SFT 18
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#define RG_DICMP_HI 19
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#define RG_DICMP_SZ 2
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#define RG_DIOP_MSK 0x00300000
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#define RG_DIOP_I_MSK 0xffcfffff
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#define RG_DIOP_SFT 20
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#define RG_DIOP_HI 21
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#define RG_DIOP_SZ 2
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#define RG_SARADC_VRSEL_MSK 0x00c00000
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#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
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#define RG_SARADC_VRSEL_SFT 22
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#define RG_SARADC_VRSEL_HI 23
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#define RG_SARADC_VRSEL_SZ 2
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#define RG_EN_SAR_TEST_MSK 0x03000000
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#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
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#define RG_EN_SAR_TEST_SFT 24
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#define RG_EN_SAR_TEST_HI 25
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#define RG_EN_SAR_TEST_SZ 2
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#define RG_SARADC_THERMAL_MSK 0x04000000
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#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
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#define RG_SARADC_THERMAL_SFT 26
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#define RG_SARADC_THERMAL_HI 26
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#define RG_SARADC_THERMAL_SZ 1
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#define RG_SARADC_TSSI_MSK 0x08000000
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#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
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#define RG_SARADC_TSSI_SFT 27
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#define RG_SARADC_TSSI_HI 27
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#define RG_SARADC_TSSI_SZ 1
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#define RG_CLK_SAR_SEL_MSK 0x30000000
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#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
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#define RG_CLK_SAR_SEL_SFT 28
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#define RG_CLK_SAR_SEL_HI 29
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#define RG_CLK_SAR_SEL_SZ 2
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#define RG_EN_SARADC_MSK 0x40000000
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#define RG_EN_SARADC_I_MSK 0xbfffffff
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#define RG_EN_SARADC_SFT 30
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#define RG_EN_SARADC_HI 30
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#define RG_EN_SARADC_SZ 1
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#define RG_DACI1ST_MSK 0x00000003
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#define RG_DACI1ST_I_MSK 0xfffffffc
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#define RG_DACI1ST_SFT 0
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#define RG_DACI1ST_HI 1
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#define RG_DACI1ST_SZ 2
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#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
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#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
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#define RG_TX_DACLPF_ICOURSE_SFT 2
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#define RG_TX_DACLPF_ICOURSE_HI 3
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#define RG_TX_DACLPF_ICOURSE_SZ 2
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#define RG_TX_DACLPF_IFINE_MSK 0x00000030
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#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
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#define RG_TX_DACLPF_IFINE_SFT 4
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#define RG_TX_DACLPF_IFINE_HI 5
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#define RG_TX_DACLPF_IFINE_SZ 2
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#define RG_TX_DACLPF_VCM_MSK 0x000000c0
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#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
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#define RG_TX_DACLPF_VCM_SFT 6
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#define RG_TX_DACLPF_VCM_HI 7
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#define RG_TX_DACLPF_VCM_SZ 2
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#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
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#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
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#define RG_TX_DAC_CKEDGE_SEL_SFT 8
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#define RG_TX_DAC_CKEDGE_SEL_HI 8
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#define RG_TX_DAC_CKEDGE_SEL_SZ 1
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#define RG_TX_DAC_IBIAS_MSK 0x00000600
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#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
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#define RG_TX_DAC_IBIAS_SFT 9
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#define RG_TX_DAC_IBIAS_HI 10
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#define RG_TX_DAC_IBIAS_SZ 2
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#define RG_TX_DAC_OS_MSK 0x00003800
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#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
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#define RG_TX_DAC_OS_SFT 11
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#define RG_TX_DAC_OS_HI 13
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#define RG_TX_DAC_OS_SZ 3
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#define RG_TX_DAC_RCAL_MSK 0x0000c000
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#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
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#define RG_TX_DAC_RCAL_SFT 14
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#define RG_TX_DAC_RCAL_HI 15
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#define RG_TX_DAC_RCAL_SZ 2
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#define RG_TX_DAC_TSEL_MSK 0x000f0000
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#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
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#define RG_TX_DAC_TSEL_SFT 16
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#define RG_TX_DAC_TSEL_HI 19
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#define RG_TX_DAC_TSEL_SZ 4
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#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
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#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
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#define RG_TX_EN_VOLTAGE_IN_SFT 20
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#define RG_TX_EN_VOLTAGE_IN_HI 20
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#define RG_TX_EN_VOLTAGE_IN_SZ 1
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#define RG_TXLPF_BYPASS_MSK 0x00200000
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#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
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#define RG_TXLPF_BYPASS_SFT 21
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#define RG_TXLPF_BYPASS_HI 21
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#define RG_TXLPF_BYPASS_SZ 1
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#define RG_TXLPF_BOOSTI_MSK 0x00400000
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#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
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#define RG_TXLPF_BOOSTI_SFT 22
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#define RG_TXLPF_BOOSTI_HI 22
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#define RG_TXLPF_BOOSTI_SZ 1
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#define RG_TX_DAC_IOFFSET_MSK 0x07800000
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#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
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#define RG_TX_DAC_IOFFSET_SFT 23
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#define RG_TX_DAC_IOFFSET_HI 26
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#define RG_TX_DAC_IOFFSET_SZ 4
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#define RG_TX_DAC_QOFFSET_MSK 0x78000000
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#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
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#define RG_TX_DAC_QOFFSET_SFT 27
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#define RG_TX_DAC_QOFFSET_HI 30
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#define RG_TX_DAC_QOFFSET_SZ 4
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#define RG_EN_SX_R3_MSK 0x00000001
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#define RG_EN_SX_R3_I_MSK 0xfffffffe
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#define RG_EN_SX_R3_SFT 0
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#define RG_EN_SX_R3_HI 0
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#define RG_EN_SX_R3_SZ 1
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#define RG_EN_SX_CH_MSK 0x00000002
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#define RG_EN_SX_CH_I_MSK 0xfffffffd
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#define RG_EN_SX_CH_SFT 1
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#define RG_EN_SX_CH_HI 1
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#define RG_EN_SX_CH_SZ 1
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#define RG_EN_SX_CHP_MSK 0x00000004
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#define RG_EN_SX_CHP_I_MSK 0xfffffffb
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#define RG_EN_SX_CHP_SFT 2
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#define RG_EN_SX_CHP_HI 2
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#define RG_EN_SX_CHP_SZ 1
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#define RG_EN_SX_DIVCK_MSK 0x00000008
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#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
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#define RG_EN_SX_DIVCK_SFT 3
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#define RG_EN_SX_DIVCK_HI 3
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#define RG_EN_SX_DIVCK_SZ 1
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#define RG_EN_SX_VCOBF_MSK 0x00000010
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#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
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#define RG_EN_SX_VCOBF_SFT 4
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#define RG_EN_SX_VCOBF_HI 4
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#define RG_EN_SX_VCOBF_SZ 1
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#define RG_EN_SX_VCO_MSK 0x00000020
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#define RG_EN_SX_VCO_I_MSK 0xffffffdf
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#define RG_EN_SX_VCO_SFT 5
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#define RG_EN_SX_VCO_HI 5
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#define RG_EN_SX_VCO_SZ 1
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#define RG_EN_SX_MOD_MSK 0x00000040
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#define RG_EN_SX_MOD_I_MSK 0xffffffbf
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#define RG_EN_SX_MOD_SFT 6
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#define RG_EN_SX_MOD_HI 6
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#define RG_EN_SX_MOD_SZ 1
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#define RG_EN_SX_DITHER_MSK 0x00000100
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#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
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#define RG_EN_SX_DITHER_SFT 8
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#define RG_EN_SX_DITHER_HI 8
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#define RG_EN_SX_DITHER_SZ 1
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#define RG_EN_SX_VT_MON_MSK 0x00000800
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#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
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#define RG_EN_SX_VT_MON_SFT 11
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#define RG_EN_SX_VT_MON_HI 11
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#define RG_EN_SX_VT_MON_SZ 1
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#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
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#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
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#define RG_EN_SX_VT_MON_DG_SFT 12
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#define RG_EN_SX_VT_MON_DG_HI 12
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#define RG_EN_SX_VT_MON_DG_SZ 1
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#define RG_EN_SX_DIV_MSK 0x00002000
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#define RG_EN_SX_DIV_I_MSK 0xffffdfff
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#define RG_EN_SX_DIV_SFT 13
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#define RG_EN_SX_DIV_HI 13
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#define RG_EN_SX_DIV_SZ 1
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#define RG_EN_SX_LPF_MSK 0x00004000
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#define RG_EN_SX_LPF_I_MSK 0xffffbfff
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#define RG_EN_SX_LPF_SFT 14
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#define RG_EN_SX_LPF_HI 14
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#define RG_EN_SX_LPF_SZ 1
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#define RG_EN_DPL_MOD_MSK 0x00008000
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#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
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#define RG_EN_DPL_MOD_SFT 15
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#define RG_EN_DPL_MOD_HI 15
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#define RG_EN_DPL_MOD_SZ 1
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#define RG_DPL_MOD_ORDER_MSK 0x00030000
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#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
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#define RG_DPL_MOD_ORDER_SFT 16
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#define RG_DPL_MOD_ORDER_HI 17
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#define RG_DPL_MOD_ORDER_SZ 2
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#define RG_SX_RFCTRL_F_MSK 0x00ffffff
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#define RG_SX_RFCTRL_F_I_MSK 0xff000000
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#define RG_SX_RFCTRL_F_SFT 0
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#define RG_SX_RFCTRL_F_HI 23
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#define RG_SX_RFCTRL_F_SZ 24
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#define RG_SX_SEL_CP_MSK 0x0f000000
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#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
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#define RG_SX_SEL_CP_SFT 24
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#define RG_SX_SEL_CP_HI 27
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#define RG_SX_SEL_CP_SZ 4
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#define RG_SX_SEL_CS_MSK 0xf0000000
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#define RG_SX_SEL_CS_I_MSK 0x0fffffff
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#define RG_SX_SEL_CS_SFT 28
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#define RG_SX_SEL_CS_HI 31
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#define RG_SX_SEL_CS_SZ 4
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#define RG_SX_RFCTRL_CH_MSK 0x000007ff
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#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
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#define RG_SX_RFCTRL_CH_SFT 0
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#define RG_SX_RFCTRL_CH_HI 10
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#define RG_SX_RFCTRL_CH_SZ 11
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#define RG_SX_SEL_C3_MSK 0x00007800
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#define RG_SX_SEL_C3_I_MSK 0xffff87ff
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#define RG_SX_SEL_C3_SFT 11
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#define RG_SX_SEL_C3_HI 14
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#define RG_SX_SEL_C3_SZ 4
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#define RG_SX_SEL_RS_MSK 0x000f8000
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#define RG_SX_SEL_RS_I_MSK 0xfff07fff
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#define RG_SX_SEL_RS_SFT 15
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#define RG_SX_SEL_RS_HI 19
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#define RG_SX_SEL_RS_SZ 5
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#define RG_SX_SEL_R3_MSK 0x01f00000
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#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
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#define RG_SX_SEL_R3_SFT 20
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#define RG_SX_SEL_R3_HI 24
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#define RG_SX_SEL_R3_SZ 5
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#define RG_SX_SEL_ICHP_MSK 0x0000001f
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#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
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#define RG_SX_SEL_ICHP_SFT 0
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#define RG_SX_SEL_ICHP_HI 4
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#define RG_SX_SEL_ICHP_SZ 5
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#define RG_SX_SEL_PCHP_MSK 0x000003e0
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#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
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#define RG_SX_SEL_PCHP_SFT 5
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#define RG_SX_SEL_PCHP_HI 9
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#define RG_SX_SEL_PCHP_SZ 5
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#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
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#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
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#define RG_SX_SEL_CHP_REGOP_SFT 10
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#define RG_SX_SEL_CHP_REGOP_HI 13
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#define RG_SX_SEL_CHP_REGOP_SZ 4
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#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
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#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
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#define RG_SX_SEL_CHP_UNIOP_SFT 14
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#define RG_SX_SEL_CHP_UNIOP_HI 17
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#define RG_SX_SEL_CHP_UNIOP_SZ 4
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#define RG_SX_CHP_IOST_POL_MSK 0x00040000
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#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
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#define RG_SX_CHP_IOST_POL_SFT 18
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#define RG_SX_CHP_IOST_POL_HI 18
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#define RG_SX_CHP_IOST_POL_SZ 1
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#define RG_SX_CHP_IOST_MSK 0x00380000
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#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
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#define RG_SX_CHP_IOST_SFT 19
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#define RG_SX_CHP_IOST_HI 21
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#define RG_SX_CHP_IOST_SZ 3
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#define RG_SX_PFDSEL_MSK 0x00400000
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#define RG_SX_PFDSEL_I_MSK 0xffbfffff
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#define RG_SX_PFDSEL_SFT 22
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#define RG_SX_PFDSEL_HI 22
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#define RG_SX_PFDSEL_SZ 1
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#define RG_SX_PFD_SET_MSK 0x00800000
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#define RG_SX_PFD_SET_I_MSK 0xff7fffff
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#define RG_SX_PFD_SET_SFT 23
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#define RG_SX_PFD_SET_HI 23
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#define RG_SX_PFD_SET_SZ 1
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#define RG_SX_PFD_SET1_MSK 0x01000000
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#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
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#define RG_SX_PFD_SET1_SFT 24
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#define RG_SX_PFD_SET1_HI 24
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#define RG_SX_PFD_SET1_SZ 1
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#define RG_SX_PFD_SET2_MSK 0x02000000
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#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
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#define RG_SX_PFD_SET2_SFT 25
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#define RG_SX_PFD_SET2_HI 25
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#define RG_SX_PFD_SET2_SZ 1
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#define RG_SX_VBNCAS_SEL_MSK 0x04000000
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#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
|
#define RG_SX_VBNCAS_SEL_SFT 26
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#define RG_SX_VBNCAS_SEL_HI 26
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#define RG_SX_VBNCAS_SEL_SZ 1
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#define RG_SX_PFD_RST_H_MSK 0x08000000
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#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
|
#define RG_SX_PFD_RST_H_SFT 27
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#define RG_SX_PFD_RST_H_HI 27
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#define RG_SX_PFD_RST_H_SZ 1
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#define RG_SX_PFD_TRUP_MSK 0x10000000
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#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
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#define RG_SX_PFD_TRUP_SFT 28
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#define RG_SX_PFD_TRUP_HI 28
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#define RG_SX_PFD_TRUP_SZ 1
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#define RG_SX_PFD_TRDN_MSK 0x20000000
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#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
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#define RG_SX_PFD_TRDN_SFT 29
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#define RG_SX_PFD_TRDN_HI 29
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#define RG_SX_PFD_TRDN_SZ 1
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#define RG_SX_PFD_TRSEL_MSK 0x40000000
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#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
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#define RG_SX_PFD_TRSEL_SFT 30
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#define RG_SX_PFD_TRSEL_HI 30
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#define RG_SX_PFD_TRSEL_SZ 1
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#define RG_SX_VCOBA_R_MSK 0x00000007
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#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
|
#define RG_SX_VCOBA_R_SFT 0
|
#define RG_SX_VCOBA_R_HI 2
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#define RG_SX_VCOBA_R_SZ 3
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#define RG_SX_VCORSEL_MSK 0x000000f8
|
#define RG_SX_VCORSEL_I_MSK 0xffffff07
|
#define RG_SX_VCORSEL_SFT 3
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#define RG_SX_VCORSEL_HI 7
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#define RG_SX_VCORSEL_SZ 5
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#define RG_SX_VCOCUSEL_MSK 0x00000f00
|
#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
|
#define RG_SX_VCOCUSEL_SFT 8
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#define RG_SX_VCOCUSEL_HI 11
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#define RG_SX_VCOCUSEL_SZ 4
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#define RG_SX_RXBFSEL_MSK 0x0000f000
|
#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
|
#define RG_SX_RXBFSEL_SFT 12
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#define RG_SX_RXBFSEL_HI 15
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#define RG_SX_RXBFSEL_SZ 4
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#define RG_SX_TXBFSEL_MSK 0x000f0000
|
#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
|
#define RG_SX_TXBFSEL_SFT 16
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#define RG_SX_TXBFSEL_HI 19
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#define RG_SX_TXBFSEL_SZ 4
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#define RG_SX_VCOBFSEL_MSK 0x00f00000
|
#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
|
#define RG_SX_VCOBFSEL_SFT 20
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#define RG_SX_VCOBFSEL_HI 23
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#define RG_SX_VCOBFSEL_SZ 4
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#define RG_SX_DIVBFSEL_MSK 0x0f000000
|
#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
|
#define RG_SX_DIVBFSEL_SFT 24
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#define RG_SX_DIVBFSEL_HI 27
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#define RG_SX_DIVBFSEL_SZ 4
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#define RG_SX_GNDR_SEL_MSK 0xf0000000
|
#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
|
#define RG_SX_GNDR_SEL_SFT 28
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#define RG_SX_GNDR_SEL_HI 31
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#define RG_SX_GNDR_SEL_SZ 4
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#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
|
#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
|
#define RG_SX_DITHER_WEIGHT_SFT 0
|
#define RG_SX_DITHER_WEIGHT_HI 1
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#define RG_SX_DITHER_WEIGHT_SZ 2
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#define RG_SX_MOD_ORDER_MSK 0x00000030
|
#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
|
#define RG_SX_MOD_ORDER_SFT 4
|
#define RG_SX_MOD_ORDER_HI 5
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#define RG_SX_MOD_ORDER_SZ 2
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#define RG_SX_RST_H_DIV_MSK 0x00000200
|
#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
|
#define RG_SX_RST_H_DIV_SFT 9
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#define RG_SX_RST_H_DIV_HI 9
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#define RG_SX_RST_H_DIV_SZ 1
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#define RG_SX_SDM_EDGE_MSK 0x00000400
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#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
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#define RG_SX_SDM_EDGE_SFT 10
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#define RG_SX_SDM_EDGE_HI 10
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#define RG_SX_SDM_EDGE_SZ 1
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#define RG_SX_XO_GM_MSK 0x00001800
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#define RG_SX_XO_GM_I_MSK 0xffffe7ff
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#define RG_SX_XO_GM_SFT 11
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#define RG_SX_XO_GM_HI 12
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#define RG_SX_XO_GM_SZ 2
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#define RG_SX_REFBYTWO_MSK 0x00002000
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#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
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#define RG_SX_REFBYTWO_SFT 13
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#define RG_SX_REFBYTWO_HI 13
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#define RG_SX_REFBYTWO_SZ 1
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#define RG_SX_LCKEN_MSK 0x00080000
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#define RG_SX_LCKEN_I_MSK 0xfff7ffff
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#define RG_SX_LCKEN_SFT 19
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#define RG_SX_LCKEN_HI 19
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#define RG_SX_LCKEN_SZ 1
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#define RG_SX_PREVDD_MSK 0x00f00000
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#define RG_SX_PREVDD_I_MSK 0xff0fffff
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#define RG_SX_PREVDD_SFT 20
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#define RG_SX_PREVDD_HI 23
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#define RG_SX_PREVDD_SZ 4
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#define RG_SX_PSCONTERVDD_MSK 0x0f000000
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#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
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#define RG_SX_PSCONTERVDD_SFT 24
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#define RG_SX_PSCONTERVDD_HI 27
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#define RG_SX_PSCONTERVDD_SZ 4
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#define RG_SX_PH_MSK 0x00002000
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#define RG_SX_PH_I_MSK 0xffffdfff
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#define RG_SX_PH_SFT 13
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#define RG_SX_PH_HI 13
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#define RG_SX_PH_SZ 1
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#define RG_SX_PL_MSK 0x00004000
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#define RG_SX_PL_I_MSK 0xffffbfff
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#define RG_SX_PL_SFT 14
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#define RG_SX_PL_HI 14
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#define RG_SX_PL_SZ 1
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#define RG_XOSC_CBANK_XO_MSK 0x00078000
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#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
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#define RG_XOSC_CBANK_XO_SFT 15
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#define RG_XOSC_CBANK_XO_HI 18
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#define RG_XOSC_CBANK_XO_SZ 4
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#define RG_XOSC_CBANK_XI_MSK 0x00780000
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#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
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#define RG_XOSC_CBANK_XI_SFT 19
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#define RG_XOSC_CBANK_XI_HI 22
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#define RG_XOSC_CBANK_XI_SZ 4
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#define RG_SX_VT_MON_MODE_MSK 0x00000001
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#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
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#define RG_SX_VT_MON_MODE_SFT 0
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#define RG_SX_VT_MON_MODE_HI 0
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#define RG_SX_VT_MON_MODE_SZ 1
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#define RG_SX_VT_TH_HI_MSK 0x00000006
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#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
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#define RG_SX_VT_TH_HI_SFT 1
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#define RG_SX_VT_TH_HI_HI 2
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#define RG_SX_VT_TH_HI_SZ 2
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#define RG_SX_VT_TH_LO_MSK 0x00000018
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#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
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#define RG_SX_VT_TH_LO_SFT 3
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#define RG_SX_VT_TH_LO_HI 4
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#define RG_SX_VT_TH_LO_SZ 2
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#define RG_SX_VT_SET_MSK 0x00000020
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#define RG_SX_VT_SET_I_MSK 0xffffffdf
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#define RG_SX_VT_SET_SFT 5
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#define RG_SX_VT_SET_HI 5
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#define RG_SX_VT_SET_SZ 1
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#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
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#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
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#define RG_SX_VT_MON_TMR_SFT 6
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#define RG_SX_VT_MON_TMR_HI 14
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#define RG_SX_VT_MON_TMR_SZ 9
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#define RG_EN_DP_VT_MON_MSK 0x00000001
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#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
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#define RG_EN_DP_VT_MON_SFT 0
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#define RG_EN_DP_VT_MON_HI 0
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#define RG_EN_DP_VT_MON_SZ 1
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#define RG_DP_VT_TH_HI_MSK 0x00000006
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#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
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#define RG_DP_VT_TH_HI_SFT 1
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#define RG_DP_VT_TH_HI_HI 2
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#define RG_DP_VT_TH_HI_SZ 2
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#define RG_DP_VT_TH_LO_MSK 0x00000018
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#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
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#define RG_DP_VT_TH_LO_SFT 3
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#define RG_DP_VT_TH_LO_HI 4
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#define RG_DP_VT_TH_LO_SZ 2
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#define RG_DP_CK320BY2_MSK 0x00004000
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#define RG_DP_CK320BY2_I_MSK 0xffffbfff
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#define RG_DP_CK320BY2_SFT 14
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#define RG_DP_CK320BY2_HI 14
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#define RG_DP_CK320BY2_SZ 1
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#define RG_DP_OD_TEST_MSK 0x00200000
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#define RG_DP_OD_TEST_I_MSK 0xffdfffff
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#define RG_DP_OD_TEST_SFT 21
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#define RG_DP_OD_TEST_HI 21
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#define RG_DP_OD_TEST_SZ 1
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#define RG_DP_BBPLL_BP_MSK 0x00000001
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#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
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#define RG_DP_BBPLL_BP_SFT 0
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#define RG_DP_BBPLL_BP_HI 0
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#define RG_DP_BBPLL_BP_SZ 1
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#define RG_DP_BBPLL_ICP_MSK 0x00000006
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#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
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#define RG_DP_BBPLL_ICP_SFT 1
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#define RG_DP_BBPLL_ICP_HI 2
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#define RG_DP_BBPLL_ICP_SZ 2
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#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
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#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
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#define RG_DP_BBPLL_IDUAL_SFT 3
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#define RG_DP_BBPLL_IDUAL_HI 4
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#define RG_DP_BBPLL_IDUAL_SZ 2
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#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
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#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
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#define RG_DP_BBPLL_OD_TEST_SFT 5
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#define RG_DP_BBPLL_OD_TEST_HI 8
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#define RG_DP_BBPLL_OD_TEST_SZ 4
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#define RG_DP_BBPLL_PD_MSK 0x00000200
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#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
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#define RG_DP_BBPLL_PD_SFT 9
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#define RG_DP_BBPLL_PD_HI 9
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#define RG_DP_BBPLL_PD_SZ 1
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#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
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#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
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#define RG_DP_BBPLL_TESTSEL_SFT 10
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#define RG_DP_BBPLL_TESTSEL_HI 12
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#define RG_DP_BBPLL_TESTSEL_SZ 3
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#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
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#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
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#define RG_DP_BBPLL_PFD_DLY_SFT 13
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#define RG_DP_BBPLL_PFD_DLY_HI 14
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#define RG_DP_BBPLL_PFD_DLY_SZ 2
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#define RG_DP_RP_MSK 0x00038000
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#define RG_DP_RP_I_MSK 0xfffc7fff
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#define RG_DP_RP_SFT 15
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#define RG_DP_RP_HI 17
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#define RG_DP_RP_SZ 3
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#define RG_DP_RHP_MSK 0x000c0000
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#define RG_DP_RHP_I_MSK 0xfff3ffff
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#define RG_DP_RHP_SFT 18
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#define RG_DP_RHP_HI 19
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#define RG_DP_RHP_SZ 2
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#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
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#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
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#define RG_DP_BBPLL_SDM_EDGE_SFT 31
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#define RG_DP_BBPLL_SDM_EDGE_HI 31
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#define RG_DP_BBPLL_SDM_EDGE_SZ 1
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#define RG_DP_FODIV_MSK 0x0007f000
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#define RG_DP_FODIV_I_MSK 0xfff80fff
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#define RG_DP_FODIV_SFT 12
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#define RG_DP_FODIV_HI 18
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#define RG_DP_FODIV_SZ 7
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#define RG_DP_REFDIV_MSK 0x1fc00000
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#define RG_DP_REFDIV_I_MSK 0xe03fffff
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#define RG_DP_REFDIV_SFT 22
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#define RG_DP_REFDIV_HI 28
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#define RG_DP_REFDIV_SZ 7
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#define RG_IDACAI_PGAG15_MSK 0x0000003f
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#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG15_SFT 0
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#define RG_IDACAI_PGAG15_HI 5
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#define RG_IDACAI_PGAG15_SZ 6
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#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG15_SFT 6
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#define RG_IDACAQ_PGAG15_HI 11
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#define RG_IDACAQ_PGAG15_SZ 6
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#define RG_IDACAI_PGAG14_MSK 0x0003f000
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#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG14_SFT 12
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#define RG_IDACAI_PGAG14_HI 17
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#define RG_IDACAI_PGAG14_SZ 6
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#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG14_SFT 18
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#define RG_IDACAQ_PGAG14_HI 23
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#define RG_IDACAQ_PGAG14_SZ 6
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#define RG_DP_BBPLL_BS_MSK 0x3f000000
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#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
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#define RG_DP_BBPLL_BS_SFT 24
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#define RG_DP_BBPLL_BS_HI 29
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#define RG_DP_BBPLL_BS_SZ 6
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#define RG_IDACAI_PGAG13_MSK 0x0000003f
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#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG13_SFT 0
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#define RG_IDACAI_PGAG13_HI 5
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#define RG_IDACAI_PGAG13_SZ 6
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#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG13_SFT 6
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#define RG_IDACAQ_PGAG13_HI 11
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#define RG_IDACAQ_PGAG13_SZ 6
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#define RG_IDACAI_PGAG12_MSK 0x0003f000
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#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG12_SFT 12
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#define RG_IDACAI_PGAG12_HI 17
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#define RG_IDACAI_PGAG12_SZ 6
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#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG12_SFT 18
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#define RG_IDACAQ_PGAG12_HI 23
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#define RG_IDACAQ_PGAG12_SZ 6
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#define RG_IDACAI_PGAG11_MSK 0x0000003f
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#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG11_SFT 0
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#define RG_IDACAI_PGAG11_HI 5
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#define RG_IDACAI_PGAG11_SZ 6
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#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG11_SFT 6
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#define RG_IDACAQ_PGAG11_HI 11
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#define RG_IDACAQ_PGAG11_SZ 6
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#define RG_IDACAI_PGAG10_MSK 0x0003f000
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#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG10_SFT 12
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#define RG_IDACAI_PGAG10_HI 17
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#define RG_IDACAI_PGAG10_SZ 6
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#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG10_SFT 18
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#define RG_IDACAQ_PGAG10_HI 23
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#define RG_IDACAQ_PGAG10_SZ 6
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#define RG_IDACAI_PGAG9_MSK 0x0000003f
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#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG9_SFT 0
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#define RG_IDACAI_PGAG9_HI 5
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#define RG_IDACAI_PGAG9_SZ 6
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#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG9_SFT 6
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#define RG_IDACAQ_PGAG9_HI 11
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#define RG_IDACAQ_PGAG9_SZ 6
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#define RG_IDACAI_PGAG8_MSK 0x0003f000
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#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG8_SFT 12
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#define RG_IDACAI_PGAG8_HI 17
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#define RG_IDACAI_PGAG8_SZ 6
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#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG8_SFT 18
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#define RG_IDACAQ_PGAG8_HI 23
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#define RG_IDACAQ_PGAG8_SZ 6
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#define RG_IDACAI_PGAG7_MSK 0x0000003f
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#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG7_SFT 0
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#define RG_IDACAI_PGAG7_HI 5
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#define RG_IDACAI_PGAG7_SZ 6
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#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG7_SFT 6
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#define RG_IDACAQ_PGAG7_HI 11
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#define RG_IDACAQ_PGAG7_SZ 6
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#define RG_IDACAI_PGAG6_MSK 0x0003f000
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#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG6_SFT 12
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#define RG_IDACAI_PGAG6_HI 17
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#define RG_IDACAI_PGAG6_SZ 6
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#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG6_SFT 18
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#define RG_IDACAQ_PGAG6_HI 23
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#define RG_IDACAQ_PGAG6_SZ 6
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#define RG_IDACAI_PGAG5_MSK 0x0000003f
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#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG5_SFT 0
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#define RG_IDACAI_PGAG5_HI 5
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#define RG_IDACAI_PGAG5_SZ 6
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#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG5_SFT 6
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#define RG_IDACAQ_PGAG5_HI 11
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#define RG_IDACAQ_PGAG5_SZ 6
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#define RG_IDACAI_PGAG4_MSK 0x0003f000
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#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG4_SFT 12
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#define RG_IDACAI_PGAG4_HI 17
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#define RG_IDACAI_PGAG4_SZ 6
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#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG4_SFT 18
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#define RG_IDACAQ_PGAG4_HI 23
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#define RG_IDACAQ_PGAG4_SZ 6
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#define RG_IDACAI_PGAG3_MSK 0x0000003f
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#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG3_SFT 0
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#define RG_IDACAI_PGAG3_HI 5
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#define RG_IDACAI_PGAG3_SZ 6
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#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG3_SFT 6
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#define RG_IDACAQ_PGAG3_HI 11
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#define RG_IDACAQ_PGAG3_SZ 6
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#define RG_IDACAI_PGAG2_MSK 0x0003f000
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#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG2_SFT 12
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#define RG_IDACAI_PGAG2_HI 17
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#define RG_IDACAI_PGAG2_SZ 6
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#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG2_SFT 18
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#define RG_IDACAQ_PGAG2_HI 23
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#define RG_IDACAQ_PGAG2_SZ 6
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#define RG_IDACAI_PGAG1_MSK 0x0000003f
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#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
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#define RG_IDACAI_PGAG1_SFT 0
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#define RG_IDACAI_PGAG1_HI 5
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#define RG_IDACAI_PGAG1_SZ 6
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#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
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#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
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#define RG_IDACAQ_PGAG1_SFT 6
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#define RG_IDACAQ_PGAG1_HI 11
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#define RG_IDACAQ_PGAG1_SZ 6
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#define RG_IDACAI_PGAG0_MSK 0x0003f000
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#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
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#define RG_IDACAI_PGAG0_SFT 12
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#define RG_IDACAI_PGAG0_HI 17
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#define RG_IDACAI_PGAG0_SZ 6
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#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
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#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
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#define RG_IDACAQ_PGAG0_SFT 18
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#define RG_IDACAQ_PGAG0_HI 23
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#define RG_IDACAQ_PGAG0_SZ 6
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#define RG_EN_RCAL_MSK 0x00000001
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#define RG_EN_RCAL_I_MSK 0xfffffffe
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#define RG_EN_RCAL_SFT 0
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#define RG_EN_RCAL_HI 0
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#define RG_EN_RCAL_SZ 1
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#define RG_RCAL_SPD_MSK 0x00000002
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#define RG_RCAL_SPD_I_MSK 0xfffffffd
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#define RG_RCAL_SPD_SFT 1
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#define RG_RCAL_SPD_HI 1
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#define RG_RCAL_SPD_SZ 1
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#define RG_RCAL_TMR_MSK 0x000001fc
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#define RG_RCAL_TMR_I_MSK 0xfffffe03
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#define RG_RCAL_TMR_SFT 2
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#define RG_RCAL_TMR_HI 8
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#define RG_RCAL_TMR_SZ 7
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#define RG_RCAL_CODE_CWR_MSK 0x00000200
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#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
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#define RG_RCAL_CODE_CWR_SFT 9
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#define RG_RCAL_CODE_CWR_HI 9
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#define RG_RCAL_CODE_CWR_SZ 1
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#define RG_RCAL_CODE_CWD_MSK 0x00007c00
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#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
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#define RG_RCAL_CODE_CWD_SFT 10
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#define RG_RCAL_CODE_CWD_HI 14
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#define RG_RCAL_CODE_CWD_SZ 5
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#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
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#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
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#define RG_SX_SUB_SEL_CWR_SFT 0
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#define RG_SX_SUB_SEL_CWR_HI 0
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#define RG_SX_SUB_SEL_CWR_SZ 1
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#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
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#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
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#define RG_SX_SUB_SEL_CWD_SFT 1
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#define RG_SX_SUB_SEL_CWD_HI 7
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#define RG_SX_SUB_SEL_CWD_SZ 7
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#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
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#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
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#define RG_SX_LCK_BIN_OFFSET_SFT 15
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#define RG_SX_LCK_BIN_OFFSET_HI 18
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#define RG_SX_LCK_BIN_OFFSET_SZ 4
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#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
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#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
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#define RG_SX_LCK_BIN_PRECISION_SFT 19
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#define RG_SX_LCK_BIN_PRECISION_HI 19
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#define RG_SX_LCK_BIN_PRECISION_SZ 1
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#define RG_SX_LOCK_EN_N_MSK 0x00100000
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#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
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#define RG_SX_LOCK_EN_N_SFT 20
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#define RG_SX_LOCK_EN_N_HI 20
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#define RG_SX_LOCK_EN_N_SZ 1
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#define RG_SX_LOCK_MANUAL_MSK 0x00200000
|
#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
|
#define RG_SX_LOCK_MANUAL_SFT 21
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#define RG_SX_LOCK_MANUAL_HI 21
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#define RG_SX_LOCK_MANUAL_SZ 1
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#define RG_SX_SUB_MANUAL_MSK 0x00400000
|
#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
|
#define RG_SX_SUB_MANUAL_SFT 22
|
#define RG_SX_SUB_MANUAL_HI 22
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#define RG_SX_SUB_MANUAL_SZ 1
|
#define RG_SX_SUB_SEL_MSK 0x3f800000
|
#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
|
#define RG_SX_SUB_SEL_SFT 23
|
#define RG_SX_SUB_SEL_HI 29
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#define RG_SX_SUB_SEL_SZ 7
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#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
|
#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
|
#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
|
#define RG_SX_MUX_SEL_VTH_BINL_HI 30
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#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
|
#define RG_TRX_DUMMMY_MSK 0xffffffff
|
#define RG_TRX_DUMMMY_I_MSK 0x00000000
|
#define RG_TRX_DUMMMY_SFT 0
|
#define RG_TRX_DUMMMY_HI 31
|
#define RG_TRX_DUMMMY_SZ 32
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#define RG_SX_DUMMMY_MSK 0xffffffff
|
#define RG_SX_DUMMMY_I_MSK 0x00000000
|
#define RG_SX_DUMMMY_SFT 0
|
#define RG_SX_DUMMMY_HI 31
|
#define RG_SX_DUMMMY_SZ 32
|
#define RCAL_RDY_MSK 0x00000001
|
#define RCAL_RDY_I_MSK 0xfffffffe
|
#define RCAL_RDY_SFT 0
|
#define RCAL_RDY_HI 0
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#define RCAL_RDY_SZ 1
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#define LCK_BIN_RDY_MSK 0x00000002
|
#define LCK_BIN_RDY_I_MSK 0xfffffffd
|
#define LCK_BIN_RDY_SFT 1
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#define LCK_BIN_RDY_HI 1
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#define LCK_BIN_RDY_SZ 1
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#define VT_MON_RDY_MSK 0x00000004
|
#define VT_MON_RDY_I_MSK 0xfffffffb
|
#define VT_MON_RDY_SFT 2
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#define VT_MON_RDY_HI 2
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#define VT_MON_RDY_SZ 1
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#define DA_R_CODE_LUT_MSK 0x000007c0
|
#define DA_R_CODE_LUT_I_MSK 0xfffff83f
|
#define DA_R_CODE_LUT_SFT 6
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#define DA_R_CODE_LUT_HI 10
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#define DA_R_CODE_LUT_SZ 5
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#define AD_SX_VT_MON_Q_MSK 0x00001800
|
#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
|
#define AD_SX_VT_MON_Q_SFT 11
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#define AD_SX_VT_MON_Q_HI 12
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#define AD_SX_VT_MON_Q_SZ 2
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#define AD_DP_VT_MON_Q_MSK 0x00006000
|
#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
|
#define AD_DP_VT_MON_Q_SFT 13
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#define AD_DP_VT_MON_Q_HI 14
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#define AD_DP_VT_MON_Q_SZ 2
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#define RTC_CAL_RDY_MSK 0x00008000
|
#define RTC_CAL_RDY_I_MSK 0xffff7fff
|
#define RTC_CAL_RDY_SFT 15
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#define RTC_CAL_RDY_HI 15
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#define RTC_CAL_RDY_SZ 1
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#define RG_SARADC_BIT_MSK 0x003f0000
|
#define RG_SARADC_BIT_I_MSK 0xffc0ffff
|
#define RG_SARADC_BIT_SFT 16
|
#define RG_SARADC_BIT_HI 21
|
#define RG_SARADC_BIT_SZ 6
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#define SAR_ADC_FSM_RDY_MSK 0x00400000
|
#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
|
#define SAR_ADC_FSM_RDY_SFT 22
|
#define SAR_ADC_FSM_RDY_HI 22
|
#define SAR_ADC_FSM_RDY_SZ 1
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#define AD_CIRCUIT_VERSION_MSK 0x07800000
|
#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
|
#define AD_CIRCUIT_VERSION_SFT 23
|
#define AD_CIRCUIT_VERSION_HI 26
|
#define AD_CIRCUIT_VERSION_SZ 4
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#define DA_R_CAL_CODE_MSK 0x0000001f
|
#define DA_R_CAL_CODE_I_MSK 0xffffffe0
|
#define DA_R_CAL_CODE_SFT 0
|
#define DA_R_CAL_CODE_HI 4
|
#define DA_R_CAL_CODE_SZ 5
|
#define DA_SX_SUB_SEL_MSK 0x00000fe0
|
#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
|
#define DA_SX_SUB_SEL_SFT 5
|
#define DA_SX_SUB_SEL_HI 11
|
#define DA_SX_SUB_SEL_SZ 7
|
#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
|
#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
|
#define RG_DPL_RFCTRL_CH_SFT 0
|
#define RG_DPL_RFCTRL_CH_HI 10
|
#define RG_DPL_RFCTRL_CH_SZ 11
|
#define RG_RSSIADC_RO_BIT_MSK 0x00007800
|
#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
|
#define RG_RSSIADC_RO_BIT_SFT 11
|
#define RG_RSSIADC_RO_BIT_HI 14
|
#define RG_RSSIADC_RO_BIT_SZ 4
|
#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
|
#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
|
#define RG_RX_ADC_I_RO_BIT_SFT 15
|
#define RG_RX_ADC_I_RO_BIT_HI 22
|
#define RG_RX_ADC_I_RO_BIT_SZ 8
|
#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
|
#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
|
#define RG_RX_ADC_Q_RO_BIT_SFT 23
|
#define RG_RX_ADC_Q_RO_BIT_HI 30
|
#define RG_RX_ADC_Q_RO_BIT_SZ 8
|
#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
|
#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
|
#define RG_DPL_RFCTRL_F_SFT 0
|
#define RG_DPL_RFCTRL_F_HI 23
|
#define RG_DPL_RFCTRL_F_SZ 24
|
#define RG_SX_TARGET_CNT_MSK 0x00001fff
|
#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
|
#define RG_SX_TARGET_CNT_SFT 0
|
#define RG_SX_TARGET_CNT_HI 12
|
#define RG_SX_TARGET_CNT_SZ 13
|
#define RG_RTC_OFFSET_MSK 0x000000ff
|
#define RG_RTC_OFFSET_I_MSK 0xffffff00
|
#define RG_RTC_OFFSET_SFT 0
|
#define RG_RTC_OFFSET_HI 7
|
#define RG_RTC_OFFSET_SZ 8
|
#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
|
#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
|
#define RG_RTC_CAL_TARGET_COUNT_SFT 8
|
#define RG_RTC_CAL_TARGET_COUNT_HI 19
|
#define RG_RTC_CAL_TARGET_COUNT_SZ 12
|
#define RG_RF_D_REG_MSK 0x0000ffff
|
#define RG_RF_D_REG_I_MSK 0xffff0000
|
#define RG_RF_D_REG_SFT 0
|
#define RG_RF_D_REG_HI 15
|
#define RG_RF_D_REG_SZ 16
|
#define DIRECT_MODE_MSK 0x00000001
|
#define DIRECT_MODE_I_MSK 0xfffffffe
|
#define DIRECT_MODE_SFT 0
|
#define DIRECT_MODE_HI 0
|
#define DIRECT_MODE_SZ 1
|
#define TAG_INTERLEAVE_MD_MSK 0x00000002
|
#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
|
#define TAG_INTERLEAVE_MD_SFT 1
|
#define TAG_INTERLEAVE_MD_HI 1
|
#define TAG_INTERLEAVE_MD_SZ 1
|
#define DIS_DEMAND_MSK 0x00000004
|
#define DIS_DEMAND_I_MSK 0xfffffffb
|
#define DIS_DEMAND_SFT 2
|
#define DIS_DEMAND_HI 2
|
#define DIS_DEMAND_SZ 1
|
#define SAME_ID_ALLOC_MD_MSK 0x00000008
|
#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
|
#define SAME_ID_ALLOC_MD_SFT 3
|
#define SAME_ID_ALLOC_MD_HI 3
|
#define SAME_ID_ALLOC_MD_SZ 1
|
#define HS_ACCESS_MD_MSK 0x00000010
|
#define HS_ACCESS_MD_I_MSK 0xffffffef
|
#define HS_ACCESS_MD_SFT 4
|
#define HS_ACCESS_MD_HI 4
|
#define HS_ACCESS_MD_SZ 1
|
#define SRAM_ACCESS_MD_MSK 0x00000020
|
#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
|
#define SRAM_ACCESS_MD_SFT 5
|
#define SRAM_ACCESS_MD_HI 5
|
#define SRAM_ACCESS_MD_SZ 1
|
#define NOHIT_RPASS_MD_MSK 0x00000040
|
#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
|
#define NOHIT_RPASS_MD_SFT 6
|
#define NOHIT_RPASS_MD_HI 6
|
#define NOHIT_RPASS_MD_SZ 1
|
#define DMN_FLAG_CLR_MSK 0x00000080
|
#define DMN_FLAG_CLR_I_MSK 0xffffff7f
|
#define DMN_FLAG_CLR_SFT 7
|
#define DMN_FLAG_CLR_HI 7
|
#define DMN_FLAG_CLR_SZ 1
|
#define ERR_SW_RST_N_MSK 0x00000100
|
#define ERR_SW_RST_N_I_MSK 0xfffffeff
|
#define ERR_SW_RST_N_SFT 8
|
#define ERR_SW_RST_N_HI 8
|
#define ERR_SW_RST_N_SZ 1
|
#define ALR_SW_RST_N_MSK 0x00000200
|
#define ALR_SW_RST_N_I_MSK 0xfffffdff
|
#define ALR_SW_RST_N_SFT 9
|
#define ALR_SW_RST_N_HI 9
|
#define ALR_SW_RST_N_SZ 1
|
#define MCH_SW_RST_N_MSK 0x00000400
|
#define MCH_SW_RST_N_I_MSK 0xfffffbff
|
#define MCH_SW_RST_N_SFT 10
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#define MCH_SW_RST_N_HI 10
|
#define MCH_SW_RST_N_SZ 1
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#define TAG_SW_RST_N_MSK 0x00000800
|
#define TAG_SW_RST_N_I_MSK 0xfffff7ff
|
#define TAG_SW_RST_N_SFT 11
|
#define TAG_SW_RST_N_HI 11
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#define TAG_SW_RST_N_SZ 1
|
#define ABT_SW_RST_N_MSK 0x00001000
|
#define ABT_SW_RST_N_I_MSK 0xffffefff
|
#define ABT_SW_RST_N_SFT 12
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#define ABT_SW_RST_N_HI 12
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#define ABT_SW_RST_N_SZ 1
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#define MMU_VER_MSK 0x0000e000
|
#define MMU_VER_I_MSK 0xffff1fff
|
#define MMU_VER_SFT 13
|
#define MMU_VER_HI 15
|
#define MMU_VER_SZ 3
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#define MMU_SHARE_MCU_MSK 0x00ff0000
|
#define MMU_SHARE_MCU_I_MSK 0xff00ffff
|
#define MMU_SHARE_MCU_SFT 16
|
#define MMU_SHARE_MCU_HI 23
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#define MMU_SHARE_MCU_SZ 8
|
#define HS_WR_MSK 0x00000001
|
#define HS_WR_I_MSK 0xfffffffe
|
#define HS_WR_SFT 0
|
#define HS_WR_HI 0
|
#define HS_WR_SZ 1
|
#define HS_FLAG_MSK 0x00000010
|
#define HS_FLAG_I_MSK 0xffffffef
|
#define HS_FLAG_SFT 4
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#define HS_FLAG_HI 4
|
#define HS_FLAG_SZ 1
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#define HS_ID_MSK 0x00007f00
|
#define HS_ID_I_MSK 0xffff80ff
|
#define HS_ID_SFT 8
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#define HS_ID_HI 14
|
#define HS_ID_SZ 7
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#define HS_CHANNEL_MSK 0x000f0000
|
#define HS_CHANNEL_I_MSK 0xfff0ffff
|
#define HS_CHANNEL_SFT 16
|
#define HS_CHANNEL_HI 19
|
#define HS_CHANNEL_SZ 4
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#define HS_PAGE_MSK 0x00f00000
|
#define HS_PAGE_I_MSK 0xff0fffff
|
#define HS_PAGE_SFT 20
|
#define HS_PAGE_HI 23
|
#define HS_PAGE_SZ 4
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#define HS_DATA_MSK 0xff000000
|
#define HS_DATA_I_MSK 0x00ffffff
|
#define HS_DATA_SFT 24
|
#define HS_DATA_HI 31
|
#define HS_DATA_SZ 8
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#define CPU_POR0_MSK 0x0000000f
|
#define CPU_POR0_I_MSK 0xfffffff0
|
#define CPU_POR0_SFT 0
|
#define CPU_POR0_HI 3
|
#define CPU_POR0_SZ 4
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#define CPU_POR1_MSK 0x000000f0
|
#define CPU_POR1_I_MSK 0xffffff0f
|
#define CPU_POR1_SFT 4
|
#define CPU_POR1_HI 7
|
#define CPU_POR1_SZ 4
|
#define CPU_POR2_MSK 0x00000f00
|
#define CPU_POR2_I_MSK 0xfffff0ff
|
#define CPU_POR2_SFT 8
|
#define CPU_POR2_HI 11
|
#define CPU_POR2_SZ 4
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#define CPU_POR3_MSK 0x0000f000
|
#define CPU_POR3_I_MSK 0xffff0fff
|
#define CPU_POR3_SFT 12
|
#define CPU_POR3_HI 15
|
#define CPU_POR3_SZ 4
|
#define CPU_POR4_MSK 0x000f0000
|
#define CPU_POR4_I_MSK 0xfff0ffff
|
#define CPU_POR4_SFT 16
|
#define CPU_POR4_HI 19
|
#define CPU_POR4_SZ 4
|
#define CPU_POR5_MSK 0x00f00000
|
#define CPU_POR5_I_MSK 0xff0fffff
|
#define CPU_POR5_SFT 20
|
#define CPU_POR5_HI 23
|
#define CPU_POR5_SZ 4
|
#define CPU_POR6_MSK 0x0f000000
|
#define CPU_POR6_I_MSK 0xf0ffffff
|
#define CPU_POR6_SFT 24
|
#define CPU_POR6_HI 27
|
#define CPU_POR6_SZ 4
|
#define CPU_POR7_MSK 0xf0000000
|
#define CPU_POR7_I_MSK 0x0fffffff
|
#define CPU_POR7_SFT 28
|
#define CPU_POR7_HI 31
|
#define CPU_POR7_SZ 4
|
#define CPU_POR8_MSK 0x0000000f
|
#define CPU_POR8_I_MSK 0xfffffff0
|
#define CPU_POR8_SFT 0
|
#define CPU_POR8_HI 3
|
#define CPU_POR8_SZ 4
|
#define CPU_POR9_MSK 0x000000f0
|
#define CPU_POR9_I_MSK 0xffffff0f
|
#define CPU_POR9_SFT 4
|
#define CPU_POR9_HI 7
|
#define CPU_POR9_SZ 4
|
#define CPU_PORA_MSK 0x00000f00
|
#define CPU_PORA_I_MSK 0xfffff0ff
|
#define CPU_PORA_SFT 8
|
#define CPU_PORA_HI 11
|
#define CPU_PORA_SZ 4
|
#define CPU_PORB_MSK 0x0000f000
|
#define CPU_PORB_I_MSK 0xffff0fff
|
#define CPU_PORB_SFT 12
|
#define CPU_PORB_HI 15
|
#define CPU_PORB_SZ 4
|
#define CPU_PORC_MSK 0x000f0000
|
#define CPU_PORC_I_MSK 0xfff0ffff
|
#define CPU_PORC_SFT 16
|
#define CPU_PORC_HI 19
|
#define CPU_PORC_SZ 4
|
#define CPU_PORD_MSK 0x00f00000
|
#define CPU_PORD_I_MSK 0xff0fffff
|
#define CPU_PORD_SFT 20
|
#define CPU_PORD_HI 23
|
#define CPU_PORD_SZ 4
|
#define CPU_PORE_MSK 0x0f000000
|
#define CPU_PORE_I_MSK 0xf0ffffff
|
#define CPU_PORE_SFT 24
|
#define CPU_PORE_HI 27
|
#define CPU_PORE_SZ 4
|
#define CPU_PORF_MSK 0xf0000000
|
#define CPU_PORF_I_MSK 0x0fffffff
|
#define CPU_PORF_SFT 28
|
#define CPU_PORF_HI 31
|
#define CPU_PORF_SZ 4
|
#define ACC_WR_LEN_MSK 0x0000003f
|
#define ACC_WR_LEN_I_MSK 0xffffffc0
|
#define ACC_WR_LEN_SFT 0
|
#define ACC_WR_LEN_HI 5
|
#define ACC_WR_LEN_SZ 6
|
#define ACC_RD_LEN_MSK 0x00003f00
|
#define ACC_RD_LEN_I_MSK 0xffffc0ff
|
#define ACC_RD_LEN_SFT 8
|
#define ACC_RD_LEN_HI 13
|
#define ACC_RD_LEN_SZ 6
|
#define REQ_NACK_CLR_MSK 0x00008000
|
#define REQ_NACK_CLR_I_MSK 0xffff7fff
|
#define REQ_NACK_CLR_SFT 15
|
#define REQ_NACK_CLR_HI 15
|
#define REQ_NACK_CLR_SZ 1
|
#define NACK_FLAG_BUS_MSK 0xffff0000
|
#define NACK_FLAG_BUS_I_MSK 0x0000ffff
|
#define NACK_FLAG_BUS_SFT 16
|
#define NACK_FLAG_BUS_HI 31
|
#define NACK_FLAG_BUS_SZ 16
|
#define DMN_R_PASS_MSK 0x0000ffff
|
#define DMN_R_PASS_I_MSK 0xffff0000
|
#define DMN_R_PASS_SFT 0
|
#define DMN_R_PASS_HI 15
|
#define DMN_R_PASS_SZ 16
|
#define PARA_ALC_RLS_MSK 0x00010000
|
#define PARA_ALC_RLS_I_MSK 0xfffeffff
|
#define PARA_ALC_RLS_SFT 16
|
#define PARA_ALC_RLS_HI 16
|
#define PARA_ALC_RLS_SZ 1
|
#define REQ_PORNS_CHGEN_MSK 0x01000000
|
#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
|
#define REQ_PORNS_CHGEN_SFT 24
|
#define REQ_PORNS_CHGEN_HI 24
|
#define REQ_PORNS_CHGEN_SZ 1
|
#define ALC_ABT_ID_MSK 0x0000007f
|
#define ALC_ABT_ID_I_MSK 0xffffff80
|
#define ALC_ABT_ID_SFT 0
|
#define ALC_ABT_ID_HI 6
|
#define ALC_ABT_ID_SZ 7
|
#define ALC_ABT_INT_MSK 0x00008000
|
#define ALC_ABT_INT_I_MSK 0xffff7fff
|
#define ALC_ABT_INT_SFT 15
|
#define ALC_ABT_INT_HI 15
|
#define ALC_ABT_INT_SZ 1
|
#define RLS_ABT_ID_MSK 0x007f0000
|
#define RLS_ABT_ID_I_MSK 0xff80ffff
|
#define RLS_ABT_ID_SFT 16
|
#define RLS_ABT_ID_HI 22
|
#define RLS_ABT_ID_SZ 7
|
#define RLS_ABT_INT_MSK 0x80000000
|
#define RLS_ABT_INT_I_MSK 0x7fffffff
|
#define RLS_ABT_INT_SFT 31
|
#define RLS_ABT_INT_HI 31
|
#define RLS_ABT_INT_SZ 1
|
#define DEBUG_CTL_MSK 0x000000ff
|
#define DEBUG_CTL_I_MSK 0xffffff00
|
#define DEBUG_CTL_SFT 0
|
#define DEBUG_CTL_HI 7
|
#define DEBUG_CTL_SZ 8
|
#define DEBUG_H16_MSK 0x00000100
|
#define DEBUG_H16_I_MSK 0xfffffeff
|
#define DEBUG_H16_SFT 8
|
#define DEBUG_H16_HI 8
|
#define DEBUG_H16_SZ 1
|
#define DEBUG_OUT_MSK 0xffffffff
|
#define DEBUG_OUT_I_MSK 0x00000000
|
#define DEBUG_OUT_SFT 0
|
#define DEBUG_OUT_HI 31
|
#define DEBUG_OUT_SZ 32
|
#define ALC_ERR_MSK 0x00000001
|
#define ALC_ERR_I_MSK 0xfffffffe
|
#define ALC_ERR_SFT 0
|
#define ALC_ERR_HI 0
|
#define ALC_ERR_SZ 1
|
#define RLS_ERR_MSK 0x00000002
|
#define RLS_ERR_I_MSK 0xfffffffd
|
#define RLS_ERR_SFT 1
|
#define RLS_ERR_HI 1
|
#define RLS_ERR_SZ 1
|
#define AL_STATE_MSK 0x00000700
|
#define AL_STATE_I_MSK 0xfffff8ff
|
#define AL_STATE_SFT 8
|
#define AL_STATE_HI 10
|
#define AL_STATE_SZ 3
|
#define RL_STATE_MSK 0x00007000
|
#define RL_STATE_I_MSK 0xffff8fff
|
#define RL_STATE_SFT 12
|
#define RL_STATE_HI 14
|
#define RL_STATE_SZ 3
|
#define ALC_ERR_ID_MSK 0x007f0000
|
#define ALC_ERR_ID_I_MSK 0xff80ffff
|
#define ALC_ERR_ID_SFT 16
|
#define ALC_ERR_ID_HI 22
|
#define ALC_ERR_ID_SZ 7
|
#define RLS_ERR_ID_MSK 0x7f000000
|
#define RLS_ERR_ID_I_MSK 0x80ffffff
|
#define RLS_ERR_ID_SFT 24
|
#define RLS_ERR_ID_HI 30
|
#define RLS_ERR_ID_SZ 7
|
#define DMN_NOHIT_FLAG_MSK 0x00000001
|
#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
|
#define DMN_NOHIT_FLAG_SFT 0
|
#define DMN_NOHIT_FLAG_HI 0
|
#define DMN_NOHIT_FLAG_SZ 1
|
#define DMN_FLAG_MSK 0x00000002
|
#define DMN_FLAG_I_MSK 0xfffffffd
|
#define DMN_FLAG_SFT 1
|
#define DMN_FLAG_HI 1
|
#define DMN_FLAG_SZ 1
|
#define DMN_WR_MSK 0x00000008
|
#define DMN_WR_I_MSK 0xfffffff7
|
#define DMN_WR_SFT 3
|
#define DMN_WR_HI 3
|
#define DMN_WR_SZ 1
|
#define DMN_PORT_MSK 0x000000f0
|
#define DMN_PORT_I_MSK 0xffffff0f
|
#define DMN_PORT_SFT 4
|
#define DMN_PORT_HI 7
|
#define DMN_PORT_SZ 4
|
#define DMN_NHIT_ID_MSK 0x00007f00
|
#define DMN_NHIT_ID_I_MSK 0xffff80ff
|
#define DMN_NHIT_ID_SFT 8
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#define DMN_NHIT_ID_HI 14
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#define DMN_NHIT_ID_SZ 7
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#define DMN_NHIT_ADDR_MSK 0xffff0000
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#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
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#define DMN_NHIT_ADDR_SFT 16
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#define DMN_NHIT_ADDR_HI 31
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#define DMN_NHIT_ADDR_SZ 16
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#define TX_MOUNT_MSK 0x000000ff
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#define TX_MOUNT_I_MSK 0xffffff00
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#define TX_MOUNT_SFT 0
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#define TX_MOUNT_HI 7
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#define TX_MOUNT_SZ 8
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#define RX_MOUNT_MSK 0x0000ff00
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#define RX_MOUNT_I_MSK 0xffff00ff
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#define RX_MOUNT_SFT 8
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#define RX_MOUNT_HI 15
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#define RX_MOUNT_SZ 8
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#define AVA_TAG_MSK 0x01ff0000
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#define AVA_TAG_I_MSK 0xfe00ffff
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#define AVA_TAG_SFT 16
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#define AVA_TAG_HI 24
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#define AVA_TAG_SZ 9
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#define PKTBUF_FULL_MSK 0x80000000
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#define PKTBUF_FULL_I_MSK 0x7fffffff
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#define PKTBUF_FULL_SFT 31
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#define PKTBUF_FULL_HI 31
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#define PKTBUF_FULL_SZ 1
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#define DMN_NOHIT_MCU_MSK 0x00000001
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#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
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#define DMN_NOHIT_MCU_SFT 0
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#define DMN_NOHIT_MCU_HI 0
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#define DMN_NOHIT_MCU_SZ 1
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#define DMN_MCU_FLAG_MSK 0x00000002
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#define DMN_MCU_FLAG_I_MSK 0xfffffffd
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#define DMN_MCU_FLAG_SFT 1
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#define DMN_MCU_FLAG_HI 1
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#define DMN_MCU_FLAG_SZ 1
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#define DMN_MCU_WR_MSK 0x00000008
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#define DMN_MCU_WR_I_MSK 0xfffffff7
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#define DMN_MCU_WR_SFT 3
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#define DMN_MCU_WR_HI 3
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#define DMN_MCU_WR_SZ 1
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#define DMN_MCU_PORT_MSK 0x000000f0
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#define DMN_MCU_PORT_I_MSK 0xffffff0f
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#define DMN_MCU_PORT_SFT 4
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#define DMN_MCU_PORT_HI 7
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#define DMN_MCU_PORT_SZ 4
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#define DMN_MCU_ID_MSK 0x00007f00
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#define DMN_MCU_ID_I_MSK 0xffff80ff
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#define DMN_MCU_ID_SFT 8
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#define DMN_MCU_ID_HI 14
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#define DMN_MCU_ID_SZ 7
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#define DMN_MCU_ADDR_MSK 0xffff0000
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#define DMN_MCU_ADDR_I_MSK 0x0000ffff
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#define DMN_MCU_ADDR_SFT 16
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#define DMN_MCU_ADDR_HI 31
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#define DMN_MCU_ADDR_SZ 16
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#define MB_IDTBL_31_0_MSK 0xffffffff
|
#define MB_IDTBL_31_0_I_MSK 0x00000000
|
#define MB_IDTBL_31_0_SFT 0
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#define MB_IDTBL_31_0_HI 31
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#define MB_IDTBL_31_0_SZ 32
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#define MB_IDTBL_63_32_MSK 0xffffffff
|
#define MB_IDTBL_63_32_I_MSK 0x00000000
|
#define MB_IDTBL_63_32_SFT 0
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#define MB_IDTBL_63_32_HI 31
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#define MB_IDTBL_63_32_SZ 32
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#define MB_IDTBL_95_64_MSK 0xffffffff
|
#define MB_IDTBL_95_64_I_MSK 0x00000000
|
#define MB_IDTBL_95_64_SFT 0
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#define MB_IDTBL_95_64_HI 31
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#define MB_IDTBL_95_64_SZ 32
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#define MB_IDTBL_127_96_MSK 0xffffffff
|
#define MB_IDTBL_127_96_I_MSK 0x00000000
|
#define MB_IDTBL_127_96_SFT 0
|
#define MB_IDTBL_127_96_HI 31
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#define MB_IDTBL_127_96_SZ 32
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#define PKT_IDTBL_31_0_MSK 0xffffffff
|
#define PKT_IDTBL_31_0_I_MSK 0x00000000
|
#define PKT_IDTBL_31_0_SFT 0
|
#define PKT_IDTBL_31_0_HI 31
|
#define PKT_IDTBL_31_0_SZ 32
|
#define PKT_IDTBL_63_32_MSK 0xffffffff
|
#define PKT_IDTBL_63_32_I_MSK 0x00000000
|
#define PKT_IDTBL_63_32_SFT 0
|
#define PKT_IDTBL_63_32_HI 31
|
#define PKT_IDTBL_63_32_SZ 32
|
#define PKT_IDTBL_95_64_MSK 0xffffffff
|
#define PKT_IDTBL_95_64_I_MSK 0x00000000
|
#define PKT_IDTBL_95_64_SFT 0
|
#define PKT_IDTBL_95_64_HI 31
|
#define PKT_IDTBL_95_64_SZ 32
|
#define PKT_IDTBL_127_96_MSK 0xffffffff
|
#define PKT_IDTBL_127_96_I_MSK 0x00000000
|
#define PKT_IDTBL_127_96_SFT 0
|
#define PKT_IDTBL_127_96_HI 31
|
#define PKT_IDTBL_127_96_SZ 32
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#define DMN_IDTBL_31_0_MSK 0xffffffff
|
#define DMN_IDTBL_31_0_I_MSK 0x00000000
|
#define DMN_IDTBL_31_0_SFT 0
|
#define DMN_IDTBL_31_0_HI 31
|
#define DMN_IDTBL_31_0_SZ 32
|
#define DMN_IDTBL_63_32_MSK 0xffffffff
|
#define DMN_IDTBL_63_32_I_MSK 0x00000000
|
#define DMN_IDTBL_63_32_SFT 0
|
#define DMN_IDTBL_63_32_HI 31
|
#define DMN_IDTBL_63_32_SZ 32
|
#define DMN_IDTBL_95_64_MSK 0xffffffff
|
#define DMN_IDTBL_95_64_I_MSK 0x00000000
|
#define DMN_IDTBL_95_64_SFT 0
|
#define DMN_IDTBL_95_64_HI 31
|
#define DMN_IDTBL_95_64_SZ 32
|
#define DMN_IDTBL_127_96_MSK 0xffffffff
|
#define DMN_IDTBL_127_96_I_MSK 0x00000000
|
#define DMN_IDTBL_127_96_SFT 0
|
#define DMN_IDTBL_127_96_HI 31
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#define DMN_IDTBL_127_96_SZ 32
|
#define NEQ_MB_ID_31_0_MSK 0xffffffff
|
#define NEQ_MB_ID_31_0_I_MSK 0x00000000
|
#define NEQ_MB_ID_31_0_SFT 0
|
#define NEQ_MB_ID_31_0_HI 31
|
#define NEQ_MB_ID_31_0_SZ 32
|
#define NEQ_MB_ID_63_32_MSK 0xffffffff
|
#define NEQ_MB_ID_63_32_I_MSK 0x00000000
|
#define NEQ_MB_ID_63_32_SFT 0
|
#define NEQ_MB_ID_63_32_HI 31
|
#define NEQ_MB_ID_63_32_SZ 32
|
#define NEQ_MB_ID_95_64_MSK 0xffffffff
|
#define NEQ_MB_ID_95_64_I_MSK 0x00000000
|
#define NEQ_MB_ID_95_64_SFT 0
|
#define NEQ_MB_ID_95_64_HI 31
|
#define NEQ_MB_ID_95_64_SZ 32
|
#define NEQ_MB_ID_127_96_MSK 0xffffffff
|
#define NEQ_MB_ID_127_96_I_MSK 0x00000000
|
#define NEQ_MB_ID_127_96_SFT 0
|
#define NEQ_MB_ID_127_96_HI 31
|
#define NEQ_MB_ID_127_96_SZ 32
|
#define NEQ_PKT_ID_31_0_MSK 0xffffffff
|
#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
|
#define NEQ_PKT_ID_31_0_SFT 0
|
#define NEQ_PKT_ID_31_0_HI 31
|
#define NEQ_PKT_ID_31_0_SZ 32
|
#define NEQ_PKT_ID_63_32_MSK 0xffffffff
|
#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
|
#define NEQ_PKT_ID_63_32_SFT 0
|
#define NEQ_PKT_ID_63_32_HI 31
|
#define NEQ_PKT_ID_63_32_SZ 32
|
#define NEQ_PKT_ID_95_64_MSK 0xffffffff
|
#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
|
#define NEQ_PKT_ID_95_64_SFT 0
|
#define NEQ_PKT_ID_95_64_HI 31
|
#define NEQ_PKT_ID_95_64_SZ 32
|
#define NEQ_PKT_ID_127_96_MSK 0xffffffff
|
#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
|
#define NEQ_PKT_ID_127_96_SFT 0
|
#define NEQ_PKT_ID_127_96_HI 31
|
#define NEQ_PKT_ID_127_96_SZ 32
|
#define ALC_NOCHG_ID_MSK 0x0000007f
|
#define ALC_NOCHG_ID_I_MSK 0xffffff80
|
#define ALC_NOCHG_ID_SFT 0
|
#define ALC_NOCHG_ID_HI 6
|
#define ALC_NOCHG_ID_SZ 7
|
#define ALC_NOCHG_INT_MSK 0x00008000
|
#define ALC_NOCHG_INT_I_MSK 0xffff7fff
|
#define ALC_NOCHG_INT_SFT 15
|
#define ALC_NOCHG_INT_HI 15
|
#define ALC_NOCHG_INT_SZ 1
|
#define NEQ_PKT_FLAG_MSK 0x00010000
|
#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
|
#define NEQ_PKT_FLAG_SFT 16
|
#define NEQ_PKT_FLAG_HI 16
|
#define NEQ_PKT_FLAG_SZ 1
|
#define NEQ_MB_FLAG_MSK 0x01000000
|
#define NEQ_MB_FLAG_I_MSK 0xfeffffff
|
#define NEQ_MB_FLAG_SFT 24
|
#define NEQ_MB_FLAG_HI 24
|
#define NEQ_MB_FLAG_SZ 1
|
#define SRAM_TAG_0_MSK 0x0000ffff
|
#define SRAM_TAG_0_I_MSK 0xffff0000
|
#define SRAM_TAG_0_SFT 0
|
#define SRAM_TAG_0_HI 15
|
#define SRAM_TAG_0_SZ 16
|
#define SRAM_TAG_1_MSK 0xffff0000
|
#define SRAM_TAG_1_I_MSK 0x0000ffff
|
#define SRAM_TAG_1_SFT 16
|
#define SRAM_TAG_1_HI 31
|
#define SRAM_TAG_1_SZ 16
|
#define SRAM_TAG_2_MSK 0x0000ffff
|
#define SRAM_TAG_2_I_MSK 0xffff0000
|
#define SRAM_TAG_2_SFT 0
|
#define SRAM_TAG_2_HI 15
|
#define SRAM_TAG_2_SZ 16
|
#define SRAM_TAG_3_MSK 0xffff0000
|
#define SRAM_TAG_3_I_MSK 0x0000ffff
|
#define SRAM_TAG_3_SFT 16
|
#define SRAM_TAG_3_HI 31
|
#define SRAM_TAG_3_SZ 16
|
#define SRAM_TAG_4_MSK 0x0000ffff
|
#define SRAM_TAG_4_I_MSK 0xffff0000
|
#define SRAM_TAG_4_SFT 0
|
#define SRAM_TAG_4_HI 15
|
#define SRAM_TAG_4_SZ 16
|
#define SRAM_TAG_5_MSK 0xffff0000
|
#define SRAM_TAG_5_I_MSK 0x0000ffff
|
#define SRAM_TAG_5_SFT 16
|
#define SRAM_TAG_5_HI 31
|
#define SRAM_TAG_5_SZ 16
|
#define SRAM_TAG_6_MSK 0x0000ffff
|
#define SRAM_TAG_6_I_MSK 0xffff0000
|
#define SRAM_TAG_6_SFT 0
|
#define SRAM_TAG_6_HI 15
|
#define SRAM_TAG_6_SZ 16
|
#define SRAM_TAG_7_MSK 0xffff0000
|
#define SRAM_TAG_7_I_MSK 0x0000ffff
|
#define SRAM_TAG_7_SFT 16
|
#define SRAM_TAG_7_HI 31
|
#define SRAM_TAG_7_SZ 16
|
#define SRAM_TAG_8_MSK 0x0000ffff
|
#define SRAM_TAG_8_I_MSK 0xffff0000
|
#define SRAM_TAG_8_SFT 0
|
#define SRAM_TAG_8_HI 15
|
#define SRAM_TAG_8_SZ 16
|
#define SRAM_TAG_9_MSK 0xffff0000
|
#define SRAM_TAG_9_I_MSK 0x0000ffff
|
#define SRAM_TAG_9_SFT 16
|
#define SRAM_TAG_9_HI 31
|
#define SRAM_TAG_9_SZ 16
|
#define SRAM_TAG_10_MSK 0x0000ffff
|
#define SRAM_TAG_10_I_MSK 0xffff0000
|
#define SRAM_TAG_10_SFT 0
|
#define SRAM_TAG_10_HI 15
|
#define SRAM_TAG_10_SZ 16
|
#define SRAM_TAG_11_MSK 0xffff0000
|
#define SRAM_TAG_11_I_MSK 0x0000ffff
|
#define SRAM_TAG_11_SFT 16
|
#define SRAM_TAG_11_HI 31
|
#define SRAM_TAG_11_SZ 16
|
#define SRAM_TAG_12_MSK 0x0000ffff
|
#define SRAM_TAG_12_I_MSK 0xffff0000
|
#define SRAM_TAG_12_SFT 0
|
#define SRAM_TAG_12_HI 15
|
#define SRAM_TAG_12_SZ 16
|
#define SRAM_TAG_13_MSK 0xffff0000
|
#define SRAM_TAG_13_I_MSK 0x0000ffff
|
#define SRAM_TAG_13_SFT 16
|
#define SRAM_TAG_13_HI 31
|
#define SRAM_TAG_13_SZ 16
|
#define SRAM_TAG_14_MSK 0x0000ffff
|
#define SRAM_TAG_14_I_MSK 0xffff0000
|
#define SRAM_TAG_14_SFT 0
|
#define SRAM_TAG_14_HI 15
|
#define SRAM_TAG_14_SZ 16
|
#define SRAM_TAG_15_MSK 0xffff0000
|
#define SRAM_TAG_15_I_MSK 0x0000ffff
|
#define SRAM_TAG_15_SFT 16
|
#define SRAM_TAG_15_HI 31
|
#define SRAM_TAG_15_SZ 16
|
