/*
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* Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
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* Copyright (c) 2015 iComm Corporation
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HCTRL_H_
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#define _HCTRL_H_
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#define MAX_FRAME_SIZE 4096
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#define SSV6XXX_INT_RX 0x00000001
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#define SSV6XXX_INT_TX 0x00000002
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#define SSV6XXX_INT_SOC 0x00000004
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#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
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#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
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#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
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#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
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#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
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#define IFDEV(_ct) ((_ct)->shi->dev)
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#define IFOPS(_ct) ((_ct)->shi->if_ops)
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#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
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#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
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#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
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{ \
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u32 _regval; \
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if(HCI_REG_READ(_ct, _reg, &_regval)); \
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_regval &= ~(_clr); \
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_regval |= (_set); \
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if(HCI_REG_WRITE(_ct, _reg, _regval)); \
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}
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#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
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#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
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#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
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#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
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struct ssv6xxx_hci_ctrl {
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struct ssv6xxx_hci_info *shi;
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spinlock_t int_lock;
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u32 int_status;
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u32 int_mask;
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struct mutex txq_mask_lock;
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u32 txq_mask;
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struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
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struct mutex hci_mutex;
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bool hci_start;
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struct sk_buff *rx_buf;
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u32 rx_pkt;
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struct workqueue_struct *hci_work_queue;
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struct work_struct hci_rx_work;
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#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
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struct work_struct hci_tx_work;
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#else
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struct work_struct hci_tx_work[SSV_HW_TXQ_NUM];
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#endif
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u32 read_rs0_info_fail;
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u32 read_rs1_info_fail;
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u32 rx_work_running;
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u32 isr_running;
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u32 xmit_running;
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u32 isr_summary_eable;
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u32 isr_routine_time;
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u32 isr_tx_time;
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u32 isr_rx_time;
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u32 isr_idle_time;
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u32 isr_rx_idle_time;
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u32 isr_miss_cnt;
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unsigned long prev_isr_jiffes;
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unsigned long prev_rx_isr_jiffes;
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#ifdef CONFIG_SSV6XXX_DEBUGFS
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struct dentry *debugfs_dir;
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u32 isr_mib_enable;
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u32 isr_mib_reset;
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long long isr_total_time;
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long long isr_tx_io_time;
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long long isr_rx_io_time;
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u32 isr_rx_io_count;
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u32 isr_tx_io_count;
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long long isr_rx_proc_time;
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#ifdef CONFIG_IRQ_DEBUG_COUNT
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bool irq_enable;
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u32 irq_count;
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u32 invalid_irq_count;
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u32 tx_irq_count;
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u32 real_tx_irq_count;
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u32 rx_irq_count;
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u32 irq_rx_pkt_count;
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u32 irq_tx_pkt_count;
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#endif
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#endif
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};
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struct ssv6xxx_hci_txq_info {
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u32 tx_use_page:8;
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u32 tx_use_id:6;
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u32 txq0_size:4;
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u32 txq1_size:4;
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u32 txq2_size:5;
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u32 txq3_size:5;
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};
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struct ssv6xxx_hci_txq_info2 {
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u32 tx_use_page:9;
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u32 tx_use_id:8;
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u32 txq4_size:4;
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u32 rsvd:11;
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};
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struct ssv6xxx_hw_resource
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{
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u32 free_tx_page;
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u32 free_tx_id;
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int max_tx_frame[SSV_HW_TXQ_NUM];
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};
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static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl, irq_handler_t irq_handler)
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{
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if(hctrl->shi->if_ops->irq_request)
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hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler, hctrl);
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}
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static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
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{
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if(hctrl->shi->if_ops->irq_enable)
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hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
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}
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static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
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{
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if(hctrl->shi->if_ops->irq_disable)
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hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
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}
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static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl, int *status)
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{
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if(hctrl->shi->if_ops->irq_getstatus)
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return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
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return 0;
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}
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static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl, int mask)
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{
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if(hctrl->shi->if_ops->irq_setmask)
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hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
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}
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static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
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{
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if(hctrl->shi->if_ops->irq_trigger)
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hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
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}
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static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
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{
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if(hctrl->shi->if_ops->pmu_wakeup)
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hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
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}
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static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8 *data, u32 size)
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{
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if(hctrl->shi->if_ops->write_sram)
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return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data, size);
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return 0;
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}
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#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
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#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
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#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
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#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
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#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
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#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
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#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
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#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
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#endif
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