/*
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* Broadcom SiliconBackplane ARM definitions
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _sbhndarm_h_
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#define _sbhndarm_h_
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#ifdef DONGLEBUILD
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#include <arminc.h>
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#include <sbconfig.h>
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/* register offsets */
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#define ARM7_CORECTL 0
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/* bits in corecontrol */
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#define ACC_FORCED_RST 0x1
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#define ACC_SERRINT 0x2
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#define ACC_WFICLKSTOP 0x4
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#if !defined(__ARM_ARCH_7A__)
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#define ACC_NOTSLEEPINGCLKREQ_SHIFT 24
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#endif /* !__ARM_ARCH_7A__ */
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#if defined(__ARM_ARCH_7A__)
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#define ACC_FORCECLOCKRATIO (0x1u << 8)
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#define ACC_CLOCKRATIO_SHIFT (9u)
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#define ACC_CLOCKRATIO_MASK (0xFu << ACC_CLOCKRATIO_SHIFT)
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#define ACC_CLOCKRATIO_1_TO_1 (0u)
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#define ACC_CLOCKRATIO_2_TO_1 (1u)
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#define ACC_CLOCKRATIO_3_TO_1 (2u)
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#define ACC_CLOCKRATIO_4_TO_1 (3u)
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#define ACC_FASTCLOCKCHANNEL_SHIFT (24u)
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#define ACC_FASTCLOCKCHANNEL_MASK (0x3u << ACC_FASTCLOCKCHANNEL_SHIFT)
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#define ACC_NUM_FASTCLOCKS_SHIFT (2u)
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#define ACC_NUM_FASTCLOCKS_MASK (0x3u << ACC_NUM_FASTCLOCKS_SHIFT)
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#define ACC_NOTSLEEPINGCLKREQ_SHIFT (4u)
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#define ACC_NOTSLEEPINGCLKREQ_MASK (0x3u << ACC_NOT_SLEEPING_CLKREQ_SHIFT)
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#define ACC_NOTSLEEPING_ALP (0u)
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#define ACC_NOTSLEEPING_HT (1u)
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#define ACC_NOTSLEEPING_ALP_HT_AVAIL (2u)
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#define ACC_NOTSLEEPING_HT_AVAIL (3u)
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#elif defined(__ARM_ARCH_7R__) /* CR4 */
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#define ACC_FORCECLOCKRATIO (1u << 7u)
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#define ACC_CLOCKRATIO_SHIFT 8u
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#define ACC_CLOCKRATIO_MASK (0xFu << ACC_CLOCKRATIO_SHIFT)
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#define ACC_CLOCKMODE_SHIFT 12u
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#define ACC_CLOCKMODE_MASK (7u << ACC_CLOCKMODE_SHIFT)
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#define ACC_NOTSLEEPCLKREQ0 3u
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#define ACC_NOTSLEEPCLKREQ1 18u
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#define ACC_FLOPSPROTECT (1u << 20u)
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#define ACC_CLOCKRATIO_1_TO_1 (0u)
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#define ACC_CLOCKRATIO_2_TO_1 (4u)
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#endif /* __ARM_ARCH_7A__ */
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#define ACC_CLOCKMODE_SAME (0) /**< BP and CPU clock are the same */
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#define ACC_CLOCKMODE_ASYNC (1) /**< BP and CPU clock are asynchronous */
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#define ACC_CLOCKMODE_SYNCH (2) /**< BP and CPU clock are synch, ratio 1:1 or 1:2 */
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/* Request ALP on backplane bit 3 and 18 */
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#define ACC_REQALP ((1<<ACC_NOTSLEEPCLKREQ0) | (1<<ACC_NOTSLEEPCLKREQ1))
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#define ACC_MPU_SHIFT 25u
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#define ACC_MPU_MASK (0x1u << ACC_MPU_SHIFT)
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#define ACC_MPU_REGION_CNT_MASK 0x7u
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#define ACC_MPU_REGION_CNT_SHIFT 3u
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#define ACC_MPU_SECURE_SHIFT 27u
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#define ACC_MPU_SECURE_MASK (0x1u << ACC_MPU_SECURE_SHIFT)
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#define ACC_MPU_READ_SHIFT 30u
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#define ACC_MPU_READ_MASK (0x1u << ACC_MPU_READ_SHIFT)
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#define ACC_MPU_WRITE_SHIFT 29u
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#define ACC_MPU_WRITE_MASK (0x1u << ACC_MPU_WRITE_SHIFT)
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#define ACC_MPU_VALID_SHIFT 31u
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#define ACC_MPU_VALID_MASK (0x1u << ACC_MPU_VALID_SHIFT)
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/* arm resetlog */
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#define SBRESETLOG 0x1
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#define SERRORLOG 0x2
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/* arm core-specific control flags */
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#define SICF_REMAP_MSK 0x001c
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#define SICF_REMAP_NONE 0
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#define SICF_REMAP_ROM 0x0004
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#define SIFC_REMAP_FLASH 0x0008
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/* misc core-specific defines */
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#if defined(__ARM_ARCH_7M__)
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/* cortex-m3 */
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/* backplane related stuff */
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#define ARM_CORE_ID ARMCM3_CORE_ID /**< arm coreid */
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#define SI_ARM_ROM SI_ARMCM3_ROM /**< ROM backplane/system address */
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#define SI_ARM_SRAM2 SI_ARMCM3_SRAM2 /**< RAM backplane address when remap is 1 or 2 */
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/* core registers offsets */
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#define ARMCM3_CYCLECNT 0x90 /**< Cortex-M3 core registers offsets */
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#define ARMCM3_INTTIMER 0x94
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#define ARMCM3_INTMASK 0x98
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#define ARMCM3_INTSTATUS 0x9c
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/* interrupt/exception */
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#define ARMCM3_NUMINTS 16 /**< # of external interrupts */
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#define ARMCM3_INTALL ((1 << ARMCM3_NUMINTS) - 1) /**< Interrupt mask */
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#define ARMCM3_SHARED_INT 0 /**< Interrupt shared by multiple cores */
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#define ARMCM3_INT(i) (1 << (i)) /**< Individual interrupt enable/disable */
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/* intmask/intstatus bits */
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#define ARMCM3_INTMASK_TIMER 0x1
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#define ARMCM3_INTMASK_SYSRESET 0x4
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#define ARMCM3_INTMASK_LOCKUP 0x8
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/*
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* Overlay Support in Rev 5
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*/
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#define ARMCM3_OVL_VALID_SHIFT 0
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#define ARMCM3_OVL_VALID 1
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#define ARMCM3_OVL_SZ_SHIFT 1
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#define ARMCM3_OVL_SZ_MASK 0x0000000e
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#define ARMCM3_OVL_SZ_512B 0 /* 512B */
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#define ARMCM3_OVL_SZ_1KB 1 /* 1KB */
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#define ARMCM3_OVL_SZ_2KB 2 /* 2KB */
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#define ARMCM3_OVL_SZ_4KB 3 /* 4KB */
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#define ARMCM3_OVL_SZ_8KB 4 /* 8KB */
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#define ARMCM3_OVL_SZ_16KB 5 /* 16KB */
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#define ARMCM3_OVL_SZ_32KB 6 /* 32KB */
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#define ARMCM3_OVL_SZ_64KB 7 /* 64KB */
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#define ARMCM3_OVL_ADDR_SHIFT 9
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#define ARMCM3_OVL_ADDR_MASK 0x003FFE00
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#define ARMCM3_OVL_MAX 16
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#elif defined(__ARM_ARCH_7R__)
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/* cortex-r4 */
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/* backplane related stuff */
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#define ARM_CORE_ID ARMCR4_CORE_ID /**< arm coreid */
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#define SI_ARM_ROM SI_ARMCR4_ROM /**< ROM backplane/system address */
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#define SI_ARM_SRAM2 0x0 /**< In the cr4 the RAM is just not available
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* when remap is 1
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*/
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/* core registers offsets */
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#define ARMCR4_CORECTL 0
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#define ARMCR4_CORECAP 4
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#define ARMCR4_COREST 8
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#define ARMCR4_FIQRSTATUS 0x10
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#define ARMCR4_FIQMASK 0x14
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#define ARMCR4_IRQMASK 0x18
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#define ARMCR4_INTSTATUS 0x20
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#define ARMCR4_INTMASK 0x24
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#define ARMCR4_CYCLECNT 0x28
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#define ARMCR4_INTTIMER 0x2c
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#define ARMCR4_GPIOSEL 0x30
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#define ARMCR4_GPIOEN 0x34
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#define ARMCR4_BANKIDX 0x40
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#define ARMCR4_BANKINFO 0x44
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#define ARMCR4_BANKSTBY 0x48
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#define ARMCR4_BANKPDA 0x4c
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#define ARMCR4_TCAMPATCHCTRL 0x68
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#define ARMCR4_TCAMPATCHTBLBASEADDR 0x6C
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#define ARMCR4_TCAMCMDREG 0x70
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#define ARMCR4_TCAMDATAREG 0x74
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#define ARMCR4_TCAMBANKXMASKREG 0x78
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#define ARMCR4_ROMNB_MASK 0xf00
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#define ARMCR4_ROMNB_SHIFT 8
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#define ARMCR4_MSB_ROMNB_MASK 0x1E00000
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/* adjusted shift to fit 4-LSB (21 - 4 = 17) */
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#define ARMCR4_MSB_ROMNB_SHIFT 17
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#define ARMCR4_TCBBNB_MASK 0xf0
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#define ARMCR4_TCBBNB_SHIFT 4
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#define ARMCR4_TCBANB_MASK 0xf
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#define ARMCR4_TCBANB_SHIFT 0
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#define ARMCR4_MT_MASK 0x300
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#define ARMCR4_MT_SHIFT 8
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#define ARMCR4_MT_ROM 0x100
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#define ARMCR4_MT_RAM 0
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#define ARMCR4_BSZ_MASK 0x7f
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#define ARMCR4_BUNITSZ_MASK 0x200
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#define ARMCR4_BSZ_8K 8192
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#define ARMCR4_BSZ_1K 1024
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#define ARMCR4_STBY_SUPPORTED 0x400
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#define ARMCR4_STBY_TIMER_PRESENT 0x800
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#define ARMCR4_TIMER_VAL_MASK 0xfffff
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#define ARMCR4_STBY_TIMER_ENABLE (1 << 24)
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#define ARMCR4_STBY_OVERRIDE (1 << 31)
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#define ARMCR4_TCAM_ENABLE (1u << 31u)
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#define ARMCR4_TCAM_CLKENAB (1u << 30u)
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#define ARMCR4_TCAM_WRITEPROT (1u << 29u)
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#define ARMCR4_TCAM_PATCHCNT_MASK 0xfu
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#define ARMCR4_TCAM_CMD_DONE (1u << 31)
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#define ARMCR4_TCAM_MATCH (1u << 24)
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#define ARMCR4_TCAM_OPCODE_MASK (3 << 16)
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#define ARMCR4_TCAM_OPCODE_SHIFT 16
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#define ARMCR4_TCAM_ADDR_MASK 0xffff
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#define ARMCR4_TCAM_NONE (0 << ARMCR4_TCAM_OPCODE_SHIFT)
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#define ARMCR4_TCAM_READ (1 << ARMCR4_TCAM_OPCODE_SHIFT)
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#define ARMCR4_TCAM_WRITE (2 << ARMCR4_TCAM_OPCODE_SHIFT)
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#define ARMCR4_TCAM_COMPARE (3 << ARMCR4_TCAM_OPCODE_SHIFT)
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#define ARMCR4_TCAM_CMD_DONE_DLY 1000
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#define ARMCR4_DATA_MASK (~0x7)
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#define ARMCR4_DATA_VALID (1u << 0)
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/* intmask/intstatus bits */
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#define ARMCR4_INTMASK_TIMER (0x1)
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#define ARMCR4_INTMASK_CLOCKSTABLE (0x20000000)
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#define CHIP_SDRENABLE(sih) (sih->boardflags2 & BFL2_SDR_EN)
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#define CHIP_TCMPROTENAB(sih) (si_arm_sflags(sih) & SISF_TCMPROT)
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/* Power Control */
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#define ARM_ENAB_MEM_CLK_GATE_SHIFT 5
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#define ROM_STBY_TIMER_4378 0xb0
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#define RAM_STBY_TIMER_4378 0x64
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#define ROM_STBY_TIMER_4387 0x10
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#define RAM_STBY_TIMER_4387 0x100
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#define RAM_STBY_DEFAULT_WAIT_TIME (3u)
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#define ROM_STBY_DEFAULT_WAIT_TIME (4u)
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#define DEFAULT_FORCE_STBY_IN_WFI (1u)
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#define ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_SHIFT (0u)
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#define ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_MASK (0xF << \
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ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_SHIFT)
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#define ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_SHIFT (8u)
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#define ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_MASK (0x3F << \
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ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_SHIFT)
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#define ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_SHIFT (16u)
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#define ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_MASK (0x1 << \
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ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_SHIFT)
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/* using CHIPID because no capabilities bit */
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#define ARM_CLKGATING_CAP(sih) ((void)(sih), (BCM4378_CHIP(sih->chip) ||\
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BCM4387_CHIP(sih->chip)))
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#define ARM_CLKGATING_ENAB(sih) (ARM_CLKGATING_CAP(sih) && 1)
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#elif defined(__ARM_ARCH_7A__)
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#if defined(CA7)
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/* backplane related stuff */
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#define ARM_CORE_ID ARMCA7_CORE_ID
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#define SI_ARM_ROM SI_ARMCA7_ROM /**< ROM backplane/system address */
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#else
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/* backplane related stuff */
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#define ARM_CORE_ID ARMCA9_CORE_ID /* arm coreid */
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#endif /* __ARM_ARCH_7A__ */
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#else /* !__ARM_ARCH_7M__ && !__ARM_ARCH_7R__ */
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#error Unrecognized ARM Architecture
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#endif /* !__ARM_ARCH_7M__ && !__ARM_ARCH_7R__ */
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#endif /* DONGLEBUILD */
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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/* cortex-m3 */
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typedef volatile struct {
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uint32 corecontrol; /* 0x0 */
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uint32 corestatus; /* 0x4 */
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uint32 PAD[1];
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uint32 biststatus; /* 0xc */
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uint32 nmiisrst; /* 0x10 */
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uint32 nmimask; /* 0x14 */
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uint32 isrmask; /* 0x18 */
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uint32 PAD[1];
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uint32 resetlog; /* 0x20 */
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uint32 gpioselect; /* 0x24 */
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uint32 gpioenable; /* 0x28 */
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uint32 PAD[1];
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uint32 bpaddrlo; /* 0x30 */
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uint32 bpaddrhi; /* 0x34 */
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uint32 bpdata; /* 0x38 */
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uint32 bpindaccess; /* 0x3c */
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uint32 ovlidx; /* 0x40 */
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uint32 ovlmatch; /* 0x44 */
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uint32 ovladdr; /* 0x48 */
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uint32 PAD[13];
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uint32 bwalloc; /* 0x80 */
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uint32 PAD[3];
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uint32 cyclecnt; /* 0x90 */
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uint32 inttimer; /* 0x94 */
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uint32 intmask; /* 0x98 */
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uint32 intstatus; /* 0x9c */
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uint32 PAD[80];
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 PAD[1];
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uint32 powerctl; /* 0x1e8 */
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} cm3regs_t;
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#define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg)
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/* cortex-R4 */
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typedef volatile struct {
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uint32 corecontrol; /* 0x0 */
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uint32 corecapabilities; /* 0x4 */
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uint32 corestatus; /* 0x8 */
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uint32 biststatus; /* 0xc */
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uint32 nmiisrst; /* 0x10 */
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uint32 nmimask; /* 0x14 */
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uint32 isrmask; /* 0x18 */
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uint32 swintreg; /* 0x1C */
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uint32 intstatus; /* 0x20 */
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uint32 intmask; /* 0x24 */
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uint32 cyclecnt; /* 0x28 */
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uint32 inttimer; /* 0x2c */
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uint32 gpioselect; /* 0x30 */
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uint32 gpioenable; /* 0x34 */
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uint32 PAD[2];
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uint32 bankidx; /* 0x40 */
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uint32 bankinfo; /* 0x44 */
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uint32 bankstbyctl; /* 0x48 */
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uint32 bankpda; /* 0x4c */
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uint32 dyn_stby_control; /* 0x50 */
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uint32 PAD[5];
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uint32 tcampatchctrl; /* 0x68 */
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uint32 tcampatchtblbaseaddr; /* 0x6c */
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uint32 tcamcmdreg; /* 0x70 */
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uint32 tcamdatareg; /* 0x74 */
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uint32 tcambankxmaskreg; /* 0x78 */
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uint32 PAD[5];
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uint32 mpucontrol; /* 0x90 */
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uint32 mpucapabilities; /* 0x94 */
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uint32 rom_reloc_addr; /* 0x98 */
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uint32 PAD[1];
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uint32 region_n_regs[16]; /* 0xa0 - 0xdc */
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uint32 PAD[16];
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uint32 initiat_n_masks[16]; /* 0x120 - 0x15c */
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uint32 PAD[32];
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 hw_war; /* 0x1e4 */
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uint32 powerctl; /* 0x1e8 */
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uint32 powerctl2; /* 0x1ec */
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} cr4regs_t;
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#define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg)
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#define SBRESETLOG_CR4 0x4
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/* cortex-A7 */
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typedef volatile struct {
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uint32 corecontrol; /* 0x0 */
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uint32 corecapabilities; /* 0x4 */
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uint32 corestatus; /* 0x8 */
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uint32 tracecontrol; /* 0xc */
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uint32 gpioselect; /* 0x10 */
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uint32 gpioenable; /* 0x14 */
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uint32 PAD[114];
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 workaround; /* 0x1e4 */
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uint32 powerctl; /* 0x1e8 */
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uint32 powerctl2; /* 0x1ec */
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} ca7regs_t;
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#define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg)
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#if defined(__ARM_ARCH_7M__)
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#define ARMREG(regs, reg) ARM_CM3_REG(regs, reg)
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#endif /* __ARM_ARCH_7M__ */
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#if defined(__ARM_ARCH_7R__)
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#define ARMREG(regs, reg) ARM_CR4_REG(regs, reg)
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#endif /* __ARM_ARCH_7R__ */
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#if defined(__ARM_ARCH_7A__)
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#define ARMREG(regs, reg) ARM_CA7_REG(regs, reg)
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#endif /* __ARM_ARCH_7A__ */
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/* MPU is present mask of ca7regs_t->corecapabilities */
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#define CAP_MPU_MASK 2000000u
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* _sbhndarm_h_ */
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