/*
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* pcicfg.h: PCI configuration constants and structures.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _h_pcicfg_
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#define _h_pcicfg_
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/* The following inside ifndef's so we don't collide with NTDDK.H */
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#ifndef PCI_MAX_BUS
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#define PCI_MAX_BUS 0x100
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#endif
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#ifndef PCI_MAX_DEVICES
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#define PCI_MAX_DEVICES 0x20
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#endif
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#ifndef PCI_MAX_FUNCTION
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#define PCI_MAX_FUNCTION 0x8
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#endif
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#ifndef PCI_INVALID_VENDORID
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#define PCI_INVALID_VENDORID 0xffff
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#endif
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#ifndef PCI_INVALID_DEVICEID
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#define PCI_INVALID_DEVICEID 0xffff
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#endif
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/* Convert between bus-slot-function-register and config addresses */
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#define PCICFG_BUS_SHIFT 16 /* Bus shift */
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#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
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#define PCICFG_FUN_SHIFT 8 /* Function shift */
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#define PCICFG_OFF_SHIFT 0 /* Register shift */
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#define PCICFG_BUS_MASK 0xff /* Bus mask */
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#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
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#define PCICFG_FUN_MASK 7 /* Function mask */
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#define PCICFG_OFF_MASK 0xff /* Bus mask */
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#define PCI_CONFIG_ADDR(b, s, f, o) \
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((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
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| (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
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| (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
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| (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
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#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
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#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
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#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
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#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
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/* PCIE Config space accessing MACROS */
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#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
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#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
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#define PCIECFG_FUN_SHIFT 16 /* Function shift */
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#define PCIECFG_OFF_SHIFT 0 /* Register shift */
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#define PCIECFG_BUS_MASK 0xff /* Bus mask */
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#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
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#define PCIECFG_FUN_MASK 7 /* Function mask */
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#define PCIECFG_OFF_MASK 0xfff /* Register mask */
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#define PCIE_CONFIG_ADDR(b, s, f, o) \
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((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
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| (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
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| (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
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| (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
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#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
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#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
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#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
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#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
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/* The actual config space */
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#define PCI_BAR_MAX 6
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#define PCI_ROM_BAR 8
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#define PCR_RSVDA_MAX 2
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/* Bits in PCI bars' flags */
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#define PCIBAR_FLAGS 0xf
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#define PCIBAR_IO 0x1
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#define PCIBAR_MEM1M 0x2
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#define PCIBAR_MEM64 0x4
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#define PCIBAR_PREFETCH 0x8
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#define PCIBAR_MEM32_MASK 0xFFFFFF80
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typedef struct _pci_config_regs {
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uint16 vendor;
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uint16 device;
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uint16 command;
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uint16 status;
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uint8 rev_id;
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uint8 prog_if;
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uint8 sub_class;
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uint8 base_class;
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uint8 cache_line_size;
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uint8 latency_timer;
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uint8 header_type;
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uint8 bist;
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uint32 base[PCI_BAR_MAX];
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uint32 cardbus_cis;
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uint16 subsys_vendor;
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uint16 subsys_id;
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uint32 baserom;
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uint32 rsvd_a[PCR_RSVDA_MAX];
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uint8 int_line;
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uint8 int_pin;
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uint8 min_gnt;
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uint8 max_lat;
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uint8 dev_dep[192];
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} pci_config_regs;
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#define SZPCR (sizeof (pci_config_regs))
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#define MINSZPCR 64 /* offsetof (dev_dep[0] */
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/* pci config status reg has a bit to indicate that capability ptr is present */
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#define PCI_CAPPTR_PRESENT 0x0010
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/* A structure for the config registers is nice, but in most
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* systems the config space is not memory mapped, so we need
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* field offsetts. :-(
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*/
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#define PCI_CFG_VID 0
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#define PCI_CFG_DID 2
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#define PCI_CFG_CMD 4
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#define PCI_CFG_STAT 6
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#define PCI_CFG_REV 8
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#define PCI_CFG_PROGIF 9
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#define PCI_CFG_SUBCL 0xa
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#define PCI_CFG_BASECL 0xb
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#define PCI_CFG_CLSZ 0xc
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#define PCI_CFG_LATTIM 0xd
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#define PCI_CFG_HDR 0xe
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#define PCI_CFG_BIST 0xf
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#define PCI_CFG_BAR0 0x10
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#define PCI_CFG_BAR1 0x18
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#define PCI_CFG_BAR2 0x20
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SVID 0x2c
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#define PCI_CFG_SSID 0x2e
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#define PCI_CFG_ROMBAR 0x30
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#define PCI_CFG_CAPPTR 0x34
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#define PCI_CFG_INT 0x3c
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#define PCI_CFG_PIN 0x3d
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#define PCI_CFG_MINGNT 0x3e
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#define PCI_CFG_MAXLAT 0x3f
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#define PCI_CFG_DEVCTRL 0xd8
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#define PCI_CFG_TLCNTRL_5 0x814
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#define PCI_CFG_ERRATTN_MASK_FN0 0x8a0
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#define PCI_CFG_ERRATTN_STATUS_FN0 0x8a4
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#define PCI_CFG_ERRATTN_MASK_FN1 0x8a8
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#define PCI_CFG_ERRATTN_STATUS_FN1 0x8ac
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#define PCI_CFG_ERRATTN_MASK_CMN 0x8b0
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#define PCI_CFG_ERRATTN_STATUS_CMN 0x8b4
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#ifdef EFI
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#undef PCI_CLASS_BRIDGE
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#undef PCI_CLASS_OLD
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#undef PCI_CLASS_DISPLAY
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#undef PCI_CLASS_SERIAL
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#undef PCI_CLASS_SATELLITE
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#endif /* EFI */
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/* Classes and subclasses */
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typedef enum {
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PCI_CLASS_OLD = 0,
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PCI_CLASS_DASDI,
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PCI_CLASS_NET,
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PCI_CLASS_DISPLAY,
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PCI_CLASS_MMEDIA,
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PCI_CLASS_MEMORY,
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PCI_CLASS_BRIDGE,
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PCI_CLASS_COMM,
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PCI_CLASS_BASE,
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PCI_CLASS_INPUT,
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PCI_CLASS_DOCK,
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PCI_CLASS_CPU,
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PCI_CLASS_SERIAL,
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PCI_CLASS_INTELLIGENT = 0xe,
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PCI_CLASS_SATELLITE,
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PCI_CLASS_CRYPT,
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PCI_CLASS_DSP,
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PCI_CLASS_XOR = 0xfe
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} pci_classes;
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typedef enum {
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PCI_DASDI_SCSI,
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PCI_DASDI_IDE,
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PCI_DASDI_FLOPPY,
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PCI_DASDI_IPI,
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PCI_DASDI_RAID,
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PCI_DASDI_OTHER = 0x80
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} pci_dasdi_subclasses;
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typedef enum {
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PCI_NET_ETHER,
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PCI_NET_TOKEN,
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PCI_NET_FDDI,
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PCI_NET_ATM,
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PCI_NET_OTHER = 0x80
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} pci_net_subclasses;
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typedef enum {
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PCI_DISPLAY_VGA,
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PCI_DISPLAY_XGA,
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PCI_DISPLAY_3D,
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PCI_DISPLAY_OTHER = 0x80
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} pci_display_subclasses;
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typedef enum {
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PCI_MMEDIA_VIDEO,
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PCI_MMEDIA_AUDIO,
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PCI_MMEDIA_PHONE,
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PCI_MEDIA_OTHER = 0x80
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} pci_mmedia_subclasses;
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typedef enum {
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PCI_MEMORY_RAM,
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PCI_MEMORY_FLASH,
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PCI_MEMORY_OTHER = 0x80
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} pci_memory_subclasses;
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typedef enum {
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PCI_BRIDGE_HOST,
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PCI_BRIDGE_ISA,
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PCI_BRIDGE_EISA,
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PCI_BRIDGE_MC,
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PCI_BRIDGE_PCI,
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PCI_BRIDGE_PCMCIA,
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PCI_BRIDGE_NUBUS,
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PCI_BRIDGE_CARDBUS,
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PCI_BRIDGE_RACEWAY,
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PCI_BRIDGE_OTHER = 0x80
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} pci_bridge_subclasses;
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typedef enum {
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PCI_COMM_UART,
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PCI_COMM_PARALLEL,
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PCI_COMM_MULTIUART,
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PCI_COMM_MODEM,
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PCI_COMM_OTHER = 0x80
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} pci_comm_subclasses;
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typedef enum {
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PCI_BASE_PIC,
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PCI_BASE_DMA,
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PCI_BASE_TIMER,
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PCI_BASE_RTC,
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PCI_BASE_PCI_HOTPLUG,
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PCI_BASE_OTHER = 0x80
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} pci_base_subclasses;
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typedef enum {
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PCI_INPUT_KBD,
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PCI_INPUT_PEN,
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PCI_INPUT_MOUSE,
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PCI_INPUT_SCANNER,
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PCI_INPUT_GAMEPORT,
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PCI_INPUT_OTHER = 0x80
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} pci_input_subclasses;
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typedef enum {
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PCI_DOCK_GENERIC,
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PCI_DOCK_OTHER = 0x80
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} pci_dock_subclasses;
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typedef enum {
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PCI_CPU_386,
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PCI_CPU_486,
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PCI_CPU_PENTIUM,
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PCI_CPU_ALPHA = 0x10,
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PCI_CPU_POWERPC = 0x20,
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PCI_CPU_MIPS = 0x30,
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PCI_CPU_COPROC = 0x40,
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PCI_CPU_OTHER = 0x80
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} pci_cpu_subclasses;
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typedef enum {
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PCI_SERIAL_IEEE1394,
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PCI_SERIAL_ACCESS,
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PCI_SERIAL_SSA,
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PCI_SERIAL_USB,
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PCI_SERIAL_FIBER,
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PCI_SERIAL_SMBUS,
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PCI_SERIAL_OTHER = 0x80
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} pci_serial_subclasses;
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typedef enum {
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PCI_INTELLIGENT_I2O
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} pci_intelligent_subclasses;
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typedef enum {
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PCI_SATELLITE_TV,
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PCI_SATELLITE_AUDIO,
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PCI_SATELLITE_VOICE,
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PCI_SATELLITE_DATA,
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PCI_SATELLITE_OTHER = 0x80
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} pci_satellite_subclasses;
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typedef enum {
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PCI_CRYPT_NETWORK,
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PCI_CRYPT_ENTERTAINMENT,
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PCI_CRYPT_OTHER = 0x80
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} pci_crypt_subclasses;
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typedef enum {
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PCI_DSP_DPIO,
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PCI_DSP_OTHER = 0x80
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} pci_dsp_subclasses;
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typedef enum {
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PCI_XOR_QDMA,
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PCI_XOR_OTHER = 0x80
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} pci_xor_subclasses;
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/* Overlay for a PCI-to-PCI bridge */
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#define PPB_RSVDA_MAX 2
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#define PPB_RSVDD_MAX 8
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typedef struct _ppb_config_regs {
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uint16 vendor;
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uint16 device;
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uint16 command;
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uint16 status;
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uint8 rev_id;
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uint8 prog_if;
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uint8 sub_class;
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uint8 base_class;
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uint8 cache_line_size;
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uint8 latency_timer;
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uint8 header_type;
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uint8 bist;
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uint32 rsvd_a[PPB_RSVDA_MAX];
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uint8 prim_bus;
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uint8 sec_bus;
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uint8 sub_bus;
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uint8 sec_lat;
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uint8 io_base;
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uint8 io_lim;
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uint16 sec_status;
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uint16 mem_base;
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uint16 mem_lim;
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uint16 pf_mem_base;
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uint16 pf_mem_lim;
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uint32 pf_mem_base_hi;
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uint32 pf_mem_lim_hi;
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uint16 io_base_hi;
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uint16 io_lim_hi;
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uint16 subsys_vendor;
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uint16 subsys_id;
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uint32 rsvd_b;
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uint8 rsvd_c;
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uint8 int_pin;
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uint16 bridge_ctrl;
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uint8 chip_ctrl;
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uint8 diag_ctrl;
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uint16 arb_ctrl;
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uint32 rsvd_d[PPB_RSVDD_MAX];
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uint8 dev_dep[192];
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} ppb_config_regs;
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/* Everything below is BRCM HND proprietary */
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/* Brcm PCI configuration registers */
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#define cap_list rsvd_a[0]
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#define bar0_window dev_dep[0x80 - 0x40]
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#define bar1_window dev_dep[0x84 - 0x40]
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#define sprom_control dev_dep[0x88 - 0x40]
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/* PCI CAPABILITY DEFINES */
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#define PCI_CAP_POWERMGMTCAP_ID 0x01
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#define PCI_CAP_MSICAP_ID 0x05
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#define PCI_CAP_VENDSPEC_ID 0x09
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#define PCI_CAP_PCIECAP_ID 0x10
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#define PCI_CAP_MSIXCAP_ID 0x11
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/* Data structure to define the Message Signalled Interrupt facility
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* Valid for PCI and PCIE configurations
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*/
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typedef struct _pciconfig_cap_msi {
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uint8 capID;
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uint8 nextptr;
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uint16 msgctrl;
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uint32 msgaddr;
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} pciconfig_cap_msi;
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#define MSI_ENABLE 0x1 /* bit 0 of msgctrl */
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/* Data structure to define the Power managment facility
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* Valid for PCI and PCIE configurations
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*/
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typedef struct _pciconfig_cap_pwrmgmt {
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uint8 capID;
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uint8 nextptr;
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uint16 pme_cap;
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uint16 pme_sts_ctrl;
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uint8 pme_bridge_ext;
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uint8 data;
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} pciconfig_cap_pwrmgmt;
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#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
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#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
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#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
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#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
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/* Data structure to define the PCIE capability */
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typedef struct _pciconfig_cap_pcie {
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uint8 capID;
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uint8 nextptr;
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uint16 pcie_cap;
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uint32 dev_cap;
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uint16 dev_ctrl;
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uint16 dev_status;
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uint32 link_cap;
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uint16 link_ctrl;
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uint16 link_status;
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uint32 slot_cap;
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uint16 slot_ctrl;
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uint16 slot_status;
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uint16 root_ctrl;
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uint16 root_cap;
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uint32 root_status;
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} pciconfig_cap_pcie;
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/* PCIE Enhanced CAPABILITY DEFINES */
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#define PCIE_EXTCFG_OFFSET 0x100
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#define PCIE_ADVERRREP_CAPID 0x0001
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#define PCIE_VC_CAPID 0x0002
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#define PCIE_DEVSNUM_CAPID 0x0003
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#define PCIE_PWRBUDGET_CAPID 0x0004
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/* PCIE Extended configuration */
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#define PCIE_ADV_CORR_ERR_MASK 0x114
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#define PCIE_ADV_CORR_ERR_MASK_OFFSET 0x14
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#define CORR_ERR_RE (1 << 0) /* Receiver */
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#define CORR_ERR_BT (1 << 6) /* Bad TLP */
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#define CORR_ERR_BD (1 << 7) /* Bad DLLP */
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#define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */
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#define CORR_ERR_RT (1 << 12) /* Reply timer timeout */
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#define CORR_ERR_AE (1 << 13) /* Adviosry Non-Fital Error Mask */
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#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
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CORR_ERR_RR | CORR_ERR_RT)
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/* PCIE Root Control Register bits (Host mode only) */
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#define PCIE_RC_CORR_SERR_EN 0x0001
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#define PCIE_RC_NONFATAL_SERR_EN 0x0002
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#define PCIE_RC_FATAL_SERR_EN 0x0004
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#define PCIE_RC_PME_INT_EN 0x0008
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#define PCIE_RC_CRS_EN 0x0010
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/* PCIE Root Capability Register bits (Host mode only) */
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#define PCIE_RC_CRS_VISIBILITY 0x0001
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/* PCIe PMCSR Register bits */
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#define PCIE_PMCSR_PMESTAT 0x8000
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/* Header to define the PCIE specific capabilities in the extended config space */
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typedef struct _pcie_enhanced_caphdr {
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uint16 capID;
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uint16 cap_ver : 4;
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uint16 next_ptr : 12;
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} pcie_enhanced_caphdr;
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#define PCIE_CFG_PMCSR 0x4C
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#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
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#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
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#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
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#define PCIE_CFG_SUBSYSTEM_CONTROL 0x88 /* used as subsystem control in PCIE devices */
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#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
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#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
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#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
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#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
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#define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
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#define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
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#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
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#define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
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#define PCIE_CFG_DEVICE_CAPABILITY 0xb0 /* used as device capability in PCIE devices */
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#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
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#define PCIE_CFG_DEVICE_CONTROL 0xb4 /* 0xb4 is used as device control in PCIE devices */
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#define PCIE_DC_AER_CORR_EN (1u << 0u)
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#define PCIE_DC_AER_NON_FATAL_EN (1u << 1u)
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#define PCIE_DC_AER_FATAL_EN (1u << 2u)
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#define PCIE_DC_AER_UNSUP_EN (1u << 3u)
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#define PCI_BAR0_WIN2_OFFSET 0x1000u
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#define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u
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#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
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#define PCI_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */
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/* Private Registers */
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#define PCI_STAT_CTRL 0xa80
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#define PCI_L0_EVENTCNT 0xa84
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#define PCI_L0_STATETMR 0xa88
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#define PCI_L1_EVENTCNT 0xa8c
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#define PCI_L1_STATETMR 0xa90
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#define PCI_L1_1_EVENTCNT 0xa94
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#define PCI_L1_1_STATETMR 0xa98
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#define PCI_L1_2_EVENTCNT 0xa9c
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#define PCI_L1_2_STATETMR 0xaa0
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#define PCI_L2_EVENTCNT 0xaa4
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#define PCI_L2_STATETMR 0xaa8
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#define PCI_LINK_STATUS 0x4dc
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#define PCI_LINK_SPEED_MASK (15u << 0u)
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#define PCI_LINK_SPEED_SHIFT (0)
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#define PCIE_LNK_SPEED_GEN1 0x1
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#define PCIE_LNK_SPEED_GEN2 0x2
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#define PCIE_LNK_SPEED_GEN3 0x3
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#define PCI_PL_SPARE 0x1808 /* Config to Increase external clkreq deasserted minimum time */
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#define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u)
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#define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31)
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#define PCI_ADV_ERR_CAP 0x100
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#define PCI_UC_ERR_STATUS 0x104
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#define PCI_UNCORR_ERR_MASK 0x108
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#define PCI_UCORR_ERR_SEVR 0x10c
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#define PCI_CORR_ERR_STATUS 0x110
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#define PCI_CORR_ERR_MASK 0x114
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#define PCI_ERR_CAP_CTRL 0x118
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#define PCI_TLP_HDR_LOG1 0x11c
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#define PCI_TLP_HDR_LOG2 0x120
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#define PCI_TLP_HDR_LOG3 0x124
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#define PCI_TLP_HDR_LOG4 0x128
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#define PCI_TL_CTRL_5 0x814
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#define PCI_TL_HDR_FC_ST 0x980
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#define PCI_TL_TGT_CRDT_ST 0x990
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#define PCI_TL_SMLOGIC_ST 0x998
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#define PCI_DL_ATTN_VEC 0x1040
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#define PCI_DL_STATUS 0x1048
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#define PCI_PHY_CTL_0 0x1800
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#define PCI_SLOW_PMCLK_EXT_RLOCK (1 << 7)
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#define PCI_REG_TX_DEEMPH_3_5_DB (1 << 21)
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#define PCI_LINK_STATE_DEBUG 0x1c24
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#define PCI_RECOVERY_HIST 0x1ce4
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#define PCI_PHY_LTSSM_HIST_0 0x1cec
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#define PCI_PHY_LTSSM_HIST_1 0x1cf0
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#define PCI_PHY_LTSSM_HIST_2 0x1cf4
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#define PCI_PHY_LTSSM_HIST_3 0x1cf8
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#define PCI_PHY_DBG_CLKREG_0 0x1e10
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#define PCI_PHY_DBG_CLKREG_1 0x1e14
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#define PCI_PHY_DBG_CLKREG_2 0x1e18
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#define PCI_PHY_DBG_CLKREG_3 0x1e1c
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#define PCI_TL_CTRL_0 0x800u
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#define PCI_BEACON_DIS (1u << 20u) /* Disable Beacon Generation */
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/* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */
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#define PCIE_BAR1COHERENTACCEN_BIT 8
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#define PCIE_BAR2COHERENTACCEN_BIT 9
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#define PCIE_SSRESET_STATUS_BIT 13
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#define PCIE_SSRESET_DISABLE_BIT 14
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#define PCIE_SSRESET_DIS_ENUM_RST_BIT 15
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#define PCIE_BARCOHERENTACCEN_MASK 0x300
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/* Bit settings for PCI_UC_ERR_STATUS register */
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#define PCI_UC_ERR_URES (1 << 20) /* Unsupported Request Error Status */
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#define PCI_UC_ERR_ECRCS (1 << 19) /* ECRC Error Status */
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#define PCI_UC_ERR_MTLPS (1 << 18) /* Malformed TLP Status */
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#define PCI_UC_ERR_ROS (1 << 17) /* Receiver Overflow Status */
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#define PCI_UC_ERR_UCS (1 << 16) /* Unexpected Completion Status */
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#define PCI_UC_ERR_CAS (1 << 15) /* Completer Abort Status */
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#define PCI_UC_ERR_CTS (1 << 14) /* Completer Timeout Status */
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#define PCI_UC_ERR_FCPES (1 << 13) /* Flow Control Protocol Error Status */
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#define PCI_UC_ERR_PTLPS (1 << 12) /* Poisoned TLP Status */
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#define PCI_UC_ERR_DLPES (1 << 4) /* Data Link Protocol Error Status */
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#define PCI_DL_STATUS_PHY_LINKUP (1 << 13) /* Status of LINK */
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#define PCI_PMCR_REFUP 0x1814 /* Trefup time */
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#define PCI_PMCR_TREFUP_LO_MASK 0x3f
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#define PCI_PMCR_TREFUP_LO_SHIFT 24
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#define PCI_PMCR_TREFUP_LO_BITS 6
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#define PCI_PMCR_TREFUP_HI_MASK 0xf
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#define PCI_PMCR_TREFUP_HI_SHIFT 5
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#define PCI_PMCR_TREFUP_HI_BITS 4
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#define PCI_PMCR_TREFUP_MAX 0x400
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#define PCI_PMCR_TREFUP_MAX_SCALE 0x2000
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#define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */
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#define PCI_PMCR_TREFUP_EXT_SHIFT 22
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#define PCI_PMCR_TREFUP_EXT_SCALE 3
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#define PCI_PMCR_TREFUP_EXT_ON 1
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#define PCI_PMCR_TREFUP_EXT_OFF 0
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#define PCI_TPOWER_SCALE_MASK 0x3
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#define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */
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#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
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#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
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#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
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#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
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* 8KB window, so their address is the "regular"
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* address plus 4K
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*/
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/*
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* PCIE GEN2 changed some of the above locations for
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* Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase
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* BAR0 maps 32K of register space
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*/
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#define PCIE2_BAR0_WIN2 0x70 /* config register to map 2nd 4KB of BAR0 */
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#define PCIE2_BAR0_CORE2_WIN 0x74 /* config register to map 5th 4KB of BAR0 */
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#define PCIE2_BAR0_CORE2_WIN2 0x78 /* config register to map 6th 4KB of BAR0 */
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/* PCIE GEN2 BAR0 window size */
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#define PCIE2_BAR0_WINSZ 0x8000
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#define PCI_BAR0_WIN2_OFFSET 0x1000u
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#define PCI_CORE_ENUM_OFFSET 0x2000u
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#define PCI_CC_CORE_ENUM_OFFSET 0x3000u
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#define PCI_SEC_BAR0_WIN_OFFSET 0x4000u
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#define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u
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#define PCI_CORE_ENUM2_OFFSET 0x6000u
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#define PCI_CC_CORE_ENUM2_OFFSET 0x7000u
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#define PCI_TER_BAR0_WIN_OFFSET 0x9000u
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#define PCI_TER_BAR0_WRAP_OFFSET 0xa000u
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#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
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/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
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#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
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#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
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#define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */
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/* On AI chips we have a second window to map DMP regs are mapped: */
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#define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */
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/* PCI_INT_STATUS */
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#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
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/* PCI_INT_MASK */
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#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
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#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
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#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
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#define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */
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#define PCI_CTO_INT_MASK (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */
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/* PCI_SPROM_CONTROL */
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#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
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#define SPROM_LOCKED 0x08 /* SPROM Locked */
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#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
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#define SPROM_WRITEEN 0x10 /* SPROM write enable */
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#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
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#define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
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#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
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#define SPROM_BAR1_COHERENT_ACC_EN 0x100 /* PCIe acceeses through BAR1 are coherent */
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#define SPROM_BAR2_COHERENT_ACC_EN 0x200 /* PCIe acceeses through BAR2 are coherent */
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#define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */
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/* Bits in PCI command and status regs */
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#define PCI_CMD_IO 0x00000001 /* I/O enable */
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#define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
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#define PCI_CMD_MASTER 0x00000004 /* Master enable */
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#define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
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#define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
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#define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
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#define PCI_STAT_TA 0x08000000 /* target abort status */
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/* Header types */
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#define PCI_HEADER_MULTI 0x80
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#define PCI_HEADER_MASK 0x7f
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typedef enum {
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PCI_HEADER_NORMAL,
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PCI_HEADER_BRIDGE,
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PCI_HEADER_CARDBUS
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} pci_header_types;
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#define PCI_CONFIG_SPACE_SIZE 256
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#define DWORD_ALIGN(x) ((x) & ~(0x03))
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#define BYTE_POS(x) ((x) & 0x3)
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#define WORD_POS(x) ((x) & 0x1)
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#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
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#define WORD_SHIFT(x) (16 * WORD_POS(x))
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#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
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#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
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#define read_pci_cfg_byte(a) \
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BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a)
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#define read_pci_cfg_word(a) \
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WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a)
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#define write_pci_cfg_byte(a, val) do { \
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uint32 tmpval; \
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tmpval = OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4); \
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tmpval &= ~(0xFF << BYTE_SHIFT(a)); \
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tmpval |= ((uint8)(val)) << BYTE_SHIFT(a); \
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OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
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} while (0)
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#define write_pci_cfg_word(a, val) do { \
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uint32 tmpval; \
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tmpval = OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4); \
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tmpval &= ~(0xFFFF << WORD_SHIFT(a))); \
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tmpval |= ((uint16)(val)) << WORD_SHIFT(a); \
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OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
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} while (0)
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#endif /* _h_pcicfg_ */
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