/*
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* Generic Broadcom Home Networking Division (HND) DMA engine SW interface
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* This supports the following chips: BCM42xx, 44xx, 47xx .
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _hnddma_h_
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#define _hnddma_h_
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#include <typedefs.h>
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#include <osl_decl.h>
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#include <siutils.h>
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#include <sbhnddma.h>
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#include <hnd_pktq.h>
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#include <hnd_pktpool.h>
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#ifndef _hnddma_pub_
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#define _hnddma_pub_
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typedef const struct hnddma_pub hnddma_t;
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#endif /* _hnddma_pub_ */
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/* range param for dma_getnexttxp() and dma_txreclaim */
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typedef enum txd_range {
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HNDDMA_RANGE_ALL = 1,
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HNDDMA_RANGE_TRANSMITTED,
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HNDDMA_RANGE_TRANSFERED
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} txd_range_t;
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/* dma parameters id */
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enum dma_param_id {
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HNDDMA_PID_TX_MULTI_OUTSTD_RD = 0,
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HNDDMA_PID_TX_PREFETCH_CTL,
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HNDDMA_PID_TX_PREFETCH_THRESH,
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HNDDMA_PID_TX_BURSTLEN,
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HNDDMA_PID_TX_CHAN_SWITCH,
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HNDDMA_PID_RX_PREFETCH_CTL = 0x100,
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HNDDMA_PID_RX_PREFETCH_THRESH,
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HNDDMA_PID_RX_BURSTLEN,
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HNDDMA_PID_BURSTLEN_CAP,
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HNDDMA_PID_BURSTLEN_WAR,
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HNDDMA_SEP_RX_HDR, /**< SPLITRX related */
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HNDDMA_SPLIT_FIFO,
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HNDDMA_PID_D11RX_WAR,
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HNDDMA_PID_RX_WAIT_CMPL,
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HNDDMA_NRXPOST,
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HNDDMA_NRXBUFSZ,
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HNDDMA_PID_RXCTL_MOW,
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HNDDMA_M2M_RXBUF_RAW /* rx buffers are raw buffers, not lbufs/lfrags */
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};
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#define SPLIT_FIFO_0 1
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#define SPLIT_FIFO_1 2
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typedef void (*setup_context_t)(void *ctx, void *p, uint8 **desc0, uint16 *len0,
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uint8 **desc1, uint16 *len1);
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/**
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* Exported data structure (read-only)
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*/
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/* export structure */
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struct hnddma_pub {
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uint dmastflags; /* dma status flags */
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uint dmactrlflags; /**< dma control flags */
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/* rx error counters */
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uint rxgiants; /**< rx giant frames */
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uint rxnobuf; /**< rx out of dma descriptors */
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/* tx error counters */
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uint txnobuf; /**< tx out of dma descriptors */
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uint txnodesc; /**< tx out of dma descriptors running count */
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};
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/* DMA status flags */
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#define BCM_DMA_STF_RX (1u << 0u) /* the channel is RX DMA */
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typedef struct dma_common dma_common_t;
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typedef struct dma_dd_pool dma_dd_pool_t;
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/* Flags for dma_attach_ext function */
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#define BCM_DMA_IND_INTF_FLAG 0x00000001 /* set for using INDIRECT DMA INTERFACE */
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#define BCM_DMA_DESC_ONLY_FLAG 0x00000002 /* For DMA that posts descriptors only and
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* no packets
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*/
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#define BCM_DMA_CHAN_SWITCH_EN 0x00000008 /* for d11 corerev 64+ to help arbitrate
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* btw dma channels.
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*/
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#define BCM_DMA_ROEXT_SUPPORT 0x00000010 /* for d11 corerev 128+ to support receive
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* frame offset >=128B and <= 255B
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*/
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#define BCM_DMA_RX_ALIGN_8BYTE 0x00000020 /* RXDMA address 8-byte aligned */
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#define BCM_DMA_DESC_SHARED_POOL 0x00000100 /* For TX DMA that uses shared desc pool */
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#define BCM_DMA_RXP_LIST 0x00000200 /* linked list for RXP instead of array */
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typedef int (*rxpkt_error_check_t)(const void* ctx, void* pkt);
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extern dma_common_t * dma_common_attach(osl_t *osh, volatile uint32 *indqsel,
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volatile uint32 *suspreq, volatile uint32 *flushreq, rxpkt_error_check_t cb, void *ctx);
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extern void dma_common_detach(dma_common_t *dmacommon);
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extern void dma_common_set_ddpool_ctx(dma_common_t *dmacommon, void *desc_pool);
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extern void * dma_common_get_ddpool_ctx(dma_common_t *dmacommon, void **va);
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extern bool dma_check_last_desc(hnddma_t *dmah);
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extern void dma_txfrwd(hnddma_t *dmah);
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#ifdef BCM_DMA_INDIRECT
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/* Use indirect registers for non-ctmode */
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#define DMA_INDQSEL_IA (1 << 31)
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extern void dma_set_indqsel(hnddma_t *di, bool force);
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extern bool dma_is_indirect(hnddma_t *dmah);
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#else
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#define dma_set_indqsel(a, b)
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#define dma_is_indirect(a) FALSE
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#endif /* #ifdef BCM_DMA_INDIRECT */
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extern hnddma_t * dma_attach_ext(dma_common_t *dmac, osl_t *osh, const char *name, si_t *sih,
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volatile void *dmaregstx, volatile void *dmaregsrx, uint32 flags, uint8 qnum,
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uint ntxd, uint nrxd, uint rxbufsize, int rxextheadroom, uint nrxpost, uint rxoffset,
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uint *msg_level, uint coreunit);
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extern hnddma_t * dma_attach(osl_t *osh, const char *name, si_t *sih,
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volatile void *dmaregstx, volatile void *dmaregsrx,
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uint ntxd, uint nrxd, uint rxbufsize, int rxextheadroom, uint nrxpost,
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uint rxoffset, uint *msg_level);
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void dma_rx_desc_init(hnddma_t *dmah, uint rxfifo);
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void dma_detach(hnddma_t *dmah);
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bool dma_txreset(hnddma_t *dmah);
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bool dma_rxreset(hnddma_t *dmah);
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bool dma_rxidle(hnddma_t *dmah);
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void dma_txinit(hnddma_t *dmah);
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bool dma_txenabled(hnddma_t *dmah);
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void dma_rxinit(hnddma_t *dmah);
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void dma_txsuspend(hnddma_t *dmah);
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void dma_txresume(hnddma_t *dmah);
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bool dma_txsuspended(hnddma_t *dmah);
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bool dma_txsuspendedidle(hnddma_t *dmah);
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void dma_txflush(hnddma_t *dmah);
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void dma_txflush_clear(hnddma_t *dmah);
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int dma_txfast_ext(hnddma_t *dmah, void *p0, bool commit, uint16 *pre_txout, uint16 *numd);
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int dma_txfast_alfrag(hnddma_t *dmah, hnddma_t *aqm_dmah, void *p, bool commit, dma64dd_t *aqmdesc,
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uint d11_txh_len, bool ptxd_hw_enab);
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#define dma_txfast(dmah, p0, commit) \
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dma_txfast_ext((dmah), (p0), (commit), NULL, NULL)
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void dma_txcommit(hnddma_t *dmah);
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int dma_txunframed(hnddma_t *dmah, void *buf, uint len, bool commit);
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void *dma_getpos(hnddma_t *dmah, bool direction);
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void dma_fifoloopbackenable(hnddma_t *dmah);
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void dma_fifoloopbackdisable(hnddma_t *dmah);
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bool dma_txstopped(hnddma_t *dmah);
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bool dma_rxstopped(hnddma_t *dmah);
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void dma_rxenable(hnddma_t *dmah);
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bool dma_rxenabled(hnddma_t *dmah);
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void *dma_rx(hnddma_t *dmah);
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#ifdef APP_RX
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void dma_getnextrxp_app(hnddma_t *dmah, bool forceall, uint *pktcnt,
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void **head, void **tail);
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void dma_rxfill_haddr_getparams(hnddma_t *dmah, uint *nrxd, uint16 *rxout,
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dma64dd_t **ddring, uint *rxextrahdrroom, uint32 **rxpktid);
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void dma_rxfill_haddr_setparams(hnddma_t *dmah, uint16 rxout);
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#endif /* APP_RX */
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uint dma_rx_get_rxoffset(hnddma_t *dmah);
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bool dma_rxfill(hnddma_t *dmah);
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bool dma_rxfill_required(hnddma_t *dmah);
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void dma_txreclaim(hnddma_t *dmah, txd_range_t range);
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void dma_rxreclaim(hnddma_t *dmah);
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#define _DMA_GETUINTVARPTR_
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uint *dma_getuintvarptr(hnddma_t *dmah, const char *name);
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uint8 dma_getuint8var(hnddma_t *dmah, const char *name);
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uint16 dma_getuint16var(hnddma_t *dmah, const char *name);
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uint32 dma_getuint32var(hnddma_t *dmah, const char *name);
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void * dma_getnexttxp(hnddma_t *dmah, txd_range_t range);
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void * dma_getnextp(hnddma_t *dmah);
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void * dma_getnextrxp(hnddma_t *dmah, bool forceall);
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void * dma_peeknexttxp(hnddma_t *dmah, txd_range_t range);
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int dma_peekntxp(hnddma_t *dmah, int *len, void *txps[], txd_range_t range);
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void * dma_peeknextrxp(hnddma_t *dmah);
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void dma_rxparam_get(hnddma_t *dmah, uint16 *rxoffset, uint16 *rxbufsize);
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bool dma_is_rxfill_suspend(hnddma_t *dmah);
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void dma_txblock(hnddma_t *dmah);
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void dma_txunblock(hnddma_t *dmah);
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uint dma_txactive(hnddma_t *dmah);
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uint dma_rxactive(hnddma_t *dmah);
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void dma_txrotate(hnddma_t *dmah);
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void dma_counterreset(hnddma_t *dmah);
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uint dma_ctrlflags(hnddma_t *dmah, uint mask, uint flags);
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uint dma_txpending(hnddma_t *dmah);
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uint dma_txcommitted(hnddma_t *dmah);
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int dma_pktpool_set(hnddma_t *dmah, pktpool_t *pool);
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int dma_rxdatapool_set(hnddma_t *dmah, pktpool_t *pktpool);
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pktpool_t *dma_rxdatapool_get(hnddma_t *dmah);
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void dma_dump_txdmaregs(hnddma_t *dmah, uint32 **buf);
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void dma_dump_rxdmaregs(hnddma_t *dmah, uint32 **buf);
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#if defined(BCMDBG) || defined(BCMDBG_DUMP) || defined(BCMDBG_DMA)
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void dma_dump(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
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void dma_dumptx(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
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void dma_dumprx(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
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#endif
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bool dma_rxtxerror(hnddma_t *dmah, bool istx);
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void dma_burstlen_set(hnddma_t *dmah, uint8 rxburstlen, uint8 txburstlen);
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uint dma_avoidance_cnt(hnddma_t *dmah);
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void dma_param_set(hnddma_t *dmah, uint16 paramid, uint16 paramval);
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void dma_param_get(hnddma_t *dmah, uint16 paramid, uint *paramval);
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void dma_context(hnddma_t *dmah, setup_context_t fn, void *ctx);
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bool dma_glom_enable(hnddma_t *dmah, uint32 val);
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uint dma_activerxbuf(hnddma_t *dmah);
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bool dma_rxidlestatus(hnddma_t *dmah);
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uint dma_get_rxpost(hnddma_t *dmah);
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/* return addresswidth allowed
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* This needs to be done after SB attach but before dma attach.
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* SB attach provides ability to probe backplane and dma core capabilities
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* This info is needed by DMA_ALLOC_CONSISTENT in dma attach
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*/
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extern uint dma_addrwidth(si_t *sih, void *dmaregs);
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/* count the number of tx packets that are queued to the dma ring */
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extern uint dma_txp(hnddma_t *di);
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extern void dma_txrewind(hnddma_t *di);
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/* pio helpers */
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extern int dma_msgbuf_txfast(hnddma_t *di, dma64addr_t p0, bool com, uint32 ln, bool fst, bool lst);
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extern int dma_ptrbuf_txfast(hnddma_t *dmah, dma64addr_t p0, void *p, bool commit,
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uint32 len, bool first, bool last);
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extern int dma_rxfast(hnddma_t *di, dma64addr_t p, uint32 len);
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extern int dma_rxfill_suspend(hnddma_t *dmah, bool suspended);
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extern void dma_link_handle(hnddma_t *dmah1, hnddma_t *dmah2);
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extern void dma_unlink_handle(hnddma_t *dmah1, hnddma_t *dmah2);
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extern int dma_rxfill_unframed(hnddma_t *di, void *buf, uint len, bool commit);
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extern uint16 dma_get_next_txd_idx(hnddma_t *di, bool txout);
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extern uint16 dma_get_txd_count(hnddma_t *dmah, uint16 start, bool txout);
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extern uintptr dma_get_txd_addr(hnddma_t *di, uint16 idx);
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/* returns the memory address (hi and low) of the buffer associated with the dma descriptor
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* having index idx.
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*/
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extern void dma_get_txd_memaddr(hnddma_t *dmah, uint32 *addrlo, uint32 *addrhi, uint idx);
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extern int dma_txdesc(hnddma_t *dmah, dma64dd_t *dd, bool commit);
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extern int dma_nexttxdd(hnddma_t *dmah, txd_range_t range, uint32 *flags1, uint32 *flags2,
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bool advance);
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extern void dma_update_rxfill(hnddma_t *dmah);
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extern void dma_rxchan_reset(hnddma_t *di);
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extern void dma_txchan_reset(hnddma_t *di);
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extern void dma_chan_reset(hnddma_t *dmah);
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extern pktpool_t* dma_pktpool_get(hnddma_t *dmah);
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extern void dma_clearrxp(hnddma_t *dmah);
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extern void dma_cleartxp(hnddma_t *dmah);
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#define dma_getnexttxdd(dmah, range, flags1, flags2) \
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dma_nexttxdd((dmah), (range), (flags1), (flags2), TRUE)
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#define dma_peeknexttxdd(dmah, range, flags1, flags2) \
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dma_nexttxdd((dmah), (range), (flags1), (flags2), FALSE)
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#define NUM_VEC_PCIE 4
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#define XFER_FROM_LBUF 0x1
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#define XFER_TO_LBUF 0x2
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#define XFER_INJ_ERR 0x4
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typedef struct m2m_vec_s {
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dma64addr_t addr;
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uint32 len;
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} m2m_vec_t;
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typedef struct m2m_desc_s {
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uint8 num_rx_vec;
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uint8 num_tx_vec;
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uint8 flags;
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bool commit;
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m2m_vec_t vec[];
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} m2m_desc_t;
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#define INIT_M2M_DESC(desc) \
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{\
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desc->num_rx_vec = 0; \
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desc->num_tx_vec = 0; \
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desc->flags = 0; \
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desc->commit = TRUE; \
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}
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#define SETUP_RX_DESC(desc, rxaddr, rxlen) \
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{\
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ASSERT(desc->num_tx_vec == 0); \
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desc->vec[desc->num_rx_vec].addr = rxaddr; \
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desc->vec[desc->num_rx_vec].len = rxlen; \
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desc->num_rx_vec++; \
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}
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#define SETUP_TX_DESC(desc, txaddr, txlen) \
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{\
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desc->vec[desc->num_tx_vec + desc->num_rx_vec].addr = txaddr; \
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desc->vec[desc->num_tx_vec + desc->num_rx_vec].len = txlen; \
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desc->num_tx_vec++; \
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}
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#define SETUP_XFER_FLAGS(desc, flag) \
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{\
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desc->flags |= flag; \
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}
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#define DD_IS_SHARED_POOL(di) ((di)->dmactrlflags & DMA_CTRL_SHARED_POOL)
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extern int dma_m2m_submit(hnddma_t *dmah, m2m_desc_t *desc, bool implicit);
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extern void dma_chan_enable(hnddma_t *dmah, bool enable);
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extern bool dma_rxfill_p(hnddma_t *dmah, void *p);
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extern void dma_aqm_di_link(hnddma_t *dmah_aqm, hnddma_t *dmah_hw);
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extern void dma_dump_aqminfo(hnddma_t * dmah, struct bcmstrbuf *b, uint16 fifonum);
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/* To dump ntxd and nrxd from the DMA ring */
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void dma_dump_info(hnddma_t *dmah, uint16 fifonum, struct bcmstrbuf *b);
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#endif /* _hnddma_h_ */
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