/*
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* Extended Trap data component interface file.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _ETD_H_
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#define _ETD_H_
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#if defined(ETD) && !defined(WLETD)
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#include <hnd_trap.h>
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#endif
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#include <bcmutils.h>
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/* Tags for structures being used by etd info iovar.
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* Related structures are defined in wlioctl.h.
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*/
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#define ETD_TAG_JOIN_CLASSIFICATION_INFO 10 /* general information about join request */
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#define ETD_TAG_JOIN_TARGET_CLASSIFICATION_INFO 11 /* per target (AP) join information */
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#define ETD_TAG_ASSOC_STATE 12 /* current state of the Device association state machine */
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#define ETD_TAG_CHANNEL 13 /* current channel on which the association was performed */
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#define ETD_TAG_TOTAL_NUM_OF_JOIN_ATTEMPTS 14 /* number of join attempts (bss_retries) */
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#define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1 3
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#define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2 6
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#ifndef _LANGUAGE_ASSEMBLY
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#define HND_EXTENDED_TRAP_VERSION 1
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#define HND_EXTENDED_TRAP_BUFLEN 512
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typedef struct hnd_ext_trap_hdr {
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uint8 version; /* Extended trap version info */
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uint8 reserved; /* currently unused */
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uint16 len; /* Length of data excluding this header */
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uint8 data[]; /* TLV data */
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} hnd_ext_trap_hdr_t;
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typedef enum {
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TAG_TRAP_NONE = 0u, /* None trap type */
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TAG_TRAP_SIGNATURE = 1u, /* Processor register dumps */
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TAG_TRAP_STACK = 2u, /* Processor stack dump (possible code locations) */
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TAG_TRAP_MEMORY = 3u, /* Memory subsystem dump */
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TAG_TRAP_DEEPSLEEP = 4u, /* Deep sleep health check failures */
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TAG_TRAP_PSM_WD = 5u, /* PSM watchdog information */
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TAG_TRAP_PHY = 6u, /* Phy related issues */
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TAG_TRAP_BUS = 7u, /* Bus level issues */
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TAG_TRAP_MAC_SUSP = 8u, /* Mac level suspend issues */
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TAG_TRAP_BACKPLANE = 9u, /* Backplane related errors */
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/* Values 10 through 14 are in use by etd_data info iovar */
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TAG_TRAP_PCIE_Q = 15u, /* PCIE Queue state during memory trap */
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TAG_TRAP_WLC_STATE = 16u, /* WLAN state during memory trap */
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TAG_TRAP_MAC_WAKE = 17u, /* Mac level wake issues */
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TAG_TRAP_PHYTXERR_THRESH = 18u, /* Phy Tx Err */
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TAG_TRAP_HC_DATA = 19u, /* Data collected by HC module */
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TAG_TRAP_LOG_DATA = 20u,
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TAG_TRAP_CODE = 21u, /* The trap type */
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TAG_TRAP_HMAP = 22u, /* HMAP violation Address and Info */
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TAG_TRAP_PCIE_ERR_ATTN = 23u, /* PCIE error attn log */
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TAG_TRAP_AXI_ERROR = 24u, /* AXI Error */
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TAG_TRAP_AXI_HOST_INFO = 25u, /* AXI Host log */
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TAG_TRAP_AXI_SR_ERROR = 26u, /* AXI SR error log */
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TAG_TRAP_MEM_BIT_FLIP = 27u, /* Memory 1-Bit Flip error */
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TAG_TRAP_LAST /* This must be the last entry */
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} hnd_ext_tag_trap_t;
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typedef struct hnd_ext_trap_bp_err
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{
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uint32 error;
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uint32 coreid;
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uint32 baseaddr;
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uint32 ioctrl;
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uint32 iostatus;
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uint32 resetctrl;
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uint32 resetstatus;
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uint32 resetreadid;
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uint32 resetwriteid;
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uint32 errlogctrl;
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uint32 errlogdone;
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uint32 errlogstatus;
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uint32 errlogaddrlo;
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uint32 errlogaddrhi;
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uint32 errlogid;
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uint32 errloguser;
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uint32 errlogflags;
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uint32 itipoobaout;
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uint32 itipoobbout;
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uint32 itipoobcout;
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uint32 itipoobdout;
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} hnd_ext_trap_bp_err_t;
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#define HND_EXT_TRAP_AXISR_INFO_VER_1 1
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typedef struct hnd_ext_trap_axi_sr_err_v1
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{
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uint8 version;
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uint8 pad[3];
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uint32 error;
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uint32 coreid;
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uint32 baseaddr;
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uint32 ioctrl;
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uint32 iostatus;
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uint32 resetctrl;
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uint32 resetstatus;
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uint32 resetreadid;
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uint32 resetwriteid;
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uint32 errlogctrl;
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uint32 errlogdone;
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uint32 errlogstatus;
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uint32 errlogaddrlo;
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uint32 errlogaddrhi;
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uint32 errlogid;
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uint32 errloguser;
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uint32 errlogflags;
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uint32 itipoobaout;
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uint32 itipoobbout;
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uint32 itipoobcout;
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uint32 itipoobdout;
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/* axi_sr_issue_debug */
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uint32 sr_pwr_control;
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uint32 sr_corereset_wrapper_main;
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uint32 sr_corereset_wrapper_aux;
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uint32 sr_main_gci_status_0;
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uint32 sr_aux_gci_status_0;
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uint32 sr_dig_gci_status_0;
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} hnd_ext_trap_axi_sr_err_v1_t;
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#define HND_EXT_TRAP_PSMWD_INFO_VER 1
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typedef struct hnd_ext_trap_psmwd_v1 {
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uint16 xtag;
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uint16 version; /* version of the information following this */
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uint32 i32_maccontrol;
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uint32 i32_maccommand;
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uint32 i32_macintstatus;
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uint32 i32_phydebug;
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uint32 i32_clk_ctl_st;
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uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1];
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uint16 i16_0x1a8; /* gated clock en */
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uint16 i16_0x406; /* Rcv Fifo Ctrl */
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uint16 i16_0x408; /* Rx ctrl 1 */
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uint16 i16_0x41a; /* Rxe Status 1 */
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uint16 i16_0x41c; /* Rxe Status 2 */
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uint16 i16_0x424; /* rcv wrd count 0 */
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uint16 i16_0x426; /* rcv wrd count 1 */
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uint16 i16_0x456; /* RCV_LFIFO_STS */
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uint16 i16_0x480; /* PSM_SLP_TMR */
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uint16 i16_0x490; /* PSM BRC */
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uint16 i16_0x500; /* TXE CTRL */
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uint16 i16_0x50e; /* TXE Status */
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uint16 i16_0x55e; /* TXE_xmtdmabusy */
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uint16 i16_0x566; /* TXE_XMTfifosuspflush */
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uint16 i16_0x690; /* IFS Stat */
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uint16 i16_0x692; /* IFS_MEDBUSY_CTR */
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uint16 i16_0x694; /* IFS_TX_DUR */
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uint16 i16_0x6a0; /* SLow_CTL */
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uint16 i16_0x838; /* TXE_AQM fifo Ready */
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uint16 i16_0x8c0; /* Dagg ctrl */
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uint16 shm_prewds_cnt;
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uint16 shm_txtplufl_cnt;
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uint16 shm_txphyerr_cnt;
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uint16 pad;
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} hnd_ext_trap_psmwd_v1_t;
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typedef struct hnd_ext_trap_psmwd {
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uint16 xtag;
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uint16 version; /* version of the information following this */
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uint32 i32_maccontrol;
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uint32 i32_maccommand;
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uint32 i32_macintstatus;
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uint32 i32_phydebug;
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uint32 i32_clk_ctl_st;
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uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2];
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uint16 i16_0x4b8; /* psm_brwk_0 */
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uint16 i16_0x4ba; /* psm_brwk_1 */
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uint16 i16_0x4bc; /* psm_brwk_2 */
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uint16 i16_0x4be; /* psm_brwk_2 */
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uint16 i16_0x1a8; /* gated clock en */
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uint16 i16_0x406; /* Rcv Fifo Ctrl */
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uint16 i16_0x408; /* Rx ctrl 1 */
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uint16 i16_0x41a; /* Rxe Status 1 */
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uint16 i16_0x41c; /* Rxe Status 2 */
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uint16 i16_0x424; /* rcv wrd count 0 */
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uint16 i16_0x426; /* rcv wrd count 1 */
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uint16 i16_0x456; /* RCV_LFIFO_STS */
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uint16 i16_0x480; /* PSM_SLP_TMR */
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uint16 i16_0x500; /* TXE CTRL */
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uint16 i16_0x50e; /* TXE Status */
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uint16 i16_0x55e; /* TXE_xmtdmabusy */
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uint16 i16_0x566; /* TXE_XMTfifosuspflush */
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uint16 i16_0x690; /* IFS Stat */
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uint16 i16_0x692; /* IFS_MEDBUSY_CTR */
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uint16 i16_0x694; /* IFS_TX_DUR */
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uint16 i16_0x6a0; /* SLow_CTL */
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uint16 i16_0x490; /* psm_brc */
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uint16 i16_0x4da; /* psm_brc_1 */
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uint16 i16_0x838; /* TXE_AQM fifo Ready */
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uint16 i16_0x8c0; /* Dagg ctrl */
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uint16 shm_prewds_cnt;
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uint16 shm_txtplufl_cnt;
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uint16 shm_txphyerr_cnt;
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} hnd_ext_trap_psmwd_t;
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#define HEAP_HISTOGRAM_DUMP_LEN 6
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#define HEAP_MAX_SZ_BLKS_LEN 2
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/* Ignore chunks for which there are fewer than this many instances, irrespective of size */
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#define HEAP_HISTOGRAM_INSTANCE_MIN 4
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/*
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* Use the last two length values for chunks larger than this, or when we run out of
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* histogram entries (because we have too many different sized chunks) to store "other"
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*/
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#define HEAP_HISTOGRAM_SPECIAL 0xfffeu
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#define HEAP_HISTOGRAM_GRTR256K 0xffffu
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typedef struct hnd_ext_trap_heap_err {
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uint32 arena_total;
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uint32 heap_free;
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uint32 heap_inuse;
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uint32 mf_count;
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uint32 stack_lwm;
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uint16 heap_histogm[HEAP_HISTOGRAM_DUMP_LEN * 2]; /* size/number */
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uint16 max_sz_free_blk[HEAP_MAX_SZ_BLKS_LEN];
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} hnd_ext_trap_heap_err_t;
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#define MEM_TRAP_NUM_WLC_TX_QUEUES 6
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#define HND_EXT_TRAP_WLC_MEM_ERR_VER_V2 2
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/* already there are quite a few chips which are ROM'ed wth this structure
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* Will not be adding version. This will be the V1 structure.
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*/
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typedef struct hnd_ext_trap_wlc_mem_err {
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uint8 instance;
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uint8 associated;
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uint8 soft_ap_client_cnt;
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uint8 peer_cnt;
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uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES];
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} hnd_ext_trap_wlc_mem_err_t;
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typedef struct hnd_ext_trap_wlc_mem_err_v2 {
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uint16 version;
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uint16 pad;
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uint8 instance;
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uint8 stas_associated;
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uint8 aps_associated;
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uint8 soft_ap_client_cnt;
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uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES];
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} hnd_ext_trap_wlc_mem_err_v2_t;
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#define HND_EXT_TRAP_WLC_MEM_ERR_VER_V3 3
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typedef struct hnd_ext_trap_wlc_mem_err_v3 {
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uint8 version;
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uint8 instance;
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uint8 stas_associated;
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uint8 aps_associated;
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uint8 soft_ap_client_cnt;
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uint8 peer_cnt;
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uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES];
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} hnd_ext_trap_wlc_mem_err_v3_t;
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typedef struct hnd_ext_trap_pcie_mem_err {
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uint16 d2h_queue_len;
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uint16 d2h_req_queue_len;
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} hnd_ext_trap_pcie_mem_err_t;
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#define MAX_DMAFIFO_ENTRIES_V1 1
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#define MAX_DMAFIFO_DESC_ENTRIES_V1 2
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#define HND_EXT_TRAP_AXIERROR_SIGNATURE 0xbabebabe
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#define HND_EXT_TRAP_AXIERROR_VERSION_1 1
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/* Structure to collect debug info of descriptor entry for dma channel on encountering AXI Error */
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/* Below three structures are dependant, any change will bump version of all the three */
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typedef struct hnd_ext_trap_desc_entry_v1 {
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uint32 ctrl1; /* descriptor entry at din < misc control bits > */
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uint32 ctrl2; /* descriptor entry at din <buffer count and address extension> */
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uint32 addrlo; /* descriptor entry at din <address of data buffer, bits 31:0> */
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uint32 addrhi; /* descriptor entry at din <address of data buffer, bits 63:32> */
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} dma_dentry_v1_t;
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/* Structure to collect debug info about a dma channel on encountering AXI Error */
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typedef struct hnd_ext_trap_dma_fifo_v1 {
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uint8 valid; /* no of valid desc entries filled, non zero = fifo entry valid */
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uint8 direction; /* TX=1, RX=2, currently only using TX */
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uint16 index; /* Index of the DMA channel in system */
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uint32 dpa; /* Expected Address of Descriptor table from software state */
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uint32 desc_lo; /* Low Address of Descriptor table programmed in DMA register */
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uint32 desc_hi; /* High Address of Descriptor table programmed in DMA register */
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uint16 din; /* rxin / txin */
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uint16 dout; /* rxout / txout */
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dma_dentry_v1_t dentry[MAX_DMAFIFO_DESC_ENTRIES_V1]; /* Descriptor Entires */
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} dma_fifo_v1_t;
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typedef struct hnd_ext_trap_axi_error_v1 {
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uint8 version; /* version = 1 */
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uint8 dma_fifo_valid_count; /* Number of valid dma_fifo entries */
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uint16 length; /* length of whole structure */
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uint32 signature; /* indicate that its filled with AXI Error data */
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uint32 axi_errorlog_status; /* errlog_status from slave wrapper */
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uint32 axi_errorlog_core; /* errlog_core from slave wrapper */
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uint32 axi_errorlog_lo; /* errlog_lo from slave wrapper */
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uint32 axi_errorlog_hi; /* errlog_hi from slave wrapper */
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uint32 axi_errorlog_id; /* errlog_id from slave wrapper */
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dma_fifo_v1_t dma_fifo[MAX_DMAFIFO_ENTRIES_V1];
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} hnd_ext_trap_axi_error_v1_t;
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#define HND_EXT_TRAP_MACSUSP_INFO_VER 1
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typedef struct hnd_ext_trap_macsusp {
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uint16 xtag;
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uint8 version; /* version of the information following this */
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uint8 trap_reason;
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uint32 i32_maccontrol;
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uint32 i32_maccommand;
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uint32 i32_macintstatus;
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uint32 i32_phydebug[4];
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uint32 i32_psmdebug[8];
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uint16 i16_0x41a; /* Rxe Status 1 */
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uint16 i16_0x41c; /* Rxe Status 2 */
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uint16 i16_0x490; /* PSM BRC */
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uint16 i16_0x50e; /* TXE Status */
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uint16 i16_0x55e; /* TXE_xmtdmabusy */
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uint16 i16_0x566; /* TXE_XMTfifosuspflush */
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uint16 i16_0x690; /* IFS Stat */
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uint16 i16_0x692; /* IFS_MEDBUSY_CTR */
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uint16 i16_0x694; /* IFS_TX_DUR */
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uint16 i16_0x7c0; /* WEP CTL */
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uint16 i16_0x838; /* TXE_AQM fifo Ready */
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uint16 i16_0x880; /* MHP_status */
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uint16 shm_prewds_cnt;
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uint16 shm_ucode_dbgst;
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} hnd_ext_trap_macsusp_t;
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#define HND_EXT_TRAP_MACENAB_INFO_VER 1
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typedef struct hnd_ext_trap_macenab {
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uint16 xtag;
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uint8 version; /* version of the information following this */
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uint8 trap_reason;
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uint32 i32_maccontrol;
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uint32 i32_maccommand;
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uint32 i32_macintstatus;
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uint32 i32_psmdebug[8];
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uint32 i32_clk_ctl_st;
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uint32 i32_powerctl;
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uint16 i16_0x1a8; /* gated clock en */
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uint16 i16_0x480; /* PSM_SLP_TMR */
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uint16 i16_0x490; /* PSM BRC */
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uint16 i16_0x600; /* TSF CTL */
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uint16 i16_0x690; /* IFS Stat */
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uint16 i16_0x692; /* IFS_MEDBUSY_CTR */
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uint16 i16_0x6a0; /* SLow_CTL */
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uint16 i16_0x6a6; /* SLow_FRAC */
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uint16 i16_0x6a8; /* fast power up delay */
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uint16 i16_0x6aa; /* SLow_PER */
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uint16 shm_ucode_dbgst;
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uint16 PAD;
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} hnd_ext_trap_macenab_t;
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#define HND_EXT_TRAP_PHY_INFO_VER_1 (1)
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typedef struct hnd_ext_trap_phydbg {
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uint16 err;
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uint16 RxFeStatus;
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uint16 TxFIFOStatus0;
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uint16 TxFIFOStatus1;
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uint16 RfseqMode;
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uint16 RfseqStatus0;
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uint16 RfseqStatus1;
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uint16 RfseqStatus_Ocl;
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uint16 RfseqStatus_Ocl1;
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uint16 OCLControl1;
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uint16 TxError;
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uint16 bphyTxError;
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uint16 TxCCKError;
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uint16 TxCtrlWrd0;
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uint16 TxCtrlWrd1;
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uint16 TxCtrlWrd2;
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uint16 TxLsig0;
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uint16 TxLsig1;
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uint16 TxVhtSigA10;
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uint16 TxVhtSigA11;
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uint16 TxVhtSigA20;
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uint16 TxVhtSigA21;
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uint16 txPktLength;
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uint16 txPsdulengthCtr;
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uint16 gpioClkControl;
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uint16 gpioSel;
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uint16 pktprocdebug;
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uint16 PAD;
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uint32 gpioOut[3];
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} hnd_ext_trap_phydbg_t;
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/* unique IDs for separate cores in SI */
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#define REGDUMP_MASK_MAC0 BCM_BIT(1)
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#define REGDUMP_MASK_ARM BCM_BIT(2)
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#define REGDUMP_MASK_PCIE BCM_BIT(3)
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#define REGDUMP_MASK_MAC1 BCM_BIT(4)
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#define REGDUMP_MASK_PMU BCM_BIT(5)
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typedef struct {
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uint16 reg_offset;
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uint16 core_mask;
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} reg_dump_config_t;
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#define HND_EXT_TRAP_PHY_INFO_VER 2
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typedef struct hnd_ext_trap_phydbg_v2 {
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uint8 version;
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uint8 len;
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uint16 err;
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uint16 RxFeStatus;
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uint16 TxFIFOStatus0;
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uint16 TxFIFOStatus1;
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uint16 RfseqMode;
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uint16 RfseqStatus0;
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uint16 RfseqStatus1;
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uint16 RfseqStatus_Ocl;
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uint16 RfseqStatus_Ocl1;
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uint16 OCLControl1;
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uint16 TxError;
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uint16 bphyTxError;
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uint16 TxCCKError;
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uint16 TxCtrlWrd0;
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uint16 TxCtrlWrd1;
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uint16 TxCtrlWrd2;
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uint16 TxLsig0;
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uint16 TxLsig1;
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uint16 TxVhtSigA10;
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uint16 TxVhtSigA11;
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uint16 TxVhtSigA20;
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uint16 TxVhtSigA21;
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uint16 txPktLength;
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uint16 txPsdulengthCtr;
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uint16 gpioClkControl;
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uint16 gpioSel;
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uint16 pktprocdebug;
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uint32 gpioOut[3];
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uint32 additional_regs[1];
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} hnd_ext_trap_phydbg_v2_t;
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#define HND_EXT_TRAP_PHY_INFO_VER_3 (3)
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typedef struct hnd_ext_trap_phydbg_v3 {
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uint8 version;
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uint8 len;
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uint16 err;
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uint16 RxFeStatus;
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uint16 TxFIFOStatus0;
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uint16 TxFIFOStatus1;
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uint16 RfseqMode;
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uint16 RfseqStatus0;
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uint16 RfseqStatus1;
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uint16 RfseqStatus_Ocl;
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uint16 RfseqStatus_Ocl1;
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uint16 OCLControl1;
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uint16 TxError;
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uint16 bphyTxError;
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uint16 TxCCKError;
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uint16 TxCtrlWrd0;
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uint16 TxCtrlWrd1;
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uint16 TxCtrlWrd2;
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uint16 TxLsig0;
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uint16 TxLsig1;
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uint16 TxVhtSigA10;
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uint16 TxVhtSigA11;
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uint16 TxVhtSigA20;
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uint16 TxVhtSigA21;
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uint16 txPktLength;
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uint16 txPsdulengthCtr;
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uint16 gpioClkControl;
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uint16 gpioSel;
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uint16 pktprocdebug;
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uint32 gpioOut[3];
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uint16 HESigURateFlagStatus;
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uint16 HESigUsRateFlagStatus;
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uint32 additional_regs[1];
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} hnd_ext_trap_phydbg_v3_t;
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/* Phy TxErr Dump Structure */
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#define HND_EXT_TRAP_PHYTXERR_INFO_VER 1
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#define HND_EXT_TRAP_PHYTXERR_INFO_VER_V2 2
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typedef struct hnd_ext_trap_macphytxerr {
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uint8 version; /* version of the information following this */
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uint8 trap_reason;
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uint16 i16_0x63E; /* tsf_tmr_rx_ts */
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uint16 i16_0x640; /* tsf_tmr_tx_ts */
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uint16 i16_0x642; /* tsf_tmr_rx_end_ts */
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uint16 i16_0x846; /* TDC_FrmLen0 */
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uint16 i16_0x848; /* TDC_FrmLen1 */
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uint16 i16_0x84a; /* TDC_Txtime */
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uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */
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uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */
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uint16 i16_0x856; /* TDC_VhtPsduLen0 */
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uint16 i16_0x858; /* TDC_VhtPsduLen1 */
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uint16 i16_0x490; /* psm_brc */
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uint16 i16_0x4d8; /* psm_brc_1 */
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uint16 shm_txerr_reason;
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uint16 shm_pctl0;
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uint16 shm_pctl1;
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uint16 shm_pctl2;
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uint16 shm_lsig0;
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uint16 shm_lsig1;
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uint16 shm_plcp0;
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uint16 shm_plcp1;
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uint16 shm_plcp2;
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uint16 shm_vht_sigb0;
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uint16 shm_vht_sigb1;
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uint16 shm_tx_tst;
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uint16 shm_txerr_tm;
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uint16 shm_curchannel;
|
uint16 shm_crx_rxtsf_pos;
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uint16 shm_lasttx_tsf;
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uint16 shm_s_rxtsftmrval;
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uint16 i16_0x29; /* Phy indirect address */
|
uint16 i16_0x2a; /* Phy indirect address */
|
} hnd_ext_trap_macphytxerr_t;
|
|
typedef struct hnd_ext_trap_macphytxerr_v2 {
|
uint8 version; /* version of the information following this */
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uint8 trap_reason;
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uint16 i16_0x63E; /* tsf_tmr_rx_ts */
|
uint16 i16_0x640; /* tsf_tmr_tx_ts */
|
uint16 i16_0x642; /* tsf_tmr_rx_end_ts */
|
uint16 i16_0x846; /* TDC_FrmLen0 */
|
uint16 i16_0x848; /* TDC_FrmLen1 */
|
uint16 i16_0x84a; /* TDC_Txtime */
|
uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */
|
uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */
|
uint16 i16_0x856; /* TDC_VhtPsduLen0 */
|
uint16 i16_0x858; /* TDC_VhtPsduLen1 */
|
uint16 i16_0x490; /* psm_brc */
|
uint16 i16_0x4d8; /* psm_brc_1 */
|
uint16 shm_txerr_reason;
|
uint16 shm_pctl0;
|
uint16 shm_pctl1;
|
uint16 shm_pctl2;
|
uint16 shm_lsig0;
|
uint16 shm_lsig1;
|
uint16 shm_plcp0;
|
uint16 shm_plcp1;
|
uint16 shm_plcp2;
|
uint16 shm_vht_sigb0;
|
uint16 shm_vht_sigb1;
|
uint16 shm_tx_tst;
|
uint16 shm_txerr_tm;
|
uint16 shm_curchannel;
|
uint16 shm_crx_rxtsf_pos;
|
uint16 shm_lasttx_tsf;
|
uint16 shm_s_rxtsftmrval;
|
uint16 i16_0x29; /* Phy indirect address */
|
uint16 i16_0x2a; /* Phy indirect address */
|
uint8 phyerr_bmac_cnt; /* number of times bmac raised phy tx err */
|
uint8 phyerr_bmac_rsn; /* bmac reason for phy tx error */
|
uint16 pad;
|
uint32 recv_fifo_status[3][2]; /* Rcv Status0 & Rcv Status1 for 3 Rx fifos */
|
} hnd_ext_trap_macphytxerr_v2_t;
|
|
#define HND_EXT_TRAP_PCIE_ERR_ATTN_VER_1 (1u)
|
#define MAX_AER_HDR_LOG_REGS (4u)
|
typedef struct hnd_ext_trap_pcie_err_attn_v1 {
|
uint8 version;
|
uint8 pad[3];
|
uint32 err_hdr_logreg1;
|
uint32 err_hdr_logreg2;
|
uint32 err_hdr_logreg3;
|
uint32 err_hdr_logreg4;
|
uint32 err_code_logreg;
|
uint32 err_type;
|
uint32 err_code_state;
|
uint32 last_err_attn_ts;
|
uint32 cfg_tlp_hdr[MAX_AER_HDR_LOG_REGS];
|
} hnd_ext_trap_pcie_err_attn_v1_t;
|
|
#define MAX_EVENTLOG_BUFFERS 48
|
typedef struct eventlog_trapdata_info {
|
uint32 num_elements;
|
uint32 seq_num;
|
uint32 log_arr_addr;
|
} eventlog_trapdata_info_t;
|
|
typedef struct eventlog_trap_buf_info {
|
uint32 len;
|
uint32 buf_addr;
|
} eventlog_trap_buf_info_t;
|
|
#define HND_MEM_HC_FB_MEM_VER_1 (1u)
|
typedef struct hnd_ext_trap_fb_mem_err {
|
uint16 version;
|
uint16 reserved;
|
uint32 flip_bit_err_time;
|
} hnd_ext_trap_fb_mem_err_t;
|
|
#if defined(ETD) && !defined(WLETD)
|
#define ETD_SW_FLAG_MEM 0x00000001
|
|
int etd_init(osl_t *osh);
|
int etd_register_trap_ext_callback(void *cb, void *arg);
|
int (etd_register_trap_ext_callback_late)(void *cb, void *arg);
|
uint32 *etd_get_trap_ext_data(void);
|
uint32 etd_get_trap_ext_swflags(void);
|
void etd_set_trap_ext_swflag(uint32 flag);
|
void etd_notify_trap_ext_callback(trap_t *tr);
|
reg_dump_config_t *etd_get_reg_dump_config_tbl(void);
|
uint etd_get_reg_dump_config_len(void);
|
|
extern bool _etd_enab;
|
|
#if defined(ROM_ENAB_RUNTIME_CHECK)
|
#define ETD_ENAB(pub) (_etd_enab)
|
#elif defined(ETD_DISABLED)
|
#define ETD_ENAB(pub) (0)
|
#else
|
#define ETD_ENAB(pub) (1)
|
#endif
|
|
#else
|
#define ETD_ENAB(pub) (0)
|
#endif /* WLETD */
|
|
#endif /* !LANGUAGE_ASSEMBLY */
|
|
#endif /* _ETD_H_ */
|
