/*
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* HND Run Time Environment ioctl.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _dngl_ioctl_h_
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#define _dngl_ioctl_h_
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/* ==== Dongle IOCTLs i.e. non-d11 IOCTLs ==== */
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#ifndef _rte_ioctl_h_
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/* ================================================================ */
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/* These are the existing ioctls moved from src/include/rte_ioctl.h */
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/* ================================================================ */
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/* RTE IOCTL definitions for generic ether devices */
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#define RTEIOCTLSTART 0x8901
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#define RTEGHWADDR 0x8901
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#define RTESHWADDR 0x8902
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#define RTEGMTU 0x8903
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#define RTEGSTATS 0x8904
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#define RTEGALLMULTI 0x8905
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#define RTESALLMULTI 0x8906
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#define RTEGPROMISC 0x8907
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#define RTESPROMISC 0x8908
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#define RTESMULTILIST 0x8909
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#define RTEGUP 0x890A
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#define RTEGPERMADDR 0x890B
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#define RTEDEVPWRSTCHG 0x890C /* Device pwr state change for PCIedev */
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#define RTEDEVPMETOGGLE 0x890D /* Toggle PME# to wake up the host */
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#define RTEDEVTIMESYNC 0x890E /* Device TimeSync */
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#define RTEDEVDSNOTIFY 0x890F /* Bus DS state notification */
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#define RTED11DMALPBK_INIT 0x8910 /* D11 DMA loopback init */
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#define RTED11DMALPBK_UNINIT 0x8911 /* D11 DMA loopback uninit */
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#define RTED11DMALPBK_RUN 0x8912 /* D11 DMA loopback run */
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#define RTEDEVTSBUFPOST 0x8913 /* Async interface for tsync buffer post */
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#define RTED11DMAHOSTLPBK_RUN 0x8914 /* D11 DMA host memory loopback run */
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#define RTEDEVGETTSF 0x8915 /* Get device TSF */
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#define RTEDURATIONUNIT 0x8916 /* Duration unit */
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#define RTEWRITE_WAR_REGS 0x8917 /* write workaround regs */
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#define RTEDEVRMPMK 0x8918 /* Remove PMK */
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#define RTEDEVDBGVAL 0x8919 /* Set debug val */
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/* Ensure last RTE IOCTL define val is assigned to RTEIOCTLEND */
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#define RTEIOCTLEND 0x8919 /* LAST RTE IOCTL value */
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#define RTE_IOCTL_QUERY 0x00
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#define RTE_IOCTL_SET 0x01
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#define RTE_IOCTL_OVL_IDX_MASK 0x1e
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#define RTE_IOCTL_OVL_RSV 0x20
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#define RTE_IOCTL_OVL 0x40
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#define RTE_IOCTL_OVL_IDX_SHIFT 1
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enum hnd_ioctl_cmd {
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HND_RTE_DNGL_IS_SS = 1, /* true if device connected at super speed */
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/* PCIEDEV specific wl <--> bus ioctls */
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BUS_GET_VAR = 2,
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BUS_SET_VAR = 3,
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BUS_FLUSH_RXREORDER_Q = 4,
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BUS_SET_LTR_STATE = 5,
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BUS_FLUSH_CHAINED_PKTS = 6,
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BUS_SET_COPY_COUNT = 7,
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BUS_UPDATE_FLOW_PKTS_MAX = 8,
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BUS_UPDATE_EXTRA_TXLFRAGS = 9,
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BUS_UPDATE_FRWD_RESRV_BUFCNT = 10,
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BUS_PCIE_CONFIG_ACCESS = 11,
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BUS_HC_EVENT_MASK_UPDATE = 12,
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BUS_SET_MAC_WAKE_STATE = 13,
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BUS_FRWD_PKT_RXCMPLT = 14,
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BUS_PCIE_LATENCY_ENAB = 15, /* to enable latency feature in pcie */
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BUS_GET_MAXITEMS = 16,
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BUS_SET_BUS_CSO_CAP = 17, /* Update the CSO cap from wl layer to bus layer */
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BUS_DUMP_RX_DMA_STALL_RELATED_INFO = 18,
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BUS_UPDATE_RESVPOOL_STATE = 19 /* Update resvpool state */
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};
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#define SDPCMDEV_SET_MAXTXPKTGLOM 1
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#define RTE_MEMUSEINFO_VER 0x00
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typedef struct memuse_info {
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uint16 ver; /* version of this struct */
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uint16 len; /* length in bytes of this structure */
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uint32 tot; /* Total memory */
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uint32 text_len; /* Size of Text segment memory */
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uint32 data_len; /* Size of Data segment memory */
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uint32 bss_len; /* Size of BSS segment memory */
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uint32 arena_size; /* Total Heap size */
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uint32 arena_free; /* Heap memory available or free */
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uint32 inuse_size; /* Heap memory currently in use */
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uint32 inuse_hwm; /* High watermark of memory - reclaimed memory */
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uint32 inuse_overhead; /* tally of allocated mem_t blocks */
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uint32 inuse_total; /* Heap in-use + Heap overhead memory */
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uint32 free_lwm; /* Least free size since reclaim */
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uint32 mf_count; /* Malloc failure count */
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} memuse_info_t;
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/* Different DMA loopback modes */
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#define M2M_DMA_LOOPBACK 0 /* PCIE M2M mode */
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#define D11_DMA_LOOPBACK 1 /* PCIE M2M and D11 mode without ucode */
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#define BMC_DMA_LOOPBACK 2 /* PCIE M2M and D11 mode with ucode */
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#define M2M_NON_DMA_LOOPBACK 3 /* Non DMA(indirect) mode */
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#define D11_DMA_HOST_MEM_LPBK 4 /* D11 mode */
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#define M2M_DMA_WRITE_TO_RAM 6 /* PCIE M2M write to specific memory mode */
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#define M2M_DMA_READ_FROM_RAM 7 /* PCIE M2M read from specific memory mode */
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#define D11_DMA_WRITE_TO_RAM 8 /* D11 write to specific memory mode */
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#define D11_DMA_READ_FROM_RAM 9 /* D11 read from specific memory mode */
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/* For D11 DMA loopback test */
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typedef struct d11_dmalpbk_init_args {
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uint8 core_num;
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uint8 lpbk_mode;
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} d11_dmalpbk_init_args_t;
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typedef struct d11_dmalpbk_args {
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uint8 *buf;
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int32 len;
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void *p;
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uint8 core_num;
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uint8 pad[3];
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} d11_dmalpbk_args_t;
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typedef enum wl_config_var {
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WL_VAR_TX_PKTFETCH_INDUCE = 1,
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WL_VAR_LAST
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} wl_config_var_t;
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typedef struct wl_config_buf {
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wl_config_var_t var;
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uint32 val;
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} wl_config_buf_t;
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/* ================================================================ */
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/* These are the existing ioctls moved from src/include/rte_ioctl.h */
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/* ================================================================ */
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#endif /* _rte_ioctl_h_ */
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/* MPU test iovar version */
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#define MPU_TEST_STRUCT_VER 0
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/* MPU test OP */
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#define MPU_TEST_OP_READ 0
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#define MPU_TEST_OP_WRITE 1
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#define MPU_TEST_OP_EXECUTE 2
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/* Debug iovar for MPU testing */
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typedef struct mpu_test_args {
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/* version control */
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uint16 ver;
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uint16 len; /* the length of this structure */
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/* data */
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uint32 addr;
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uint8 op; /* see MPU_TEST_OP_XXXX */
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uint8 rsvd;
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uint16 size; /* valid for read/write */
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uint8 val[];
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} mpu_test_args_t;
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#endif /* _dngl_ioctl_h_ */
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