/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "mt76x2.h"
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#include "mt76x2_eeprom.h"
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static void
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mt76x2_adjust_high_lna_gain(struct mt76x2_dev *dev, int reg, s8 offset)
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{
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s8 gain;
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gain = FIELD_GET(MT_BBP_AGC_LNA_HIGH_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
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gain -= offset / 2;
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mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain);
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}
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static void
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mt76x2_adjust_agc_gain(struct mt76x2_dev *dev, int reg, s8 offset)
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{
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s8 gain;
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gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
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gain += offset;
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mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
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}
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void mt76x2_apply_gain_adj(struct mt76x2_dev *dev)
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{
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s8 *gain_adj = dev->cal.rx.high_gain;
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mt76x2_adjust_high_lna_gain(dev, 4, gain_adj[0]);
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mt76x2_adjust_high_lna_gain(dev, 5, gain_adj[1]);
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mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]);
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mt76x2_adjust_agc_gain(dev, 9, gain_adj[1]);
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}
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EXPORT_SYMBOL_GPL(mt76x2_apply_gain_adj);
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void mt76x2_phy_set_txpower_regs(struct mt76x2_dev *dev,
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enum nl80211_band band)
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{
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u32 pa_mode[2];
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u32 pa_mode_adj;
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if (band == NL80211_BAND_2GHZ) {
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pa_mode[0] = 0x010055ff;
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pa_mode[1] = 0x00550055;
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mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
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mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
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if (mt76x2_ext_pa_enabled(dev, band)) {
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mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
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mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
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} else {
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mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
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mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
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}
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} else {
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pa_mode[0] = 0x0000ffff;
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pa_mode[1] = 0x00ff00ff;
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if (mt76x2_ext_pa_enabled(dev, band)) {
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mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400);
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mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476);
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} else {
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mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
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mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
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}
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if (mt76x2_ext_pa_enabled(dev, band))
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pa_mode_adj = 0x04000000;
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else
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pa_mode_adj = 0;
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mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
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mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
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}
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mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
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mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
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mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
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mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
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if (mt76x2_ext_pa_enabled(dev, band)) {
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u32 val;
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if (band == NL80211_BAND_2GHZ)
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val = 0x3c3c023c;
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else
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val = 0x363c023c;
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mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
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mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
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mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
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} else {
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if (band == NL80211_BAND_2GHZ) {
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u32 val = 0x0f3c3c3c;
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mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
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mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
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mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
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} else {
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mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
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mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
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mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
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}
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}
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}
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EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower_regs);
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static void
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mt76x2_limit_rate_power(struct mt76_rate_power *r, int limit)
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{
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int i;
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for (i = 0; i < sizeof(r->all); i++)
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if (r->all[i] > limit)
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r->all[i] = limit;
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}
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static u32
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mt76x2_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
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{
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u32 val = 0;
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val |= (v1 & (BIT(6) - 1)) << 0;
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val |= (v2 & (BIT(6) - 1)) << 8;
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val |= (v3 & (BIT(6) - 1)) << 16;
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val |= (v4 & (BIT(6) - 1)) << 24;
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return val;
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}
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static void
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mt76x2_add_rate_power_offset(struct mt76_rate_power *r, int offset)
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{
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int i;
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for (i = 0; i < sizeof(r->all); i++)
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r->all[i] += offset;
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}
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static int
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mt76x2_get_min_rate_power(struct mt76_rate_power *r)
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{
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int i;
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s8 ret = 0;
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for (i = 0; i < sizeof(r->all); i++) {
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if (!r->all[i])
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continue;
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if (ret)
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ret = min(ret, r->all[i]);
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else
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ret = r->all[i];
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}
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return ret;
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}
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void mt76x2_phy_set_txpower(struct mt76x2_dev *dev)
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{
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enum nl80211_chan_width width = dev->mt76.chandef.width;
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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struct mt76x2_tx_power_info txp;
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int txp_0, txp_1, delta = 0;
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struct mt76_rate_power t = {};
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int base_power, gain;
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mt76x2_get_power_info(dev, &txp, chan);
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if (width == NL80211_CHAN_WIDTH_40)
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delta = txp.delta_bw40;
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else if (width == NL80211_CHAN_WIDTH_80)
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delta = txp.delta_bw80;
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mt76x2_get_rate_power(dev, &t, chan);
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mt76x2_add_rate_power_offset(&t, txp.chain[0].target_power);
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mt76x2_limit_rate_power(&t, dev->txpower_conf);
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dev->txpower_cur = mt76x2_get_max_rate_power(&t);
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base_power = mt76x2_get_min_rate_power(&t);
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delta += base_power - txp.chain[0].target_power;
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txp_0 = txp.chain[0].target_power + txp.chain[0].delta + delta;
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txp_1 = txp.chain[1].target_power + txp.chain[1].delta + delta;
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gain = min(txp_0, txp_1);
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if (gain < 0) {
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base_power -= gain;
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txp_0 -= gain;
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txp_1 -= gain;
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} else if (gain > 0x2f) {
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base_power -= gain - 0x2f;
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txp_0 = 0x2f;
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txp_1 = 0x2f;
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}
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mt76x2_add_rate_power_offset(&t, -base_power);
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dev->target_power = txp.chain[0].target_power;
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dev->target_power_delta[0] = txp_0 - txp.chain[0].target_power;
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dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power;
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dev->rate_power = t;
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mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
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mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
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mt76_wr(dev, MT_TX_PWR_CFG_0,
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mt76x2_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
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mt76_wr(dev, MT_TX_PWR_CFG_1,
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mt76x2_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[2]));
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mt76_wr(dev, MT_TX_PWR_CFG_2,
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mt76x2_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
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mt76_wr(dev, MT_TX_PWR_CFG_3,
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mt76x2_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
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mt76_wr(dev, MT_TX_PWR_CFG_4,
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mt76x2_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
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mt76_wr(dev, MT_TX_PWR_CFG_7,
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mt76x2_tx_power_mask(t.ofdm[6], t.vht[8], t.ht[6], t.vht[8]));
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mt76_wr(dev, MT_TX_PWR_CFG_8,
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mt76x2_tx_power_mask(t.ht[14], 0, t.vht[8], t.vht[8]));
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mt76_wr(dev, MT_TX_PWR_CFG_9,
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mt76x2_tx_power_mask(t.ht[6], 0, t.vht[8], t.vht[8]));
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}
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EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower);
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void mt76x2_configure_tx_delay(struct mt76x2_dev *dev,
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enum nl80211_band band, u8 bw)
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{
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u32 cfg0, cfg1;
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if (mt76x2_ext_pa_enabled(dev, band)) {
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cfg0 = bw ? 0x000b0c01 : 0x00101101;
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cfg1 = 0x00011414;
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} else {
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cfg0 = bw ? 0x000b0b01 : 0x00101001;
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cfg1 = 0x00021414;
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}
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mt76_wr(dev, MT_TX_SW_CFG0, cfg0);
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mt76_wr(dev, MT_TX_SW_CFG1, cfg1);
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mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, 15);
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}
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EXPORT_SYMBOL_GPL(mt76x2_configure_tx_delay);
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void mt76x2_phy_set_bw(struct mt76x2_dev *dev, int width, u8 ctrl)
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{
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int core_val, agc_val;
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switch (width) {
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case NL80211_CHAN_WIDTH_80:
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core_val = 3;
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agc_val = 7;
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break;
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case NL80211_CHAN_WIDTH_40:
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core_val = 2;
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agc_val = 3;
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break;
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default:
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core_val = 0;
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agc_val = 1;
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break;
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}
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mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
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mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
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mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
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mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
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}
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EXPORT_SYMBOL_GPL(mt76x2_phy_set_bw);
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void mt76x2_phy_set_band(struct mt76x2_dev *dev, int band, bool primary_upper)
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{
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switch (band) {
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case NL80211_BAND_2GHZ:
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mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
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mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
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break;
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case NL80211_BAND_5GHZ:
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mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
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mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
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break;
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}
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mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
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primary_upper);
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}
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EXPORT_SYMBOL_GPL(mt76x2_phy_set_band);
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int mt76x2_phy_get_min_avg_rssi(struct mt76x2_dev *dev)
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{
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struct mt76x2_sta *sta;
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struct mt76_wcid *wcid;
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int i, j, min_rssi = 0;
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s8 cur_rssi;
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local_bh_disable();
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rcu_read_lock();
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for (i = 0; i < ARRAY_SIZE(dev->wcid_mask); i++) {
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unsigned long mask = dev->wcid_mask[i];
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if (!mask)
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continue;
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for (j = i * BITS_PER_LONG; mask; j++, mask >>= 1) {
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if (!(mask & 1))
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continue;
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wcid = rcu_dereference(dev->wcid[j]);
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if (!wcid)
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continue;
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sta = container_of(wcid, struct mt76x2_sta, wcid);
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spin_lock(&dev->mt76.rx_lock);
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if (sta->inactive_count++ < 5)
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cur_rssi = ewma_signal_read(&sta->rssi);
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else
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cur_rssi = 0;
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spin_unlock(&dev->mt76.rx_lock);
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if (cur_rssi < min_rssi)
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min_rssi = cur_rssi;
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}
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}
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rcu_read_unlock();
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local_bh_enable();
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if (!min_rssi)
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return -75;
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return min_rssi;
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}
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EXPORT_SYMBOL_GPL(mt76x2_phy_get_min_avg_rssi);
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