// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Algea Cao <algea.cao@rock-chips.com>
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*/
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/gpio/consumer.h>
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#include <linux/mfd/rk630.h>
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static int rk630_macphy_enable(struct rk630 *rk630, unsigned long rate)
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{
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u32 val;
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int ret;
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/* IOMUX */
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val = 0xfffc5554;
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ret = regmap_write(rk630->grf, GRF_REG(0x8), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
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return ret;
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}
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/* IOMUX */
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val = 0x00330021;
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ret = regmap_write(rk630->grf, GRF_REG(0x10), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
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return ret;
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}
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/* reset */
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val = BIT(12 + 16) | BIT(12);
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ret = regmap_write(rk630->cru, CRU_REG(0x50), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
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return ret;
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}
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usleep_range(20, 30);
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val = BIT(12 + 16);
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ret = regmap_write(rk630->cru, CRU_REG(0x50), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
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return ret;
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}
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usleep_range(20, 30);
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/* power up && led*/
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val = BIT(1 + 16) | BIT(1) | BIT(2 + 16);
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ret = regmap_write(rk630->grf, GRF_REG(0x408), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
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return ret;
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}
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usleep_range(20000, 50000);
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/* mdio_sel: mdio */
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val = BIT(8 + 16) | BIT(8);
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ret = regmap_write(rk630->grf, GRF_REG(0x400), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
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return ret;
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}
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/* mode sel: RMII && BGS value: OTP && id */
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val = (2 << 14) | (0 << 12) | (0x1 << 8) | 1;
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switch (rate) {
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case 24000000:
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val |= 0x6 << 5;
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break;
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case 25000000:
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val |= 0x4 << 5;
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break;
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case 27000000:
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val |= 0x5 << 5;
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break;
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default:
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dev_err(rk630->dev, "Unsupported clock rate: %ld\n", rate);
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return -EINVAL;
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}
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ret = regmap_write(rk630->grf, GRF_REG(0x404), val | 0xffff0000);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
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return ret;
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}
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usleep_range(100, 150);
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return 0;
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}
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static int rk630_macphy_disable(struct rk630 *rk630)
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{
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u32 val;
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int ret;
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/* GRF_SOC_CON2_CFG */
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val = BIT(2) | BIT(16 + 2);
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ret = regmap_write(rk630->grf, GRF_REG(0x408), val);
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if (ret != 0) {
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dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct mfd_cell rk630_devs[] = {
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{
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.name = "rk630-efuse",
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.of_compatible = "rockchip,rk630-efuse",
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},
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{
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.name = "rk630-pinctrl",
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.of_compatible = "rockchip,rk630-pinctrl",
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},
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{
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.name = "rk630-tve",
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.of_compatible = "rockchip,rk630-tve",
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},
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{
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.name = "rk630-rtc",
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.of_compatible = "rockchip,rk630-rtc",
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},
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{
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.name = "rk630-macphy",
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.of_compatible = "rockchip,rk630-macphy",
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},
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{
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.name = "rk630-codec",
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.of_compatible = "rockchip,rk630-codec",
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},
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};
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static const struct regmap_range rk630_grf_readable_ranges[] = {
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regmap_reg_range(PLUMAGE_GRF_GPIO0A_IOMUX, PLUMAGE_GRF_GPIO0A_IOMUX),
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regmap_reg_range(PLUMAGE_GRF_GPIO0B_IOMUX, PLUMAGE_GRF_GPIO0B_IOMUX),
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regmap_reg_range(PLUMAGE_GRF_GPIO0C_IOMUX, PLUMAGE_GRF_GPIO0C_IOMUX),
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regmap_reg_range(PLUMAGE_GRF_GPIO0D_IOMUX, PLUMAGE_GRF_GPIO0D_IOMUX),
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regmap_reg_range(PLUMAGE_GRF_GPIO1A_IOMUX, PLUMAGE_GRF_GPIO1A_IOMUX),
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regmap_reg_range(PLUMAGE_GRF_GPIO1B_IOMUX, PLUMAGE_GRF_GPIO1B_IOMUX),
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regmap_reg_range(PLUMAGE_GRF_GPIO0A_P, PLUMAGE_GRF_GPIO1B_P),
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regmap_reg_range(PLUMAGE_GRF_GPIO1B_SR, PLUMAGE_GRF_GPIO1B_SR),
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regmap_reg_range(PLUMAGE_GRF_GPIO1B_E, PLUMAGE_GRF_GPIO1B_E),
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regmap_reg_range(PLUMAGE_GRF_SOC_CON0, PLUMAGE_GRF_SOC_CON4),
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regmap_reg_range(PLUMAGE_GRF_SOC_STATUS, PLUMAGE_GRF_SOC_STATUS),
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regmap_reg_range(PLUMAGE_GRF_GPIO0_REN0, PLUMAGE_GRF_GPIO1_REN0),
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};
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static const struct regmap_access_table rk630_grf_readable_table = {
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.yes_ranges = rk630_grf_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk630_grf_readable_ranges),
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};
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const struct regmap_config rk630_grf_regmap_config = {
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.name = "grf",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = GRF_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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.rd_table = &rk630_grf_readable_table,
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};
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EXPORT_SYMBOL_GPL(rk630_grf_regmap_config);
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static const struct regmap_range rk630_pinctrl_readable_ranges[] = {
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regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID),
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regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID),
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};
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static const struct regmap_access_table rk630_pinctrl_readable_table = {
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.yes_ranges = rk630_pinctrl_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk630_pinctrl_readable_ranges),
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};
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const struct regmap_config rk630_pinctrl_regmap_config = {
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.name = "pinctrl",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = GPIO_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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.rd_table = &rk630_pinctrl_readable_table,
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};
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static const struct regmap_range rk630_cru_readable_ranges[] = {
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regmap_reg_range(CRU_SPLL_CON0, CRU_SPLL_CON2),
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regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON),
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regmap_reg_range(CRU_CLKSEL_CON0, CRU_CLKSEL_CON3),
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regmap_reg_range(CRU_GATE_CON0, CRU_GATE_CON0),
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regmap_reg_range(CRU_SOFTRST_CON0, CRU_SOFTRST_CON0),
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};
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static const struct regmap_access_table rk630_cru_readable_table = {
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.yes_ranges = rk630_cru_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk630_cru_readable_ranges),
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};
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const struct regmap_config rk630_cru_regmap_config = {
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.name = "cru",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = CRU_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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.rd_table = &rk630_cru_readable_table,
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};
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static const struct regmap_range rk630_rtc_readable_ranges[] = {
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regmap_reg_range(RTC_SET_SECONDS, RTC_CNT_3),
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};
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static const struct regmap_access_table rk630_rtc_readable_table = {
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.yes_ranges = rk630_rtc_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk630_rtc_readable_ranges),
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};
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const struct regmap_config rk630_rtc_regmap_config = {
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.name = "rtc",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = RTC_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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.rd_table = &rk630_rtc_readable_table,
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};
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int rk630_core_probe(struct rk630 *rk630)
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{
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bool macphy_enabled = false;
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struct device_node *np;
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unsigned long rate;
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int ret;
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rk630->ref_clk = devm_clk_get(rk630->dev, "ref");
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if (IS_ERR(rk630->ref_clk)) {
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dev_err(rk630->dev, "failed to get ref clk source\n");
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return PTR_ERR(rk630->ref_clk);
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}
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ret = clk_prepare_enable(rk630->ref_clk);
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if (ret < 0) {
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dev_err(rk630->dev, "failed to enable ref clk - %d\n", ret);
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return ret;
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}
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rate = clk_get_rate(rk630->ref_clk);
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ret = devm_add_action_or_reset(rk630->dev, (void (*) (void *))clk_disable_unprepare,
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rk630->ref_clk);
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if (ret)
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return ret;
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rk630->reset_gpio = devm_gpiod_get(rk630->dev, "reset", 0);
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if (IS_ERR(rk630->reset_gpio)) {
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ret = PTR_ERR(rk630->reset_gpio);
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dev_err(rk630->dev, "failed to request reset GPIO: %d\n", ret);
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return ret;
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}
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gpiod_direction_output(rk630->reset_gpio, 0);
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usleep_range(2000, 4000);
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gpiod_direction_output(rk630->reset_gpio, 1);
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usleep_range(50000, 60000);
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gpiod_direction_output(rk630->reset_gpio, 0);
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if (!rk630->irq) {
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dev_err(rk630->dev, "No interrupt support, no core IRQ\n");
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return -EINVAL;
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}
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regmap_update_bits(rk630->grf, PLUMAGE_GRF_SOC_CON0,
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RTC_CLAMP_EN_MASK, RTC_CLAMP_EN(1));
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/* disable ext_off\vbat_det\msec\sys_int\periodic interrupt by default */
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regmap_write(rk630->rtc, RTC_INT1_EN, 0);
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ret = devm_mfd_add_devices(rk630->dev, PLATFORM_DEVID_NONE,
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rk630_devs, ARRAY_SIZE(rk630_devs),
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NULL, 0, NULL);
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if (ret) {
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dev_err(rk630->dev, "failed to add MFD children: %d\n", ret);
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return ret;
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}
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for_each_child_of_node(rk630->dev->of_node, np) {
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if (!of_device_is_compatible(np, "rockchip,rk630-macphy"))
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continue;
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if (!of_device_is_available(np)) {
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continue;
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} else {
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macphy_enabled = true;
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break;
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}
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}
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if (macphy_enabled)
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rk630_macphy_enable(rk630, rate);
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else
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rk630_macphy_disable(rk630);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rk630_core_probe);
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MODULE_AUTHOR("Algea Cao <Algea.cao@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip rk630 MFD Core driver");
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MODULE_LICENSE("GPL v2");
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