/*
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* Copyright (C) 2011-2014, 2016-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __MALI_GP_H__
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#define __MALI_GP_H__
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#include "mali_osk.h"
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#include "mali_gp_job.h"
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#include "mali_hw_core.h"
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#include "regs/mali_gp_regs.h"
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struct mali_group;
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/**
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* Definition of the GP core struct
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* Used to track a GP core in the system.
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*/
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struct mali_gp_core {
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struct mali_hw_core hw_core; /**< Common for all HW cores */
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_mali_osk_irq_t *irq; /**< IRQ handler */
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};
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_mali_osk_errcode_t mali_gp_initialize(void);
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void mali_gp_terminate(void);
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struct mali_gp_core *mali_gp_create(const _mali_osk_resource_t *resource, struct mali_group *group);
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void mali_gp_delete(struct mali_gp_core *core);
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void mali_gp_stop_bus(struct mali_gp_core *core);
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_mali_osk_errcode_t mali_gp_stop_bus_wait(struct mali_gp_core *core);
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void mali_gp_reset_async(struct mali_gp_core *core);
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_mali_osk_errcode_t mali_gp_reset_wait(struct mali_gp_core *core);
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void mali_gp_hard_reset(struct mali_gp_core *core);
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_mali_osk_errcode_t mali_gp_reset(struct mali_gp_core *core);
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void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job);
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void mali_gp_resume_with_new_heap(struct mali_gp_core *core, u32 start_addr, u32 end_addr);
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u32 mali_gp_core_get_version(struct mali_gp_core *core);
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struct mali_gp_core *mali_gp_get_global_gp_core(void);
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#if MALI_STATE_TRACKING
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u32 mali_gp_dump_state(struct mali_gp_core *core, char *buf, u32 size);
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#endif
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void mali_gp_update_performance_counters(struct mali_gp_core *core, struct mali_gp_job *job);
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MALI_STATIC_INLINE const char *mali_gp_core_description(struct mali_gp_core *core)
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{
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return core->hw_core.description;
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}
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MALI_STATIC_INLINE enum mali_interrupt_result mali_gp_get_interrupt_result(struct mali_gp_core *core)
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{
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u32 stat_used = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_STAT) &
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MALIGP2_REG_VAL_IRQ_MASK_USED;
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if (0 == stat_used) {
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return MALI_INTERRUPT_RESULT_NONE;
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} else if ((MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST |
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MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST) == stat_used) {
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return MALI_INTERRUPT_RESULT_SUCCESS;
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} else if (MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST == stat_used) {
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return MALI_INTERRUPT_RESULT_SUCCESS_VS;
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} else if (MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST == stat_used) {
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return MALI_INTERRUPT_RESULT_SUCCESS_PLBU;
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} else if (MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM & stat_used) {
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return MALI_INTERRUPT_RESULT_OOM;
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}
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return MALI_INTERRUPT_RESULT_ERROR;
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}
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MALI_STATIC_INLINE u32 mali_gp_get_rawstat(struct mali_gp_core *core)
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{
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MALI_DEBUG_ASSERT_POINTER(core);
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return mali_hw_core_register_read(&core->hw_core,
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MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT);
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}
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MALI_STATIC_INLINE u32 mali_gp_is_active(struct mali_gp_core *core)
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{
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u32 status = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS);
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return (status & MALIGP2_REG_VAL_STATUS_MASK_ACTIVE) ? MALI_TRUE : MALI_FALSE;
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}
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MALI_STATIC_INLINE void mali_gp_mask_all_interrupts(struct mali_gp_core *core)
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{
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_NONE);
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}
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MALI_STATIC_INLINE void mali_gp_enable_interrupts(struct mali_gp_core *core, enum mali_interrupt_result exceptions)
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{
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/* Enable all interrupts, except those specified in exceptions */
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u32 value;
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if (MALI_INTERRUPT_RESULT_SUCCESS_VS == exceptions) {
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/* Enable all used except VS complete */
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value = MALIGP2_REG_VAL_IRQ_MASK_USED &
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~MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST;
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} else {
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MALI_DEBUG_ASSERT(MALI_INTERRUPT_RESULT_SUCCESS_PLBU ==
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exceptions);
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/* Enable all used except PLBU complete */
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value = MALIGP2_REG_VAL_IRQ_MASK_USED &
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~MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST;
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}
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mali_hw_core_register_write(&core->hw_core,
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MALIGP2_REG_ADDR_MGMT_INT_MASK,
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value);
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}
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MALI_STATIC_INLINE u32 mali_gp_read_plbu_alloc_start_addr(struct mali_gp_core *core)
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{
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return mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR);
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}
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#endif /* __MALI_GP_H__ */
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