/*
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* Copyright (C) 2010-2012, 2014, 2016-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/mali/mali_utgard.h>
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#include "mali_kernel_common.h"
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#include "mali_scheduler.h"
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#include "mali_dvfs_policy.h"
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#include "mali_osk_mali.h"
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#include "mali_osk_profiling.h"
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#define CLOCK_TUNING_TIME_DEBUG 0
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#define MAX_PERFORMANCE_VALUE 256
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#define MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(percent) ((int) ((percent)*(MAX_PERFORMANCE_VALUE)/100.0 + 0.5))
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/** The max fps the same as display vsync default 60, can set by module insert parameter */
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int mali_max_system_fps = 60;
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/** A lower limit on their desired FPS default 58, can set by module insert parameter */
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int mali_desired_fps = 58;
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static int mali_fps_step1 = 0;
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static int mali_fps_step2 = 0;
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static int clock_step = -1;
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static int cur_clk_step = -1;
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static struct mali_gpu_clock *gpu_clk = NULL;
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/*Function prototype */
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static int (*mali_gpu_set_freq)(int) = NULL;
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static int (*mali_gpu_get_freq)(void) = NULL;
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static mali_bool mali_dvfs_enabled = MALI_FALSE;
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#define NUMBER_OF_NANOSECONDS_PER_SECOND 1000000000ULL
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static u32 calculate_window_render_fps(u64 time_period)
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{
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u32 max_window_number;
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u64 tmp;
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u64 max = time_period;
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u32 leading_zeroes;
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u32 shift_val;
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u32 time_period_shift;
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u32 max_window_number_shift;
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u32 ret_val;
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max_window_number = mali_session_max_window_num();
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/* To avoid float division, extend the dividend to ns unit */
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tmp = (u64)max_window_number * NUMBER_OF_NANOSECONDS_PER_SECOND;
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if (tmp > time_period) {
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max = tmp;
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}
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/*
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* We may have 64-bit values, a dividend or a divisor or both
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* To avoid dependencies to a 64-bit divider, we shift down the two values
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* equally first.
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*/
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leading_zeroes = _mali_osk_clz((u32)(max >> 32));
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shift_val = 32 - leading_zeroes;
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time_period_shift = (u32)(time_period >> shift_val);
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max_window_number_shift = (u32)(tmp >> shift_val);
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ret_val = max_window_number_shift / time_period_shift;
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return ret_val;
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}
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static bool mali_pickup_closest_avail_clock(int target_clock_mhz, mali_bool pick_clock_up)
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{
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int i = 0;
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bool clock_changed = false;
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/* Round up the closest available frequency step for target_clock_hz */
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for (i = 0; i < gpu_clk->num_of_steps; i++) {
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/* Find the first item > target_clock_hz */
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if (((int)(gpu_clk->item[i].clock) - target_clock_mhz) > 0) {
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break;
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}
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}
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/* If the target clock greater than the maximum clock just pick the maximum one*/
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if (i == gpu_clk->num_of_steps) {
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i = gpu_clk->num_of_steps - 1;
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} else {
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if ((!pick_clock_up) && (i > 0)) {
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i = i - 1;
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}
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}
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clock_step = i;
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if (cur_clk_step != clock_step) {
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clock_changed = true;
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}
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return clock_changed;
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}
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void mali_dvfs_policy_realize(struct mali_gpu_utilization_data *data, u64 time_period)
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{
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int under_perform_boundary_value = 0;
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int over_perform_boundary_value = 0;
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int current_fps = 0;
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int current_gpu_util = 0;
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bool clock_changed = false;
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#if CLOCK_TUNING_TIME_DEBUG
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struct timeval start;
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struct timeval stop;
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unsigned int elapse_time;
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do_gettimeofday(&start);
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#endif
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u32 window_render_fps;
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if (NULL == gpu_clk) {
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MALI_DEBUG_PRINT(2, ("Enable DVFS but patform doesn't Support freq change. \n"));
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return;
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}
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window_render_fps = calculate_window_render_fps(time_period);
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current_fps = window_render_fps;
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current_gpu_util = data->utilization_gpu;
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/* Get the specific under_perform_boundary_value and over_perform_boundary_value */
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if ((mali_desired_fps <= current_fps) && (current_fps < mali_max_system_fps)) {
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under_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(90);
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over_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(70);
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} else if ((mali_fps_step1 <= current_fps) && (current_fps < mali_desired_fps)) {
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under_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(55);
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over_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(35);
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} else if ((mali_fps_step2 <= current_fps) && (current_fps < mali_fps_step1)) {
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under_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(70);
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over_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(50);
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} else {
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under_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(55);
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over_perform_boundary_value = MALI_PERCENTAGE_TO_UTILIZATION_FRACTION(35);
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}
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MALI_DEBUG_PRINT(5, ("Using ARM power policy: gpu util = %d \n", current_gpu_util));
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MALI_DEBUG_PRINT(5, ("Using ARM power policy: under_perform = %d, over_perform = %d \n", under_perform_boundary_value, over_perform_boundary_value));
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MALI_DEBUG_PRINT(5, ("Using ARM power policy: render fps = %d, pressure render fps = %d \n", current_fps, window_render_fps));
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/* Get current clock value */
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cur_clk_step = mali_gpu_get_freq();
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/* Consider offscreen */
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if (0 == current_fps) {
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/* GP or PP under perform, need to give full power */
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if (current_gpu_util > over_perform_boundary_value) {
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if (cur_clk_step != gpu_clk->num_of_steps - 1) {
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clock_changed = true;
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clock_step = gpu_clk->num_of_steps - 1;
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}
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}
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/* If GPU is idle, use lowest power */
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if (0 == current_gpu_util) {
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if (cur_clk_step != 0) {
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clock_changed = true;
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clock_step = 0;
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}
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}
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goto real_setting;
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}
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/* 2. Calculate target clock if the GPU clock can be tuned */
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if (-1 != cur_clk_step) {
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int target_clk_mhz = -1;
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mali_bool pick_clock_up = MALI_TRUE;
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if (current_gpu_util > under_perform_boundary_value) {
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/* when under perform, need to consider the fps part */
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target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util * mali_desired_fps / under_perform_boundary_value / current_fps;
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pick_clock_up = MALI_TRUE;
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} else if (current_gpu_util < over_perform_boundary_value) {
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/* when over perform, did't need to consider fps, system didn't want to reach desired fps */
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target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util / under_perform_boundary_value;
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pick_clock_up = MALI_FALSE;
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}
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if (-1 != target_clk_mhz) {
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clock_changed = mali_pickup_closest_avail_clock(target_clk_mhz, pick_clock_up);
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}
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}
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real_setting:
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if (clock_changed) {
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mali_gpu_set_freq(clock_step);
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_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
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MALI_PROFILING_EVENT_CHANNEL_GPU |
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MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
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gpu_clk->item[clock_step].clock,
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gpu_clk->item[clock_step].vol / 1000,
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0, 0, 0);
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}
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#if CLOCK_TUNING_TIME_DEBUG
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do_gettimeofday(&stop);
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elapse_time = timeval_to_ns(&stop) - timeval_to_ns(&start);
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MALI_DEBUG_PRINT(2, ("Using ARM power policy: eclapse time = %d\n", elapse_time));
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#endif
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}
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_mali_osk_errcode_t mali_dvfs_policy_init(void)
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{
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_mali_osk_device_data data;
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_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
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if (_MALI_OSK_ERR_OK == _mali_osk_device_data_get(&data)) {
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if ((NULL != data.get_clock_info) && (NULL != data.set_freq) && (NULL != data.get_freq)) {
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MALI_DEBUG_PRINT(2, ("Mali DVFS init: using arm dvfs policy \n"));
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mali_fps_step1 = mali_max_system_fps / 3;
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mali_fps_step2 = mali_max_system_fps / 5;
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data.get_clock_info(&gpu_clk);
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if (gpu_clk != NULL) {
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#ifdef DEBUG
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int i;
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for (i = 0; i < gpu_clk->num_of_steps; i++) {
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MALI_DEBUG_PRINT(5, ("mali gpu clock info: step%d clock(%d)Hz,vol(%d) \n",
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i, gpu_clk->item[i].clock, gpu_clk->item[i].vol));
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}
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#endif
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} else {
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MALI_DEBUG_PRINT(2, ("Mali DVFS init: platform didn't define enough info for ddk to do DVFS \n"));
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}
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mali_gpu_get_freq = data.get_freq;
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mali_gpu_set_freq = data.set_freq;
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if ((NULL != gpu_clk) && (gpu_clk->num_of_steps > 0)
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&& (NULL != mali_gpu_get_freq) && (NULL != mali_gpu_set_freq)) {
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mali_dvfs_enabled = MALI_TRUE;
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}
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} else {
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MALI_DEBUG_PRINT(2, ("Mali DVFS init: platform function callback incomplete, need check mali_gpu_device_data in platform .\n"));
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}
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} else {
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err = _MALI_OSK_ERR_FAULT;
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MALI_DEBUG_PRINT(2, ("Mali DVFS init: get platform data error .\n"));
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}
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return err;
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}
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/*
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* Always give full power when start a new period,
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* if mali dvfs enabled, for performance consideration
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*/
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void mali_dvfs_policy_new_period(void)
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{
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/* Always give full power when start a new period */
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unsigned int cur_clk_step = 0;
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cur_clk_step = mali_gpu_get_freq();
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if (cur_clk_step != (gpu_clk->num_of_steps - 1)) {
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mali_gpu_set_freq(gpu_clk->num_of_steps - 1);
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_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
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MALI_PROFILING_EVENT_CHANNEL_GPU |
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MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, gpu_clk->item[gpu_clk->num_of_steps - 1].clock,
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gpu_clk->item[gpu_clk->num_of_steps - 1].vol / 1000, 0, 0, 0);
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}
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}
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mali_bool mali_dvfs_policy_enabled(void)
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{
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return mali_dvfs_enabled;
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}
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#if defined(CONFIG_MALI400_PROFILING)
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void mali_get_current_gpu_clk_item(struct mali_gpu_clk_item *clk_item)
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{
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if (mali_platform_device != NULL) {
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struct mali_gpu_device_data *device_data = NULL;
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device_data = (struct mali_gpu_device_data *)mali_platform_device->dev.platform_data;
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if ((NULL != device_data->get_clock_info) && (NULL != device_data->get_freq)) {
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int cur_clk_step = device_data->get_freq();
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struct mali_gpu_clock *mali_gpu_clk = NULL;
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device_data->get_clock_info(&mali_gpu_clk);
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clk_item->clock = mali_gpu_clk->item[cur_clk_step].clock;
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clk_item->vol = mali_gpu_clk->item[cur_clk_step].vol;
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} else {
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MALI_DEBUG_PRINT(2, ("Mali GPU Utilization: platform function callback incomplete, need check mali_gpu_device_data in platform .\n"));
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}
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}
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}
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#endif
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