/*
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* SH4 CPU-specific DMA definitions, used by both DMA drivers
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef CPU_DMA_REGISTER_H
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#define CPU_DMA_REGISTER_H
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/* SH7751/7760/7780 DMA IRQ sources */
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#ifdef CONFIG_CPU_SH4A
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#define DMAOR_INIT DMAOR_DME
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#if defined(CONFIG_CPU_SUBTYPE_SH7343)
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
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defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7724) || \
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defined(CONFIG_CPU_SUBTYPE_SH7730) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0x00300000
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#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
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defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785)
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#define CHCR_TS_LOW_MASK 0x00000018
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0x00100000
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#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
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#endif
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_128BIT_BLK = 0xb,
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XMIT_SZ_256BIT_BLK = 0xc,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_128BIT] = 4, \
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[XMIT_SZ_256BIT] = 5, \
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[XMIT_SZ_128BIT_BLK] = 4, \
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[XMIT_SZ_256BIT_BLK] = 5, \
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}
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#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
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(((i) & 0xc) << CHCR_TS_HIGH_SHIFT))
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#else /* CONFIG_CPU_SH4A */
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#define DMAOR_INIT (0x8000 | DMAOR_DME)
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#define CHCR_TS_LOW_MASK 0x70
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#define CHCR_TS_LOW_SHIFT 4
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 1,
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XMIT_SZ_16BIT = 2,
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XMIT_SZ_32BIT = 3,
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XMIT_SZ_64BIT = 0,
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XMIT_SZ_256BIT = 4,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_256BIT] = 5, \
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}
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#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
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#endif /* CONFIG_CPU_SH4A */
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#endif
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