/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Derived from book3s_hv_rmhandlers.S, which is:
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*
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* Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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*/
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#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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#include <asm/tm.h>
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#include <asm/cputable.h>
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
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/*
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* Save transactional state and TM-related registers.
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* Called with:
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* - r3 pointing to the vcpu struct
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* - r4 points to the MSR with current TS bits:
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* (For HV KVM, it is VCPU_MSR ; For PR KVM, it is host MSR).
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* This can modify all checkpointed registers, but
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* restores r1, r2 before exit.
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*/
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_GLOBAL(__kvmppc_save_tm)
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mflr r0
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std r0, PPC_LR_STKOFF(r1)
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/* Turn on TM. */
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mfmsr r8
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li r0, 1
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rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
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ori r8, r8, MSR_FP
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oris r8, r8, (MSR_VEC | MSR_VSX)@h
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mtmsrd r8
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rldicl. r4, r4, 64 - MSR_TS_S_LG, 62
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beq 1f /* TM not active in guest. */
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std r1, HSTATE_SCRATCH2(r13)
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std r3, HSTATE_SCRATCH1(r13)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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BEGIN_FTR_SECTION
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/* Emulation of the treclaim instruction needs TEXASR before treclaim */
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mfspr r6, SPRN_TEXASR
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std r6, VCPU_ORIG_TEXASR(r3)
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END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
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#endif
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/* Clear the MSR RI since r1, r13 are all going to be foobar. */
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li r5, 0
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mtmsrd r5, 1
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li r3, TM_CAUSE_KVM_RESCHED
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/* All GPRs are volatile at this point. */
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TRECLAIM(R3)
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/* Temporarily store r13 and r9 so we have some regs to play with */
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SET_SCRATCH0(r13)
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GET_PACA(r13)
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std r9, PACATMSCRATCH(r13)
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ld r9, HSTATE_SCRATCH1(r13)
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/* Get a few more GPRs free. */
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std r29, VCPU_GPRS_TM(29)(r9)
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std r30, VCPU_GPRS_TM(30)(r9)
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std r31, VCPU_GPRS_TM(31)(r9)
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/* Save away PPR and DSCR soon so don't run with user values. */
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mfspr r31, SPRN_PPR
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HMT_MEDIUM
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mfspr r30, SPRN_DSCR
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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ld r29, HSTATE_DSCR(r13)
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mtspr SPRN_DSCR, r29
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#endif
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/* Save all but r9, r13 & r29-r31 */
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reg = 0
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.rept 29
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.if (reg != 9) && (reg != 13)
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std reg, VCPU_GPRS_TM(reg)(r9)
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.endif
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reg = reg + 1
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.endr
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/* ... now save r13 */
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GET_SCRATCH0(r4)
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std r4, VCPU_GPRS_TM(13)(r9)
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/* ... and save r9 */
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ld r4, PACATMSCRATCH(r13)
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std r4, VCPU_GPRS_TM(9)(r9)
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/* Reload stack pointer and TOC. */
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ld r1, HSTATE_SCRATCH2(r13)
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ld r2, PACATOC(r13)
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/* Set MSR RI now we have r1 and r13 back. */
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li r5, MSR_RI
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mtmsrd r5, 1
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/* Save away checkpinted SPRs. */
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std r31, VCPU_PPR_TM(r9)
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std r30, VCPU_DSCR_TM(r9)
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mflr r5
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mfcr r6
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mfctr r7
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mfspr r8, SPRN_AMR
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mfspr r10, SPRN_TAR
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mfxer r11
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std r5, VCPU_LR_TM(r9)
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stw r6, VCPU_CR_TM(r9)
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std r7, VCPU_CTR_TM(r9)
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std r8, VCPU_AMR_TM(r9)
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std r10, VCPU_TAR_TM(r9)
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std r11, VCPU_XER_TM(r9)
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/* Restore r12 as trap number. */
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lwz r12, VCPU_TRAP(r9)
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/* Save FP/VSX. */
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addi r3, r9, VCPU_FPRS_TM
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bl store_fp_state
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addi r3, r9, VCPU_VRS_TM
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bl store_vr_state
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mfspr r6, SPRN_VRSAVE
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stw r6, VCPU_VRSAVE_TM(r9)
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1:
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/*
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* We need to save these SPRs after the treclaim so that the software
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* error code is recorded correctly in the TEXASR. Also the user may
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* change these outside of a transaction, so they must always be
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* context switched.
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*/
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mfspr r7, SPRN_TEXASR
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std r7, VCPU_TEXASR(r9)
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11:
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mfspr r5, SPRN_TFHAR
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mfspr r6, SPRN_TFIAR
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std r5, VCPU_TFHAR(r9)
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std r6, VCPU_TFIAR(r9)
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ld r0, PPC_LR_STKOFF(r1)
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mtlr r0
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blr
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/*
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* _kvmppc_save_tm_pr() is a wrapper around __kvmppc_save_tm(), so that it can
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* be invoked from C function by PR KVM only.
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*/
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_GLOBAL(_kvmppc_save_tm_pr)
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mflr r5
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std r5, PPC_LR_STKOFF(r1)
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stdu r1, -SWITCH_FRAME_SIZE(r1)
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SAVE_NVGPRS(r1)
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/* save MSR since TM/math bits might be impacted
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* by __kvmppc_save_tm().
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*/
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mfmsr r5
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SAVE_GPR(5, r1)
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/* also save DSCR/CR/TAR so that it can be recovered later */
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mfspr r6, SPRN_DSCR
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SAVE_GPR(6, r1)
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mfcr r7
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stw r7, _CCR(r1)
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mfspr r8, SPRN_TAR
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SAVE_GPR(8, r1)
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bl __kvmppc_save_tm
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REST_GPR(8, r1)
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mtspr SPRN_TAR, r8
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ld r7, _CCR(r1)
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mtcr r7
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REST_GPR(6, r1)
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mtspr SPRN_DSCR, r6
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/* need preserve current MSR's MSR_TS bits */
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REST_GPR(5, r1)
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mfmsr r6
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rldicl r6, r6, 64 - MSR_TS_S_LG, 62
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rldimi r5, r6, MSR_TS_S_LG, 63 - MSR_TS_T_LG
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mtmsrd r5
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REST_NVGPRS(r1)
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addi r1, r1, SWITCH_FRAME_SIZE
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ld r5, PPC_LR_STKOFF(r1)
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mtlr r5
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blr
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EXPORT_SYMBOL_GPL(_kvmppc_save_tm_pr);
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/*
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* Restore transactional state and TM-related registers.
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* Called with:
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* - r3 pointing to the vcpu struct.
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* - r4 is the guest MSR with desired TS bits:
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* For HV KVM, it is VCPU_MSR
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* For PR KVM, it is provided by caller
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* This potentially modifies all checkpointed registers.
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* It restores r1, r2 from the PACA.
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*/
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_GLOBAL(__kvmppc_restore_tm)
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mflr r0
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std r0, PPC_LR_STKOFF(r1)
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/* Turn on TM/FP/VSX/VMX so we can restore them. */
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mfmsr r5
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li r6, MSR_TM >> 32
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sldi r6, r6, 32
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or r5, r5, r6
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ori r5, r5, MSR_FP
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oris r5, r5, (MSR_VEC | MSR_VSX)@h
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mtmsrd r5
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/*
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* The user may change these outside of a transaction, so they must
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* always be context switched.
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*/
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ld r5, VCPU_TFHAR(r3)
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ld r6, VCPU_TFIAR(r3)
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ld r7, VCPU_TEXASR(r3)
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mtspr SPRN_TFHAR, r5
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mtspr SPRN_TFIAR, r6
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mtspr SPRN_TEXASR, r7
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mr r5, r4
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rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
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beqlr /* TM not active in guest */
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std r1, HSTATE_SCRATCH2(r13)
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/* Make sure the failure summary is set, otherwise we'll program check
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* when we trechkpt. It's possible that this might have been not set
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* on a kvmppc_set_one_reg() call but we shouldn't let this crash the
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* host.
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*/
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oris r7, r7, (TEXASR_FS)@h
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mtspr SPRN_TEXASR, r7
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/*
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* We need to load up the checkpointed state for the guest.
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* We need to do this early as it will blow away any GPRs, VSRs and
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* some SPRs.
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*/
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mr r31, r3
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addi r3, r31, VCPU_FPRS_TM
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bl load_fp_state
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addi r3, r31, VCPU_VRS_TM
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bl load_vr_state
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mr r3, r31
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lwz r7, VCPU_VRSAVE_TM(r3)
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mtspr SPRN_VRSAVE, r7
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ld r5, VCPU_LR_TM(r3)
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lwz r6, VCPU_CR_TM(r3)
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ld r7, VCPU_CTR_TM(r3)
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ld r8, VCPU_AMR_TM(r3)
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ld r9, VCPU_TAR_TM(r3)
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ld r10, VCPU_XER_TM(r3)
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mtlr r5
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mtcr r6
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mtctr r7
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mtspr SPRN_AMR, r8
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mtspr SPRN_TAR, r9
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mtxer r10
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/*
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* Load up PPR and DSCR values but don't put them in the actual SPRs
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* till the last moment to avoid running with userspace PPR and DSCR for
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* too long.
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*/
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ld r29, VCPU_DSCR_TM(r3)
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ld r30, VCPU_PPR_TM(r3)
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std r2, PACATMSCRATCH(r13) /* Save TOC */
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/* Clear the MSR RI since r1, r13 are all going to be foobar. */
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li r5, 0
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mtmsrd r5, 1
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/* Load GPRs r0-r28 */
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reg = 0
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.rept 29
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ld reg, VCPU_GPRS_TM(reg)(r31)
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reg = reg + 1
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.endr
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mtspr SPRN_DSCR, r29
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mtspr SPRN_PPR, r30
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/* Load final GPRs */
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ld 29, VCPU_GPRS_TM(29)(r31)
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ld 30, VCPU_GPRS_TM(30)(r31)
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ld 31, VCPU_GPRS_TM(31)(r31)
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/* TM checkpointed state is now setup. All GPRs are now volatile. */
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TRECHKPT
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/* Now let's get back the state we need. */
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HMT_MEDIUM
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GET_PACA(r13)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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ld r29, HSTATE_DSCR(r13)
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mtspr SPRN_DSCR, r29
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#endif
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ld r1, HSTATE_SCRATCH2(r13)
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ld r2, PACATMSCRATCH(r13)
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/* Set the MSR RI since we have our registers back. */
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li r5, MSR_RI
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mtmsrd r5, 1
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ld r0, PPC_LR_STKOFF(r1)
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mtlr r0
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blr
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/*
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* _kvmppc_restore_tm_pr() is a wrapper around __kvmppc_restore_tm(), so that it
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* can be invoked from C function by PR KVM only.
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*/
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_GLOBAL(_kvmppc_restore_tm_pr)
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mflr r5
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std r5, PPC_LR_STKOFF(r1)
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stdu r1, -SWITCH_FRAME_SIZE(r1)
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SAVE_NVGPRS(r1)
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/* save MSR to avoid TM/math bits change */
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mfmsr r5
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SAVE_GPR(5, r1)
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/* also save DSCR/CR/TAR so that it can be recovered later */
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mfspr r6, SPRN_DSCR
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SAVE_GPR(6, r1)
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mfcr r7
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stw r7, _CCR(r1)
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mfspr r8, SPRN_TAR
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SAVE_GPR(8, r1)
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bl __kvmppc_restore_tm
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REST_GPR(8, r1)
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mtspr SPRN_TAR, r8
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ld r7, _CCR(r1)
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mtcr r7
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REST_GPR(6, r1)
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mtspr SPRN_DSCR, r6
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/* need preserve current MSR's MSR_TS bits */
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REST_GPR(5, r1)
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mfmsr r6
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rldicl r6, r6, 64 - MSR_TS_S_LG, 62
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rldimi r5, r6, MSR_TS_S_LG, 63 - MSR_TS_T_LG
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mtmsrd r5
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REST_NVGPRS(r1)
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addi r1, r1, SWITCH_FRAME_SIZE
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ld r5, PPC_LR_STKOFF(r1)
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mtlr r5
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blr
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EXPORT_SYMBOL_GPL(_kvmppc_restore_tm_pr);
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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