/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_TLB_H
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#define __ASM_TLB_H
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#include <asm/cpu-features.h>
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#include <asm/mipsregs.h>
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/*
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* MIPS doesn't need any special per-pte or per-vma handling, except
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* we need to flush cache for area to be unmapped.
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*/
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#define tlb_start_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_cache_range(vma, vma->vm_start, vma->vm_end); \
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} while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
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/*
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* .. because we flush the whole mm when it fills up.
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*/
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#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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#define _UNIQUE_ENTRYHI(base, idx) \
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(((base) + ((idx) << (PAGE_SHIFT + 1))) | \
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(cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
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#define UNIQUE_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG0, idx)
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#define UNIQUE_GUEST_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG1, idx)
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static inline unsigned int num_wired_entries(void)
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{
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unsigned int wired = read_c0_wired();
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if (cpu_has_mips_r6)
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wired &= MIPSR6_WIRED_WIRED;
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return wired;
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}
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#include <asm-generic/tlb.h>
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#endif /* __ASM_TLB_H */
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