/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_BRIDGE_H_
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#define _ASM_NLM_BRIDGE_H_
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#define BRIDGE_DRAM_0_BAR 0
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#define BRIDGE_DRAM_1_BAR 1
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#define BRIDGE_DRAM_2_BAR 2
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#define BRIDGE_DRAM_3_BAR 3
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#define BRIDGE_DRAM_4_BAR 4
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#define BRIDGE_DRAM_5_BAR 5
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#define BRIDGE_DRAM_6_BAR 6
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#define BRIDGE_DRAM_7_BAR 7
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#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8
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#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9
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#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10
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#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11
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#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12
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#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13
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#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14
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#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15
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#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16
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#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17
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#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18
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#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19
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#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20
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#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21
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#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22
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#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23
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#define BRIDGE_CFG_BAR 24
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#define BRIDGE_PHNX_IO_BAR 25
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#define BRIDGE_FLASH_BAR 26
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#define BRIDGE_SRAM_BAR 27
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#define BRIDGE_HTMEM_BAR 28
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#define BRIDGE_HTINT_BAR 29
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#define BRIDGE_HTPIC_BAR 30
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#define BRIDGE_HTSM_BAR 31
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#define BRIDGE_HTIO_BAR 32
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#define BRIDGE_HTCFG_BAR 33
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#define BRIDGE_PCIXCFG_BAR 34
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#define BRIDGE_PCIXMEM_BAR 35
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#define BRIDGE_PCIXIO_BAR 36
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#define BRIDGE_DEVICE_MASK 37
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#define BRIDGE_AERR_INTR_LOG1 38
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#define BRIDGE_AERR_INTR_LOG2 39
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#define BRIDGE_AERR_INTR_LOG3 40
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#define BRIDGE_AERR_DEV_STAT 41
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#define BRIDGE_AERR1_LOG1 42
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#define BRIDGE_AERR1_LOG2 43
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#define BRIDGE_AERR1_LOG3 44
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#define BRIDGE_AERR1_DEV_STAT 45
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#define BRIDGE_AERR_INTR_EN 46
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#define BRIDGE_AERR_UPG 47
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#define BRIDGE_AERR_CLEAR 48
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#define BRIDGE_AERR1_CLEAR 49
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#define BRIDGE_SBE_COUNTS 50
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#define BRIDGE_DBE_COUNTS 51
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#define BRIDGE_BITERR_INT_EN 52
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#define BRIDGE_SYS2IO_CREDITS 53
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#define BRIDGE_EVNT_CNT_CTRL1 54
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#define BRIDGE_EVNT_COUNTER1 55
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#define BRIDGE_EVNT_CNT_CTRL2 56
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#define BRIDGE_EVNT_COUNTER2 57
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#define BRIDGE_RESERVED1 58
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#define BRIDGE_DEFEATURE 59
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#define BRIDGE_SCRATCH0 60
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#define BRIDGE_SCRATCH1 61
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#define BRIDGE_SCRATCH2 62
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#define BRIDGE_SCRATCH3 63
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#endif
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