/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NLM_HAL_XLP_H
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#define _NLM_HAL_XLP_H
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#define PIC_UART_0_IRQ 17
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#define PIC_UART_1_IRQ 18
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#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
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#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
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#define PIC_EHCI_0_IRQ 23
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#define PIC_EHCI_1_IRQ 24
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#define PIC_OHCI_0_IRQ 25
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#define PIC_OHCI_1_IRQ 26
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#define PIC_OHCI_2_IRQ 27
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#define PIC_OHCI_3_IRQ 28
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#define PIC_2XX_XHCI_0_IRQ 23
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#define PIC_2XX_XHCI_1_IRQ 24
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#define PIC_2XX_XHCI_2_IRQ 25
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#define PIC_9XX_XHCI_0_IRQ 23
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#define PIC_9XX_XHCI_1_IRQ 24
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#define PIC_9XX_XHCI_2_IRQ 25
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#define PIC_MMC_IRQ 29
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#define PIC_I2C_0_IRQ 30
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#define PIC_I2C_1_IRQ 31
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#define PIC_I2C_2_IRQ 32
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#define PIC_I2C_3_IRQ 33
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#define PIC_SPI_IRQ 34
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#define PIC_NAND_IRQ 37
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#define PIC_SATA_IRQ 38
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#define PIC_GPIO_IRQ 39
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#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
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#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
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/* MSI-X with second link-level dispatch */
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#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
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#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
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/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
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#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */
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#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */
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#define NLM_PIC_INDIRECT_VEC_BASE 512
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#define NLM_GPIO_VEC_BASE 768
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#define PIC_IRQ_BASE 8
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#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
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#define PIC_IRT_LAST_IRQ 63
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#ifndef __ASSEMBLY__
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/* SMP support functions */
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void xlp_boot_core0_siblings(void);
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void xlp_wakeup_secondary_cpus(void);
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void xlp_mmu_init(void);
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void nlm_hal_init(void);
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int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
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struct pci_dev;
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int xlp_socdev_to_node(const struct pci_dev *dev);
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/* Device tree related */
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void xlp_early_init_devtree(void);
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void *xlp_dt_init(void *fdtp);
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static inline int cpu_is_xlpii(void)
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{
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int chip = read_c0_prid() & PRID_IMP_MASK;
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return chip == PRID_IMP_NETLOGIC_XLP2XX ||
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chip == PRID_IMP_NETLOGIC_XLP9XX ||
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chip == PRID_IMP_NETLOGIC_XLP5XX;
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}
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static inline int cpu_is_xlp9xx(void)
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{
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int chip = read_c0_prid() & PRID_IMP_MASK;
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return chip == PRID_IMP_NETLOGIC_XLP9XX ||
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chip == PRID_IMP_NETLOGIC_XLP5XX;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_NLM_XLP_H */
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