/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_CPUCONTROL_H__
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#define __NLM_HAL_CPUCONTROL_H__
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#define CPU_BLOCKID_IFU 0
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#define CPU_BLOCKID_ICU 1
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#define CPU_BLOCKID_IEU 2
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#define CPU_BLOCKID_LSU 3
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#define CPU_BLOCKID_MMU 4
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#define CPU_BLOCKID_PRF 5
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#define CPU_BLOCKID_SCH 7
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#define CPU_BLOCKID_SCU 8
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#define CPU_BLOCKID_FPU 9
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#define CPU_BLOCKID_MAP 10
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#define IFU_BRUB_RESERVE 0x007
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#define ICU_DEFEATURE 0x100
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#define LSU_DEFEATURE 0x304
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#define LSU_DEBUG_ADDR 0x305
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#define LSU_DEBUG_DATA0 0x306
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#define LSU_CERRLOG_REGID 0x309
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#define SCHED_DEFEATURE 0x700
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/* Offsets of interest from the 'MAP' Block */
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#define MAP_THREADMODE 0x00
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#define MAP_EXT_EBASE_ENABLE 0x04
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#define MAP_CCDI_CONFIG 0x08
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#define MAP_THRD0_CCDI_STATUS 0x0c
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#define MAP_THRD1_CCDI_STATUS 0x10
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#define MAP_THRD2_CCDI_STATUS 0x14
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#define MAP_THRD3_CCDI_STATUS 0x18
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#define MAP_THRD0_DEBUG_MODE 0x1c
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#define MAP_THRD1_DEBUG_MODE 0x20
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#define MAP_THRD2_DEBUG_MODE 0x24
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#define MAP_THRD3_DEBUG_MODE 0x28
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#define MAP_MISC_STATE 0x60
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#define MAP_DEBUG_READ_CTL 0x64
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#define MAP_DEBUG_READ_REG0 0x68
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#define MAP_DEBUG_READ_REG1 0x6c
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#define MMU_SETUP 0x400
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#define MMU_LFSRSEED 0x401
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#define MMU_HPW_NUM_PAGE_LVL 0x410
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#define MMU_PGWKR_PGDBASE 0x411
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#define MMU_PGWKR_PGDSHFT 0x412
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#define MMU_PGWKR_PGDMASK 0x413
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#define MMU_PGWKR_PUDSHFT 0x414
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#define MMU_PGWKR_PUDMASK 0x415
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#define MMU_PGWKR_PMDSHFT 0x416
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#define MMU_PGWKR_PMDMASK 0x417
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#define MMU_PGWKR_PTESHFT 0x418
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#define MMU_PGWKR_PTEMASK 0x419
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#endif /* __NLM_CPUCONTROL_H__ */
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