/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2015 Imagination Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H
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#define __ASM_MIPS_BOARDS_SEAD3_ADDR_H
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/*
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* Target #0 Register Decode
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*/
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#define SEAD3_SD_SPDCNF 0xbb000040
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#define SEAD3_SD_SPADDR 0xbb000048
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#define SEAD3_SD_DATA 0xbb000050
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/*
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* Target #1 Register Decode
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*/
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#define SEAD3_CFG 0xbb100110
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#define SEAD3_GIC_BASE_ADDRESS 0xbb1c0000
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#define SEAD3_SHARED_SECTION 0xbb1c0000
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#define SEAD3_VPE_LOCAL_SECTION 0xbb1c8000
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#define SEAD3_VPE_OTHER_SECTION 0xbb1cc000
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#define SEAD3_USER_MODE_VISIBLE_SECTION 0xbb1d0000
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/*
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* Target #3 Register Decode
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*/
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#define SEAD3_USB_HS_BASE 0xbb200000
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#define SEAD3_USB_HS_IDENTIFICATION_REGS 0xbb200000
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#define SEAD3_USB_HS_CAPABILITY_REGS 0xbb200100
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#define SEAD3_USB_HS_OPERATIONAL_REGS 0xbb200140
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#define SEAD3_RESERVED 0xbe800000
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/*
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* Target #3 Register Decode
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*/
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#define SEAD3_SRAM 0xbe000000
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#define SEAD3_OPTIONAL_SRAM 0xbe400000
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#define SEAD3_FPGA 0xbf000000
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#define SEAD3_PI_PIC32_USB_STATUS 0xbf000060
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#define SEAD3_PI_PIC32_USB_STATUS_IO_RDY (1 << 0)
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#define SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1)
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#define SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT (1 << 2)
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#define SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT (1 << 3)
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#define SEAD3_PI_SOFT_ENDIAN 0xbf000070
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#define SEAD3_CPLD_P_SWITCH 0xbf000200
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#define SEAD3_CPLD_F_SWITCH 0xbf000208
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#define SEAD3_CPLD_P_LED 0xbf000210
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#define SEAD3_CPLD_F_LED 0xbf000218
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#define SEAD3_NEWSC_LIVE 0xbf000220
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#define SEAD3_NEWSC_REG 0xbf000228
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#define SEAD3_NEWSC_CTRL 0xbf000230
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#define SEAD3_LCD_CONTROL 0xbf000400
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#define SEAD3_LCD_DATA 0xbf000408
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#define SEAD3_CPLD_LCD_STATUS 0xbf000410
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#define SEAD3_CPLD_LCD_DATA 0xbf000418
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#define SEAD3_CPLD_PI_DEVRST 0xbf000480
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#define SEAD3_CPLD_PI_DEVRST_IC32_RST (1 << 0)
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#define SEAD3_RESERVED_0 0xbf000500
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#define SEAD3_PIC32_REGISTERS 0xbf000600
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#define SEAD3_RESERVED_1 0xbf000700
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#define SEAD3_UART_CH_0 0xbf000800
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#define SEAD3_UART_CH_1 0xbf000900
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#define SEAD3_RESERVED_2 0xbf000a00
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#define SEAD3_ETHERNET 0xbf010000
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#define SEAD3_RESERVED_3 0xbf020000
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#define SEAD3_USER_EXPANSION 0xbf400000
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#define SEAD3_RESERVED_4 0xbf800000
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#define SEAD3_BOOT_FLASH_EXTENSION 0xbfa00000
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#define SEAD3_BOOT_FLASH 0xbfc00000
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#define SEAD3_REVISION_REGISTER 0xbfc00010
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#endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H */
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