/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
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/*
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* Sibyte are MIPS64 processors wired to a specific configuration
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*/
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#define cpu_has_watch 1
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#define cpu_has_mips16 0
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#define cpu_has_mips16e2 0
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 1
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#define cpu_has_mcheck 1
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#define cpu_has_ejtag 1
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#define cpu_has_llsc 1
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#define cpu_has_vtag_icache 1
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#define cpu_has_dc_aliases 0
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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#define cpu_icache_snoops_remote_store 0
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#define cpu_has_nofpuex 0
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#define cpu_has_64bits 1
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 1
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#define cpu_has_mips64r2 0
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#define cpu_has_inclusive_pcaches 0
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#define cpu_scache_line_size() 32
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#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */
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