/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* GPIO register definition.
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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* Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
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* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
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*/
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#ifndef _RC32434_GPIO_H_
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#define _RC32434_GPIO_H_
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struct rb532_gpio_reg {
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u32 gpiofunc; /* GPIO Function Register
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* gpiofunc[x]==0 bit = gpio
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* func[x]==1 bit = altfunc
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*/
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u32 gpiocfg; /* GPIO Configuration Register
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* gpiocfg[x]==0 bit = input
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* gpiocfg[x]==1 bit = output
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*/
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u32 gpiod; /* GPIO Data Register
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* gpiod[x] read/write gpio pinX status
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*/
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u32 gpioilevel; /* GPIO Interrupt Status Register
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* interrupt level (see gpioistat)
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*/
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u32 gpioistat; /* Gpio Interrupt Status Register
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* istat[x] = (gpiod[x] == level[x])
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* cleared in ISR (STICKY bits)
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*/
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u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
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};
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/* UART GPIO signals */
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#define RC32434_UART0_SOUT (1 << 0)
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#define RC32434_UART0_SIN (1 << 1)
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#define RC32434_UART0_RTS (1 << 2)
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#define RC32434_UART0_CTS (1 << 3)
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/* M & P bus GPIO signals */
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#define RC32434_MP_BIT_22 (1 << 4)
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#define RC32434_MP_BIT_23 (1 << 5)
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#define RC32434_MP_BIT_24 (1 << 6)
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#define RC32434_MP_BIT_25 (1 << 7)
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/* CPU GPIO signals */
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#define RC32434_CPU_GPIO (1 << 8)
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/* Reserved GPIO signals */
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#define RC32434_AF_SPARE_6 (1 << 9)
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#define RC32434_AF_SPARE_4 (1 << 10)
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#define RC32434_AF_SPARE_3 (1 << 11)
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#define RC32434_AF_SPARE_2 (1 << 12)
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/* PCI messaging unit */
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#define RC32434_PCI_MSU_GPIO (1 << 13)
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/* NAND GPIO signals */
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#define GPIO_RDY 8
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#define GPIO_WPX 9
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#define GPIO_ALE 10
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#define GPIO_CLE 11
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/* Compact Flash GPIO pin */
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#define CF_GPIO_NUM 13
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/* S1 button GPIO (shared with UART0_SIN) */
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#define GPIO_BTN_S1 1
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extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
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extern void rb532_gpio_set_istat(int bit, unsigned gpio);
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extern void rb532_gpio_set_func(unsigned gpio);
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#endif /* _RC32434_GPIO_H_ */
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