/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* DMA register definition.
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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*/
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#ifndef __ASM_RC32434_DMA_H
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#define __ASM_RC32434_DMA_H
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#include <asm/mach-rc32434/rb.h>
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#define DMA0_BASE_ADDR 0x18040000
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/*
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* DMA descriptor (in physical memory).
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*/
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struct dma_desc {
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u32 control; /* Control. use DMAD_* */
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u32 ca; /* Current Address. */
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u32 devcs; /* Device control and status. */
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u32 link; /* Next descriptor in chain. */
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};
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#define DMA_DESC_SIZ sizeof(struct dma_desc)
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#define DMA_DESC_COUNT_BIT 0
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#define DMA_DESC_COUNT_MSK 0x0003ffff
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#define DMA_DESC_DS_BIT 20
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#define DMA_DESC_DS_MSK 0x00300000
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#define DMA_DESC_DEV_CMD_BIT 22
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#define DMA_DESC_DEV_CMD_MSK 0x01c00000
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/* DMA command sizes */
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#define DMA_DESC_DEV_CMD_BYTE 0
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#define DMA_DESC_DEV_CMD_HLF_WD 1
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#define DMA_DESC_DEV_CMD_WORD 2
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#define DMA_DESC_DEV_CMD_2WORDS 3
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#define DMA_DESC_DEV_CMD_4WORDS 4
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#define DMA_DESC_DEV_CMD_6WORDS 5
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#define DMA_DESC_DEV_CMD_8WORDS 6
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#define DMA_DESC_DEV_CMD_16WORDS 7
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/* DMA descriptors interrupts */
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#define DMA_DESC_COF (1 << 25) /* Chain on finished */
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#define DMA_DESC_COD (1 << 26) /* Chain on done */
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#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
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#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
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#define DMA_DESC_TERM (1 << 29) /* Terminated */
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#define DMA_DESC_DONE (1 << 30) /* Done */
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#define DMA_DESC_FINI (1 << 31) /* Finished */
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/*
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* DMA register (within Internal Register Map).
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*/
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struct dma_reg {
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u32 dmac; /* Control. */
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u32 dmas; /* Status. */
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u32 dmasm; /* Mask. */
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u32 dmadptr; /* Descriptor pointer. */
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u32 dmandptr; /* Next descriptor pointer. */
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};
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/* DMA channels specific registers */
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#define DMA_CHAN_RUN_BIT (1 << 0)
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#define DMA_CHAN_DONE_BIT (1 << 1)
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#define DMA_CHAN_MODE_BIT (1 << 2)
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#define DMA_CHAN_MODE_MSK 0x0000000c
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#define DMA_CHAN_MODE_AUTO 0
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#define DMA_CHAN_MODE_BURST 1
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#define DMA_CHAN_MODE_XFRT 2
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#define DMA_CHAN_MODE_RSVD 3
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#define DMA_CHAN_ACT_BIT (1 << 4)
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/* DMA status registers */
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#define DMA_STAT_FINI (1 << 0)
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#define DMA_STAT_DONE (1 << 1)
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#define DMA_STAT_CHAIN (1 << 2)
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#define DMA_STAT_ERR (1 << 3)
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#define DMA_STAT_HALT (1 << 4)
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/*
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* DMA channel definitions
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*/
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#define DMA_CHAN_ETH_RCV 0
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#define DMA_CHAN_ETH_XMT 1
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#define DMA_CHAN_MEM_TO_FIFO 2
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#define DMA_CHAN_FIFO_TO_MEM 3
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#define DMA_CHAN_PCI_TO_MEM 4
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#define DMA_CHAN_MEM_TO_PCI 5
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#define DMA_CHAN_COUNT 6
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struct dma_channel {
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struct dma_reg ch[DMA_CHAN_COUNT];
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};
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#endif /* __ASM_RC32434_DMA_H */
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