/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* The header file of cs5536 south bridge.
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*
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* Copyright (C) 2007 Lemote, Inc.
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* Author : jlliu <liujl@lemote.com>
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*/
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#ifndef _CS5536_H
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#define _CS5536_H
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#include <linux/types.h>
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extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
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extern void _wrmsr(u32 msr, u32 hi, u32 lo);
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/*
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* MSR module base
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*/
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#define CS5536_SB_MSR_BASE (0x00000000)
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#define CS5536_GLIU_MSR_BASE (0x10000000)
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#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
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#define CS5536_USB_MSR_BASE (0x40000000)
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#define CS5536_IDE_MSR_BASE (0x60000000)
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#define CS5536_DIVIL_MSR_BASE (0x80000000)
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#define CS5536_ACC_MSR_BASE (0xa0000000)
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#define CS5536_UNUSED_MSR_BASE (0xc0000000)
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#define CS5536_GLCP_MSR_BASE (0xe0000000)
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#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
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#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
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#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
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#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
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#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
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#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
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#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
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#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
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#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
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/*
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* BAR SPACE OF VIRTUAL PCI :
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* range for pci probe use, length is the actual size.
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*/
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/* IO space for all DIVIL modules */
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#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
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#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
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#define CS5536_SMB_RANGE 0xfffffff8
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#define CS5536_SMB_LENGTH 0x08
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#define CS5536_GPIO_RANGE 0xffffff00
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#define CS5536_GPIO_LENGTH 0x100
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#define CS5536_MFGPT_RANGE 0xffffffc0
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#define CS5536_MFGPT_LENGTH 0x40
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#define CS5536_ACPI_RANGE 0xffffffe0
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#define CS5536_ACPI_LENGTH 0x20
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#define CS5536_PMS_RANGE 0xffffff80
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#define CS5536_PMS_LENGTH 0x80
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/* IO space for IDE */
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#define CS5536_IDE_RANGE 0xfffffff0
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#define CS5536_IDE_LENGTH 0x10
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/* IO space for ACC */
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#define CS5536_ACC_RANGE 0xffffff80
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#define CS5536_ACC_LENGTH 0x80
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/* MEM space for ALL USB modules */
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#define CS5536_OHCI_RANGE 0xfffff000
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#define CS5536_OHCI_LENGTH 0x1000
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#define CS5536_EHCI_RANGE 0xfffff000
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#define CS5536_EHCI_LENGTH 0x1000
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/*
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* PCI MSR ACCESS
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*/
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#define PCI_MSR_CTRL 0xF0
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#define PCI_MSR_ADDR 0xF4
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#define PCI_MSR_DATA_LO 0xF8
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#define PCI_MSR_DATA_HI 0xFC
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/**************** MSR *****************************/
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/*
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* GLIU STANDARD MSR
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*/
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#define GLIU_CAP 0x00
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#define GLIU_CONFIG 0x01
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#define GLIU_SMI 0x02
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#define GLIU_ERROR 0x03
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#define GLIU_PM 0x04
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#define GLIU_DIAG 0x05
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/*
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* GLIU SPEC. MSR
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*/
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#define GLIU_P2D_BM0 0x20
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#define GLIU_P2D_BM1 0x21
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#define GLIU_P2D_BM2 0x22
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#define GLIU_P2D_BMK0 0x23
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#define GLIU_P2D_BMK1 0x24
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#define GLIU_P2D_BM3 0x25
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#define GLIU_P2D_BM4 0x26
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#define GLIU_COH 0x80
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#define GLIU_PAE 0x81
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#define GLIU_ARB 0x82
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#define GLIU_ASMI 0x83
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#define GLIU_AERR 0x84
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#define GLIU_DEBUG 0x85
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#define GLIU_PHY_CAP 0x86
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#define GLIU_NOUT_RESP 0x87
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#define GLIU_NOUT_WDATA 0x88
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#define GLIU_WHOAMI 0x8B
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#define GLIU_SLV_DIS 0x8C
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#define GLIU_IOD_BM0 0xE0
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#define GLIU_IOD_BM1 0xE1
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#define GLIU_IOD_BM2 0xE2
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#define GLIU_IOD_BM3 0xE3
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#define GLIU_IOD_BM4 0xE4
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#define GLIU_IOD_BM5 0xE5
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#define GLIU_IOD_BM6 0xE6
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#define GLIU_IOD_BM7 0xE7
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#define GLIU_IOD_BM8 0xE8
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#define GLIU_IOD_BM9 0xE9
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#define GLIU_IOD_SC0 0xEA
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#define GLIU_IOD_SC1 0xEB
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#define GLIU_IOD_SC2 0xEC
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#define GLIU_IOD_SC3 0xED
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#define GLIU_IOD_SC4 0xEE
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#define GLIU_IOD_SC5 0xEF
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#define GLIU_IOD_SC6 0xF0
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#define GLIU_IOD_SC7 0xF1
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/*
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* SB STANDARD
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*/
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#define SB_CAP 0x00
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#define SB_CONFIG 0x01
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#define SB_SMI 0x02
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#define SB_ERROR 0x03
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#define SB_MAR_ERR_EN 0x00000001
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#define SB_TAR_ERR_EN 0x00000002
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#define SB_RSVD_BIT1 0x00000004
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#define SB_EXCEP_ERR_EN 0x00000008
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#define SB_SYSE_ERR_EN 0x00000010
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#define SB_PARE_ERR_EN 0x00000020
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#define SB_TAS_ERR_EN 0x00000040
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#define SB_MAR_ERR_FLAG 0x00010000
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#define SB_TAR_ERR_FLAG 0x00020000
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#define SB_RSVD_BIT2 0x00040000
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#define SB_EXCEP_ERR_FLAG 0x00080000
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#define SB_SYSE_ERR_FLAG 0x00100000
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#define SB_PARE_ERR_FLAG 0x00200000
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#define SB_TAS_ERR_FLAG 0x00400000
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#define SB_PM 0x04
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#define SB_DIAG 0x05
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/*
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* SB SPEC.
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*/
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#define SB_CTRL 0x10
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#define SB_R0 0x20
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#define SB_R1 0x21
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#define SB_R2 0x22
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#define SB_R3 0x23
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#define SB_R4 0x24
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#define SB_R5 0x25
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#define SB_R6 0x26
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#define SB_R7 0x27
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#define SB_R8 0x28
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#define SB_R9 0x29
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#define SB_R10 0x2A
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#define SB_R11 0x2B
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#define SB_R12 0x2C
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#define SB_R13 0x2D
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#define SB_R14 0x2E
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#define SB_R15 0x2F
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/*
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* GLCP STANDARD
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*/
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#define GLCP_CAP 0x00
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#define GLCP_CONFIG 0x01
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#define GLCP_SMI 0x02
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#define GLCP_ERROR 0x03
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#define GLCP_PM 0x04
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#define GLCP_DIAG 0x05
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/*
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* GLCP SPEC.
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*/
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#define GLCP_CLK_DIS_DELAY 0x08
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#define GLCP_PM_CLK_DISABLE 0x09
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#define GLCP_GLB_PM 0x0B
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#define GLCP_DBG_OUT 0x0C
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#define GLCP_RSVD1 0x0D
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#define GLCP_SOFT_COM 0x0E
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#define SOFT_BAR_SMB_FLAG 0x00000001
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#define SOFT_BAR_GPIO_FLAG 0x00000002
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#define SOFT_BAR_MFGPT_FLAG 0x00000004
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#define SOFT_BAR_IRQ_FLAG 0x00000008
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#define SOFT_BAR_PMS_FLAG 0x00000010
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#define SOFT_BAR_ACPI_FLAG 0x00000020
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#define SOFT_BAR_IDE_FLAG 0x00000400
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#define SOFT_BAR_ACC_FLAG 0x00000800
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#define SOFT_BAR_OHCI_FLAG 0x00001000
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#define SOFT_BAR_EHCI_FLAG 0x00002000
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#define GLCP_RSVD2 0x0F
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#define GLCP_CLK_OFF 0x10
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#define GLCP_CLK_ACTIVE 0x11
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#define GLCP_CLK_DISABLE 0x12
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#define GLCP_CLK4ACK 0x13
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#define GLCP_SYS_RST 0x14
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#define GLCP_RSVD3 0x15
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#define GLCP_DBG_CLK_CTRL 0x16
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#define GLCP_CHIP_REV_ID 0x17
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/* PIC */
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#define PIC_YSEL_LOW 0x20
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#define PIC_YSEL_LOW_USB_SHIFT 8
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#define PIC_YSEL_LOW_ACC_SHIFT 16
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#define PIC_YSEL_LOW_FLASH_SHIFT 24
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#define PIC_YSEL_HIGH 0x21
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#define PIC_ZSEL_LOW 0x22
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#define PIC_ZSEL_HIGH 0x23
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#define PIC_IRQM_PRIM 0x24
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#define PIC_IRQM_LPC 0x25
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#define PIC_XIRR_STS_LOW 0x26
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#define PIC_XIRR_STS_HIGH 0x27
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#define PCI_SHDW 0x34
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/*
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* DIVIL STANDARD
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*/
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#define DIVIL_CAP 0x00
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#define DIVIL_CONFIG 0x01
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#define DIVIL_SMI 0x02
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#define DIVIL_ERROR 0x03
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#define DIVIL_PM 0x04
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#define DIVIL_DIAG 0x05
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/*
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* DIVIL SPEC.
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*/
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#define DIVIL_LBAR_IRQ 0x08
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#define DIVIL_LBAR_KEL 0x09
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#define DIVIL_LBAR_SMB 0x0B
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#define DIVIL_LBAR_GPIO 0x0C
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#define DIVIL_LBAR_MFGPT 0x0D
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#define DIVIL_LBAR_ACPI 0x0E
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#define DIVIL_LBAR_PMS 0x0F
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#define DIVIL_LEG_IO 0x14
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#define DIVIL_BALL_OPTS 0x15
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#define DIVIL_SOFT_IRQ 0x16
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#define DIVIL_SOFT_RESET 0x17
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/* MFGPT */
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#define MFGPT_IRQ 0x28
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/*
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* IDE STANDARD
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*/
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#define IDE_CAP 0x00
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#define IDE_CONFIG 0x01
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#define IDE_SMI 0x02
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#define IDE_ERROR 0x03
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#define IDE_PM 0x04
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#define IDE_DIAG 0x05
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/*
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* IDE SPEC.
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*/
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#define IDE_IO_BAR 0x08
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#define IDE_CFG 0x10
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#define IDE_DTC 0x12
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#define IDE_CAST 0x13
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#define IDE_ETC 0x14
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#define IDE_INTERNAL_PM 0x15
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/*
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* ACC STANDARD
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*/
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#define ACC_CAP 0x00
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#define ACC_CONFIG 0x01
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#define ACC_SMI 0x02
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#define ACC_ERROR 0x03
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#define ACC_PM 0x04
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#define ACC_DIAG 0x05
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/*
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* USB STANDARD
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*/
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#define USB_CAP 0x00
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#define USB_CONFIG 0x01
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#define USB_SMI 0x02
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#define USB_ERROR 0x03
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#define USB_PM 0x04
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#define USB_DIAG 0x05
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/*
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* USB SPEC.
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*/
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#define USB_OHCI 0x08
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#define USB_EHCI 0x09
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/****************** NATIVE ***************************/
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/* GPIO : I/O SPACE; REG : 32BITS */
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#define GPIOL_OUT_VAL 0x00
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#define GPIOL_OUT_EN 0x04
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#endif /* _CS5536_H */
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