/*
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* Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
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* Engine)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Harald Koerfgen
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*/
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#ifndef __ASM_CRIME_H__
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#define __ASM_CRIME_H__
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/*
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* Address map
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*/
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#define CRIME_BASE 0x14000000 /* physical */
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struct sgi_crime {
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volatile unsigned long id;
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#define CRIME_ID_MASK 0xff
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#define CRIME_ID_IDBITS 0xf0
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#define CRIME_ID_IDVALUE 0xa0
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#define CRIME_ID_REV 0x0f
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#define CRIME_REV_PETTY 0x00
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#define CRIME_REV_11 0x11
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#define CRIME_REV_13 0x13
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#define CRIME_REV_14 0x14
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volatile unsigned long control;
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#define CRIME_CONTROL_MASK 0x3fff
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#define CRIME_CONTROL_TRITON_SYSADC 0x2000
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#define CRIME_CONTROL_CRIME_SYSADC 0x1000
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#define CRIME_CONTROL_HARD_RESET 0x0800
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#define CRIME_CONTROL_SOFT_RESET 0x0400
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#define CRIME_CONTROL_DOG_ENA 0x0200
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#define CRIME_CONTROL_ENDIANESS 0x0100
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#define CRIME_CONTROL_ENDIAN_BIG 0x0100
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#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
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#define CRIME_CONTROL_CQUEUE_HWM 0x000f
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#define CRIME_CONTROL_CQUEUE_SHFT 0
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#define CRIME_CONTROL_WBUF_HWM 0x00f0
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#define CRIME_CONTROL_WBUF_SHFT 8
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volatile unsigned long istat;
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volatile unsigned long imask;
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volatile unsigned long soft_int;
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volatile unsigned long hard_int;
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#define MACE_VID_IN1_INT BIT(0)
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#define MACE_VID_IN2_INT BIT(1)
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#define MACE_VID_OUT_INT BIT(2)
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#define MACE_ETHERNET_INT BIT(3)
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#define MACE_SUPERIO_INT BIT(4)
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#define MACE_MISC_INT BIT(5)
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#define MACE_AUDIO_INT BIT(6)
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#define MACE_PCI_BRIDGE_INT BIT(7)
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#define MACEPCI_SCSI0_INT BIT(8)
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#define MACEPCI_SCSI1_INT BIT(9)
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#define MACEPCI_SLOT0_INT BIT(10)
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#define MACEPCI_SLOT1_INT BIT(11)
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#define MACEPCI_SLOT2_INT BIT(12)
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#define MACEPCI_SHARED0_INT BIT(13)
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#define MACEPCI_SHARED1_INT BIT(14)
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#define MACEPCI_SHARED2_INT BIT(15)
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#define CRIME_GBE0_INT BIT(16)
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#define CRIME_GBE1_INT BIT(17)
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#define CRIME_GBE2_INT BIT(18)
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#define CRIME_GBE3_INT BIT(19)
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#define CRIME_CPUERR_INT BIT(20)
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#define CRIME_MEMERR_INT BIT(21)
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#define CRIME_RE_EMPTY_E_INT BIT(22)
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#define CRIME_RE_FULL_E_INT BIT(23)
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#define CRIME_RE_IDLE_E_INT BIT(24)
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#define CRIME_RE_EMPTY_L_INT BIT(25)
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#define CRIME_RE_FULL_L_INT BIT(26)
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#define CRIME_RE_IDLE_L_INT BIT(27)
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#define CRIME_SOFT0_INT BIT(28)
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#define CRIME_SOFT1_INT BIT(29)
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#define CRIME_SOFT2_INT BIT(30)
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#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
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#define CRIME_VICE_INT BIT(31)
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/* Masks for deciding who handles the interrupt */
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#define CRIME_MACE_INT_MASK 0x8f
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#define CRIME_MACEISA_INT_MASK 0x70
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#define CRIME_MACEPCI_INT_MASK 0xff00
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#define CRIME_CRIME_INT_MASK 0xffff0000
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volatile unsigned long watchdog;
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#define CRIME_DOG_POWER_ON_RESET 0x00010000
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#define CRIME_DOG_WARM_RESET 0x00080000
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#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
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#define CRIME_DOG_VALUE 0x00007fff
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volatile unsigned long timer;
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#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
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#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
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volatile unsigned long cpu_error_addr;
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#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
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volatile unsigned long cpu_error_stat;
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#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */
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#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
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#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
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#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
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unsigned long _pad0[54];
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volatile unsigned long mc_ctrl;
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volatile unsigned long bank_ctrl[8];
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#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */
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#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
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#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
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#define CRIME_MAXBANKS 8
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volatile unsigned long mem_ref_counter;
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#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */
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volatile unsigned long mem_error_stat;
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#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
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#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
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#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
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#define CRIME_MEM_ERROR_RE_ID 0x00007f00
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#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
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#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
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#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
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#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
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#define CRIME_MEM_ERROR_RESERVED 0x00080000
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#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
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#define CRIME_MEM_ERROR_HARD_ERR 0x00200000
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#define CRIME_MEM_ERROR_MULTIPLE 0x00400000
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#define CRIME_MEM_ERROR_ECC 0x01800000
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#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
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#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
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#define CRIME_MEM_ERROR_INV 0x0e000000
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#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
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#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
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#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
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volatile unsigned long mem_error_addr;
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#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
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volatile unsigned long mem_ecc_syn;
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#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
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volatile unsigned long mem_ecc_chk;
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#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
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volatile unsigned long mem_ecc_repl;
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#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
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};
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extern struct sgi_crime __iomem *crime;
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#define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */
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#endif /* __ASM_CRIME_H__ */
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