// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi MIPS SoC support
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <asm/machine.h>
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#include <asm/prom.h>
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#define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x71070000
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#define CHIP_ID_PART_ID GENMASK(27, 12)
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#define OCELOT_PART_ID (0x7514 << 12)
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#define UART_UART 0x70100000
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static __init bool ocelot_detect(void)
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{
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u32 rev;
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int idx;
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/* Look for the TLB entry set up by redboot before trying to use it */
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write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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if (idx < 0)
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return 0;
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/* A TLB entry exists, lets assume its usable and check the CHIP ID */
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rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
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if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
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return 0;
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/* Copy command line from bootloader early for Initrd detection */
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if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
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unsigned int prom_argc = fw_arg0;
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const char **prom_argv = (const char **)fw_arg1;
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if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
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/* ignore all built-in args if any f/w args given */
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strcpy(arcs_cmdline, prom_argv[1]);
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}
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return 1;
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}
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static void __init ocelot_earlyprintk_init(void)
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{
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void __iomem *uart_base;
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uart_base = ioremap_nocache(UART_UART, 0x20);
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setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
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}
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static void __init ocelot_late_init(void)
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{
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ocelot_earlyprintk_init();
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}
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static __init const void *ocelot_fixup_fdt(const void *fdt,
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const void *match_data)
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{
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/* This has to be done so late because ioremap needs to work */
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late_time_init = ocelot_late_init;
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return fdt;
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}
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extern char __dtb_ocelot_pcb123_begin[];
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MIPS_MACHINE(ocelot) = {
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.fdt = __dtb_ocelot_pcb123_begin,
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.fixup_fdt = ocelot_fixup_fdt,
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.detect = ocelot_detect,
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};
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