/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/* First 4KB has trampoline code for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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#include "socfpga.dtsi"
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/ {
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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mmc0: dwmmc0@ff704000 {
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broken-cd;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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&watchdog0 {
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status = "okay";
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};
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